[{"id":3675136,"web_url":"http://patchwork.ozlabs.org/comment/3675136/","msgid":"<14d1214a-f787-44eb-b66e-2f6d26deba42@linaro.org>","list_archive_url":null,"date":"2026-04-09T08:00:52","subject":"Re: [PATCH 2/4] arm: meson: enable SYSRESET_PSCI","submitter":{"id":84903,"url":"http://patchwork.ozlabs.org/api/people/84903/","name":"Neil Armstrong","email":"neil.armstrong@linaro.org"},"content":"On 4/8/26 22:30, Ferass El Hafidi wrote:\n> Previously, Amlogic SoCs defined their own reset_cpu() implementation\n> that essentially just did what the sysreset PSCI driver already\n> supports. To reduce duplication (and allow for EFI Capsule on Disk\n> support), make use of it instead of a board-specific reset_cpu.\n> \n> This does not affect SPL, as in that stage we do not actually have PSCI\n> (BL31 is not loaded yet at that point).\n> \n> Signed-off-by: Ferass El Hafidi \n> ---\n> arch/arm/mach-meson/Kconfig | 2 ++\n> 1 file changed, 2 insertions(+)\n> \n> diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig\n> index ef86129b535..a615d871095 100644\n> --- a/arch/arm/mach-meson/Kconfig\n> +++ b/arch/arm/mach-meson/Kconfig\n> @@ -7,6 +7,8 @@ config MESON64_COMMON\n> \tselect DM\n> \tselect DM_SERIAL\n> \tselect SYSCON\n> +\tselect SYSRESET\n> +\tselect SYSRESET_PSCI\n> \tselect REGMAP\n> \tselect PWRSEQ\n> \tselect MMC_PWRSEQ\n> \n\nReviewed-by: Neil Armstrong \n\nThanks,\nNeil","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=HpVpB3vR;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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