[{"id":3675611,"web_url":"http://patchwork.ozlabs.org/comment/3675611/","msgid":"","list_archive_url":null,"date":"2026-04-10T02:28:07","subject":"Re: [PATCH qemu v2 1/7] Rename ibex_uart to ot_uart","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Thu, Apr 9, 2026 at 5:37 AM ~lexbaileylowrisc\n wrote:\n>\n> From: Lex Bailey \n>\n> This UART device is not specifically tied to ibex. Currently it is only used in the\n> opentitan machine, which does use an ibex core, but an opentitan machine with a\n> different core would still use this UART, hence it should be considered a part of\n> opentitan more than a part of ibex.\n>\n> Signed-off-by: Lex Bailey \n\nReviewed-by: Alistair Francis \n\nAlistair\n\n> ---\n> MAINTAINERS | 1 +\n> hw/char/Kconfig | 3 +\n> hw/char/meson.build | 2 +-\n> hw/char/{ibex_uart.c => ot_uart.c} | 177 ++++++++++-----------\n> hw/riscv/Kconfig | 1 +\n> hw/riscv/opentitan.c | 2 +-\n> include/hw/char/{ibex_uart.h => ot_uart.h} | 20 +--\n> include/hw/riscv/opentitan.h | 4 +-\n> 8 files changed, 107 insertions(+), 103 deletions(-)\n> rename hw/char/{ibex_uart.c => ot_uart.c} (75%)\n> rename include/hw/char/{ibex_uart.h => ot_uart.h} (84%)\n>\n> diff --git a/MAINTAINERS b/MAINTAINERS\n> index ad215eced8..9bd0b98f09 100644\n> --- a/MAINTAINERS\n> +++ b/MAINTAINERS\n> @@ -1719,6 +1719,7 @@ L: qemu-riscv@nongnu.org\n> S: Supported\n> F: hw/riscv/opentitan.c\n> F: hw/*/ibex_*.c\n> +F: hw/*/ot_*.c\n> F: include/hw/riscv/opentitan.h\n> F: include/hw/*/ibex_*.h\n>\n> diff --git a/hw/char/Kconfig b/hw/char/Kconfig\n> index 020c0a84bb..23ddab6b78 100644\n> --- a/hw/char/Kconfig\n> +++ b/hw/char/Kconfig\n> @@ -95,3 +95,6 @@ config IP_OCTAL_232\n> bool\n> default y\n> depends on IPACK\n> +\n> +config OT_UART\n> + bool\n> diff --git a/hw/char/meson.build b/hw/char/meson.build\n> index fc3d7ee506..056153085f 100644\n> --- a/hw/char/meson.build\n> +++ b/hw/char/meson.build\n> @@ -2,7 +2,7 @@ system_ss.add(when: 'CONFIG_CADENCE', if_true: files('cadence_uart.c'))\n> system_ss.add(when: 'CONFIG_CMSDK_APB_UART', if_true: files('cmsdk-apb-uart.c'))\n> system_ss.add(when: 'CONFIG_ESCC', if_true: files('escc.c'))\n> system_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_apbuart.c'))\n> -system_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_uart.c'))\n> +system_ss.add(when: 'CONFIG_OT_UART', if_true: files('ot_uart.c'))\n> system_ss.add(when: 'CONFIG_IMX', if_true: files('imx_serial.c'))\n> system_ss.add(when: 'CONFIG_IP_OCTAL_232', if_true: files('ipoctal232.c'))\n> system_ss.add(when: 'CONFIG_ISA_BUS', if_true: files('parallel-isa.c'))\n> diff --git a/hw/char/ibex_uart.c b/hw/char/ot_uart.c\n> similarity index 75%\n> rename from hw/char/ibex_uart.c\n> rename to hw/char/ot_uart.c\n> index 26ed1aea14..b3eb619641 100644\n> --- a/hw/char/ibex_uart.c\n> +++ b/hw/char/ot_uart.c\n> @@ -1,5 +1,5 @@\n> /*\n> - * QEMU lowRISC Ibex UART device\n> + * QEMU OpenTitan UART device\n> *\n> * Copyright (c) 2020 Western Digital\n> *\n> @@ -26,7 +26,7 @@\n> */\n>\n> #include \"qemu/osdep.h\"\n> -#include \"hw/char/ibex_uart.h\"\n> +#include \"hw/char/ot_uart.h\"\n> #include \"hw/core/irq.h\"\n> #include \"hw/core/qdev-clock.h\"\n> #include \"hw/core/qdev-properties.h\"\n> @@ -74,7 +74,7 @@ REG32(OVRD, 0x28)\n> REG32(VAL, 0x2C)\n> REG32(TIMEOUT_CTRL, 0x30)\n>\n> -static void ibex_uart_update_irqs(IbexUartState *s)\n> +static void ot_uart_update_irqs(OtUARTState *s)\n> {\n> if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_WATERMARK_MASK) {\n> qemu_set_irq(s->tx_watermark, 1);\n> @@ -101,9 +101,9 @@ static void ibex_uart_update_irqs(IbexUartState *s)\n> }\n> }\n>\n> -static int ibex_uart_can_receive(void *opaque)\n> +static int ot_uart_can_receive(void *opaque)\n> {\n> - IbexUartState *s = opaque;\n> + OtUARTState *s = opaque;\n>\n> if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK)\n> && !(s->uart_status & R_STATUS_RXFULL_MASK)) {\n> @@ -113,9 +113,9 @@ static int ibex_uart_can_receive(void *opaque)\n> return 0;\n> }\n>\n> -static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)\n> +static void ot_uart_receive(void *opaque, const uint8_t *buf, int size)\n> {\n> - IbexUartState *s = opaque;\n> + OtUARTState *s = opaque;\n> uint8_t rx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_RXILVL_MASK)\n> >> R_FIFO_CTRL_RXILVL_SHIFT;\n>\n> @@ -133,13 +133,13 @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)\n> s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;\n> }\n>\n> - ibex_uart_update_irqs(s);\n> + ot_uart_update_irqs(s);\n> }\n>\n> -static gboolean ibex_uart_xmit(void *do_not_use, GIOCondition cond,\n> - void *opaque)\n> +static gboolean ot_uart_xmit(void *do_not_use, GIOCondition cond,\n> + void *opaque)\n> {\n> - IbexUartState *s = opaque;\n> + OtUARTState *s = opaque;\n> uint8_t tx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_TXILVL_MASK)\n> >> R_FIFO_CTRL_TXILVL_SHIFT;\n> int ret;\n> @@ -155,7 +155,7 @@ static gboolean ibex_uart_xmit(void *do_not_use, GIOCondition cond,\n> s->uart_status |= R_STATUS_TXEMPTY_MASK;\n> s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK;\n> s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK;\n> - ibex_uart_update_irqs(s);\n> + ot_uart_update_irqs(s);\n> return G_SOURCE_REMOVE;\n> }\n>\n> @@ -168,7 +168,7 @@ static gboolean ibex_uart_xmit(void *do_not_use, GIOCondition cond,\n>\n> if (s->tx_level) {\n> guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,\n> - ibex_uart_xmit, s);\n> + ot_uart_xmit, s);\n> if (!r) {\n> s->tx_level = 0;\n> return G_SOURCE_REMOVE;\n> @@ -176,7 +176,7 @@ static gboolean ibex_uart_xmit(void *do_not_use, GIOCondition cond,\n> }\n>\n> /* Clear the TX Full bit */\n> - if (s->tx_level != IBEX_UART_TX_FIFO_SIZE) {\n> + if (s->tx_level != OT_UART_TX_FIFO_SIZE) {\n> s->uart_status &= ~R_STATUS_TXFULL_MASK;\n> }\n>\n> @@ -191,20 +191,20 @@ static gboolean ibex_uart_xmit(void *do_not_use, GIOCondition cond,\n> s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK;\n> }\n>\n> - ibex_uart_update_irqs(s);\n> + ot_uart_update_irqs(s);\n> return G_SOURCE_REMOVE;\n> }\n>\n> -static void uart_write_tx_fifo(IbexUartState *s, const uint8_t *buf,\n> +static void uart_write_tx_fifo(OtUARTState *s, const uint8_t *buf,\n> int size)\n> {\n> uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);\n> uint8_t tx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_TXILVL_MASK)\n> >> R_FIFO_CTRL_TXILVL_SHIFT;\n>\n> - if (size > IBEX_UART_TX_FIFO_SIZE - s->tx_level) {\n> - size = IBEX_UART_TX_FIFO_SIZE - s->tx_level;\n> - qemu_log_mask(LOG_GUEST_ERROR, \"ibex_uart: TX FIFO overflow\");\n> + if (size > OT_UART_TX_FIFO_SIZE - s->tx_level) {\n> + size = OT_UART_TX_FIFO_SIZE - s->tx_level;\n> + qemu_log_mask(LOG_GUEST_ERROR, \"ot_uart: TX FIFO overflow\");\n> }\n>\n> memcpy(s->tx_fifo + s->tx_level, buf, size);\n> @@ -216,10 +216,10 @@ static void uart_write_tx_fifo(IbexUartState *s, const uint8_t *buf,\n>\n> if (s->tx_level >= tx_fifo_level) {\n> s->uart_intr_state |= R_INTR_STATE_TX_WATERMARK_MASK;\n> - ibex_uart_update_irqs(s);\n> + ot_uart_update_irqs(s);\n> }\n>\n> - if (s->tx_level == IBEX_UART_TX_FIFO_SIZE) {\n> + if (s->tx_level == OT_UART_TX_FIFO_SIZE) {\n> s->uart_status |= R_STATUS_TXFULL_MASK;\n> }\n>\n> @@ -227,9 +227,9 @@ static void uart_write_tx_fifo(IbexUartState *s, const uint8_t *buf,\n> (s->char_tx_time * 4));\n> }\n>\n> -static void ibex_uart_reset(DeviceState *dev)\n> +static void ot_uart_reset(DeviceState *dev)\n> {\n> - IbexUartState *s = IBEX_UART(dev);\n> + OtUARTState *s = OT_UART(dev);\n>\n> s->uart_intr_state = 0x00000000;\n> s->uart_intr_state = 0x00000000;\n> @@ -248,10 +248,10 @@ static void ibex_uart_reset(DeviceState *dev)\n>\n> s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;\n>\n> - ibex_uart_update_irqs(s);\n> + ot_uart_update_irqs(s);\n> }\n>\n> -static uint64_t ibex_uart_get_baud(IbexUartState *s)\n> +static uint64_t ot_uart_get_baud(OtUARTState *s)\n> {\n> uint64_t baud;\n>\n> @@ -262,10 +262,9 @@ static uint64_t ibex_uart_get_baud(IbexUartState *s)\n> return baud;\n> }\n>\n> -static uint64_t ibex_uart_read(void *opaque, hwaddr addr,\n> - unsigned int size)\n> +static uint64_t ot_uart_read(void *opaque, hwaddr addr, unsigned int size)\n> {\n> - IbexUartState *s = opaque;\n> + OtUARTState *s = opaque;\n> uint64_t retvalue = 0;\n>\n> switch (addr >> 2) {\n> @@ -342,25 +341,25 @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,\n> return retvalue;\n> }\n>\n> -static void ibex_uart_write(void *opaque, hwaddr addr,\n> - uint64_t val64, unsigned int size)\n> +static void ot_uart_write(void *opaque, hwaddr addr, uint64_t val64,\n> + unsigned int size)\n> {\n> - IbexUartState *s = opaque;\n> + OtUARTState *s = opaque;\n> uint32_t value = val64;\n>\n> switch (addr >> 2) {\n> case R_INTR_STATE:\n> /* Write 1 clear */\n> s->uart_intr_state &= ~value;\n> - ibex_uart_update_irqs(s);\n> + ot_uart_update_irqs(s);\n> break;\n> case R_INTR_ENABLE:\n> s->uart_intr_enable = value;\n> - ibex_uart_update_irqs(s);\n> + ot_uart_update_irqs(s);\n> break;\n> case R_INTR_TEST:\n> s->uart_intr_state |= value;\n> - ibex_uart_update_irqs(s);\n> + ot_uart_update_irqs(s);\n> break;\n>\n> case R_CTRL:\n> @@ -393,7 +392,7 @@ static void ibex_uart_write(void *opaque, hwaddr addr,\n> \"%s: UART_CTRL_RXBLVL is not supported\\n\", __func__);\n> }\n> if (value & R_CTRL_NCO_MASK) {\n> - uint64_t baud = ibex_uart_get_baud(s);\n> + uint64_t baud = ot_uart_get_baud(s);\n>\n> s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10;\n> }\n> @@ -448,122 +447,122 @@ static void ibex_uart_write(void *opaque, hwaddr addr,\n> }\n> }\n>\n> -static void ibex_uart_clk_update(void *opaque, ClockEvent event)\n> +static void ot_uart_clk_update(void *opaque, ClockEvent event)\n> {\n> - IbexUartState *s = opaque;\n> + OtUARTState *s = opaque;\n>\n> /* recompute uart's speed on clock change */\n> - uint64_t baud = ibex_uart_get_baud(s);\n> + uint64_t baud = ot_uart_get_baud(s);\n>\n> s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10;\n> }\n>\n> static void fifo_trigger_update(void *opaque)\n> {\n> - IbexUartState *s = opaque;\n> + OtUARTState *s = opaque;\n>\n> if (s->uart_ctrl & R_CTRL_TX_ENABLE_MASK) {\n> - ibex_uart_xmit(NULL, G_IO_OUT, s);\n> + ot_uart_xmit(NULL, G_IO_OUT, s);\n> }\n> }\n>\n> -static const MemoryRegionOps ibex_uart_ops = {\n> - .read = ibex_uart_read,\n> - .write = ibex_uart_write,\n> +static const MemoryRegionOps ot_uart_ops = {\n> + .read = ot_uart_read,\n> + .write = ot_uart_write,\n> .endianness = DEVICE_LITTLE_ENDIAN,\n> .impl.min_access_size = 4,\n> .impl.max_access_size = 4,\n> };\n>\n> -static int ibex_uart_post_load(void *opaque, int version_id)\n> +static int ot_uart_post_load(void *opaque, int version_id)\n> {\n> - IbexUartState *s = opaque;\n> + OtUARTState *s = opaque;\n>\n> - ibex_uart_update_irqs(s);\n> + ot_uart_update_irqs(s);\n> return 0;\n> }\n>\n> -static const VMStateDescription vmstate_ibex_uart = {\n> - .name = TYPE_IBEX_UART,\n> +static const VMStateDescription vmstate_ot_uart = {\n> + .name = TYPE_OT_UART,\n> .version_id = 1,\n> .minimum_version_id = 1,\n> - .post_load = ibex_uart_post_load,\n> + .post_load = ot_uart_post_load,\n> .fields = (const VMStateField[]) {\n> - VMSTATE_UINT8_ARRAY(tx_fifo, IbexUartState,\n> - IBEX_UART_TX_FIFO_SIZE),\n> - VMSTATE_UINT32(tx_level, IbexUartState),\n> - VMSTATE_UINT64(char_tx_time, IbexUartState),\n> - VMSTATE_TIMER_PTR(fifo_trigger_handle, IbexUartState),\n> - VMSTATE_UINT32(uart_intr_state, IbexUartState),\n> - VMSTATE_UINT32(uart_intr_enable, IbexUartState),\n> - VMSTATE_UINT32(uart_ctrl, IbexUartState),\n> - VMSTATE_UINT32(uart_status, IbexUartState),\n> - VMSTATE_UINT32(uart_rdata, IbexUartState),\n> - VMSTATE_UINT32(uart_fifo_ctrl, IbexUartState),\n> - VMSTATE_UINT32(uart_fifo_status, IbexUartState),\n> - VMSTATE_UINT32(uart_ovrd, IbexUartState),\n> - VMSTATE_UINT32(uart_val, IbexUartState),\n> - VMSTATE_UINT32(uart_timeout_ctrl, IbexUartState),\n> + VMSTATE_UINT8_ARRAY(tx_fifo, OtUARTState,\n> + OT_UART_TX_FIFO_SIZE),\n> + VMSTATE_UINT32(tx_level, OtUARTState),\n> + VMSTATE_UINT64(char_tx_time, OtUARTState),\n> + VMSTATE_TIMER_PTR(fifo_trigger_handle, OtUARTState),\n> + VMSTATE_UINT32(uart_intr_state, OtUARTState),\n> + VMSTATE_UINT32(uart_intr_enable, OtUARTState),\n> + VMSTATE_UINT32(uart_ctrl, OtUARTState),\n> + VMSTATE_UINT32(uart_status, OtUARTState),\n> + VMSTATE_UINT32(uart_rdata, OtUARTState),\n> + VMSTATE_UINT32(uart_fifo_ctrl, OtUARTState),\n> + VMSTATE_UINT32(uart_fifo_status, OtUARTState),\n> + VMSTATE_UINT32(uart_ovrd, OtUARTState),\n> + VMSTATE_UINT32(uart_val, OtUARTState),\n> + VMSTATE_UINT32(uart_timeout_ctrl, OtUARTState),\n> VMSTATE_END_OF_LIST()\n> }\n> };\n>\n> -static const Property ibex_uart_properties[] = {\n> - DEFINE_PROP_CHR(\"chardev\", IbexUartState, chr),\n> +static const Property ot_uart_properties[] = {\n> + DEFINE_PROP_CHR(\"chardev\", OtUARTState, chr),\n> };\n>\n> -static void ibex_uart_init(Object *obj)\n> +static void ot_uart_init(Object *obj)\n> {\n> - IbexUartState *s = IBEX_UART(obj);\n> + OtUARTState *s = OT_UART(obj);\n>\n> s->f_clk = qdev_init_clock_in(DEVICE(obj), \"f_clock\",\n> - ibex_uart_clk_update, s, ClockUpdate);\n> - clock_set_hz(s->f_clk, IBEX_UART_CLOCK);\n> + ot_uart_clk_update, s, ClockUpdate);\n> + clock_set_hz(s->f_clk, OT_UART_CLOCK);\n>\n> sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_watermark);\n> sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_watermark);\n> sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_empty);\n> sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_overflow);\n>\n> - memory_region_init_io(&s->mmio, obj, &ibex_uart_ops, s,\n> - TYPE_IBEX_UART, 0x400);\n> + memory_region_init_io(&s->mmio, obj, &ot_uart_ops, s,\n> + TYPE_OT_UART, 0x400);\n> sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);\n> }\n>\n> -static void ibex_uart_realize(DeviceState *dev, Error **errp)\n> +static void ot_uart_realize(DeviceState *dev, Error **errp)\n> {\n> - IbexUartState *s = IBEX_UART(dev);\n> + OtUARTState *s = OT_UART(dev);\n>\n> s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,\n> fifo_trigger_update, s);\n>\n> - qemu_chr_fe_set_handlers(&s->chr, ibex_uart_can_receive,\n> - ibex_uart_receive, NULL, NULL,\n> + qemu_chr_fe_set_handlers(&s->chr, ot_uart_can_receive,\n> + ot_uart_receive, NULL, NULL,\n> s, NULL, true);\n> }\n>\n> -static void ibex_uart_class_init(ObjectClass *klass, const void *data)\n> +static void ot_uart_class_init(ObjectClass *klass, const void *data)\n> {\n> DeviceClass *dc = DEVICE_CLASS(klass);\n>\n> - device_class_set_legacy_reset(dc, ibex_uart_reset);\n> - dc->realize = ibex_uart_realize;\n> - dc->vmsd = &vmstate_ibex_uart;\n> - device_class_set_props(dc, ibex_uart_properties);\n> + device_class_set_legacy_reset(dc, ot_uart_reset);\n> + dc->realize = ot_uart_realize;\n> + dc->vmsd = &vmstate_ot_uart;\n> + device_class_set_props(dc, ot_uart_properties);\n> set_bit(DEVICE_CATEGORY_INPUT, dc->categories);\n> }\n>\n> -static const TypeInfo ibex_uart_info = {\n> - .name = TYPE_IBEX_UART,\n> +static const TypeInfo ot_uart_info = {\n> + .name = TYPE_OT_UART,\n> .parent = TYPE_SYS_BUS_DEVICE,\n> - .instance_size = sizeof(IbexUartState),\n> - .instance_init = ibex_uart_init,\n> - .class_init = ibex_uart_class_init,\n> + .instance_size = sizeof(OtUARTState),\n> + .instance_init = ot_uart_init,\n> + .class_init = ot_uart_class_init,\n> };\n>\n> -static void ibex_uart_register_types(void)\n> +static void ot_uart_register_types(void)\n> {\n> - type_register_static(&ibex_uart_info);\n> + type_register_static(&ot_uart_info);\n> }\n>\n> -type_init(ibex_uart_register_types)\n> +type_init(ot_uart_register_types)\n> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig\n> index 0222c93f87..cb4bb5f442 100644\n> --- a/hw/riscv/Kconfig\n> +++ b/hw/riscv/Kconfig\n> @@ -38,6 +38,7 @@ config OPENTITAN\n> default y\n> depends on RISCV32\n> select IBEX\n> + select OT_UART\n> select SIFIVE_PLIC\n> select UNIMP\n>\n> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c\n> index 309125e854..97c33d1b53 100644\n> --- a/hw/riscv/opentitan.c\n> +++ b/hw/riscv/opentitan.c\n> @@ -132,7 +132,7 @@ static void lowrisc_ibex_soc_init(Object *obj)\n>\n> object_initialize_child(obj, \"plic\", &s->plic, TYPE_SIFIVE_PLIC);\n>\n> - object_initialize_child(obj, \"uart\", &s->uart, TYPE_IBEX_UART);\n> + object_initialize_child(obj, \"uart\", &s->uart, TYPE_OT_UART);\n>\n> object_initialize_child(obj, \"timer\", &s->timer, TYPE_IBEX_TIMER);\n>\n> diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ot_uart.h\n> similarity index 84%\n> rename from include/hw/char/ibex_uart.h\n> rename to include/hw/char/ot_uart.h\n> index 882796e0c6..517324b65d 100644\n> --- a/include/hw/char/ibex_uart.h\n> +++ b/include/hw/char/ot_uart.h\n> @@ -1,5 +1,5 @@\n> /*\n> - * QEMU lowRISC Ibex UART device\n> + * QEMU OpenTitan UART device\n> *\n> * Copyright (c) 2020 Western Digital\n> *\n> @@ -22,28 +22,28 @@\n> * THE SOFTWARE.\n> */\n>\n> -#ifndef HW_IBEX_UART_H\n> -#define HW_IBEX_UART_H\n> +#ifndef HW_OT_UART_H\n> +#define HW_OT_UART_H\n>\n> #include \"hw/core/sysbus.h\"\n> #include \"chardev/char-fe.h\"\n> #include \"qemu/timer.h\"\n> #include \"qom/object.h\"\n>\n> -#define IBEX_UART_TX_FIFO_SIZE 16\n> -#define IBEX_UART_CLOCK 50000000 /* 50MHz clock */\n> +#define OT_UART_TX_FIFO_SIZE 16\n> +#define OT_UART_CLOCK 50000000 /* 50MHz clock */\n>\n> -#define TYPE_IBEX_UART \"ibex-uart\"\n> -OBJECT_DECLARE_SIMPLE_TYPE(IbexUartState, IBEX_UART)\n> +#define TYPE_OT_UART \"ot-uart\"\n> +OBJECT_DECLARE_SIMPLE_TYPE(OtUARTState, OT_UART)\n>\n> -struct IbexUartState {\n> +struct OtUARTState {\n> /* */\n> SysBusDevice parent_obj;\n>\n> /* */\n> MemoryRegion mmio;\n>\n> - uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];\n> + uint8_t tx_fifo[OT_UART_TX_FIFO_SIZE];\n> uint32_t tx_level;\n>\n> uint32_t rx_level;\n> @@ -70,4 +70,4 @@ struct IbexUartState {\n> qemu_irq tx_empty;\n> qemu_irq rx_overflow;\n> };\n> -#endif /* HW_IBEX_UART_H */\n> +#endif /* HW_OT_UART_H */\n> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h\n> index 5b9016e1d8..f2b4bf3814 100644\n> --- a/include/hw/riscv/opentitan.h\n> +++ b/include/hw/riscv/opentitan.h\n> @@ -21,7 +21,7 @@\n>\n> #include \"hw/riscv/riscv_hart.h\"\n> #include \"hw/intc/sifive_plic.h\"\n> -#include \"hw/char/ibex_uart.h\"\n> +#include \"hw/char/ot_uart.h\"\n> #include \"hw/timer/ibex_timer.h\"\n> #include \"hw/ssi/ibex_spi_host.h\"\n> #include \"hw/core/boards.h\"\n> @@ -43,7 +43,7 @@ struct LowRISCIbexSoCState {\n> /*< public >*/\n> RISCVHartArrayState cpus;\n> SiFivePLICState plic;\n> - IbexUartState uart;\n> + OtUARTState uart;\n> IbexTimerState timer;\n> IbexSPIHostState spi_host[OPENTITAN_NUM_SPI_HOSTS];\n>\n> --\n> 2.49.1\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=K+CLB4WM;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n 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