[{"id":3675618,"web_url":"http://patchwork.ozlabs.org/comment/3675618/","msgid":"","list_archive_url":null,"date":"2026-04-10T03:03:26","subject":"Re: [PATCH qemu v2 4/7] ot_uart: replace individual IRQ fields with\n array, add missing IRQs","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Thu, Apr 9, 2026 at 5:37 AM ~lexbaileylowrisc\n wrote:\n>\n> From: Lex Bailey \n>\n> There are 9 interrupts in the OpenTitan UART device.\n> These are documented here:\n> https://opentitan.org/book/hw/ip/uart/doc/theory_of_operation.html#interrupts\n>\n> This commit removes the individually named interrupts (of which there was only four)\n> and replaces them with an array of 9 interrupts.\n>\n> Signed-off-by: Lex Bailey \n\nReviewed-by: Alistair Francis \n\nAlistair\n\n> ---\n> hw/char/ot_uart.c | 44 +++++++++++++--------------------------\n> include/hw/char/ot_uart.h | 5 +----\n> 2 files changed, 15 insertions(+), 34 deletions(-)\n>\n> diff --git a/hw/char/ot_uart.c b/hw/char/ot_uart.c\n> index 3bf3295b1b..923aab12af 100644\n> --- a/hw/char/ot_uart.c\n> +++ b/hw/char/ot_uart.c\n> @@ -107,6 +107,7 @@ REG32(TIMEOUT_CTRL, 0x30)\n> #define OT_UART_NCO_BITS 16\n> #define OT_UART_TX_FIFO_SIZE 128\n> #define OT_UART_RX_FIFO_SIZE 128\n> +#define OT_UART_IRQ_NUM 9\n>\n> #define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))\n>\n> @@ -116,31 +117,11 @@ REG32(TIMEOUT_CTRL, 0x30)\n>\n> static void ot_uart_update_irqs(OtUARTState *s)\n> {\n> - if (s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE]\n> - & INTR_TX_WATERMARK_MASK) {\n> - qemu_set_irq(s->tx_watermark, 1);\n> - } else {\n> - qemu_set_irq(s->tx_watermark, 0);\n> - }\n> -\n> - if (s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE]\n> - & INTR_RX_WATERMARK_MASK) {\n> - qemu_set_irq(s->rx_watermark, 1);\n> - } else {\n> - qemu_set_irq(s->rx_watermark, 0);\n> - }\n> + uint32_t state_masked = s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE];\n>\n> - if (s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE] & INTR_TX_EMPTY_MASK) {\n> - qemu_set_irq(s->tx_empty, 1);\n> - } else {\n> - qemu_set_irq(s->tx_empty, 0);\n> - }\n> -\n> - if (s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE]\n> - & INTR_RX_OVERFLOW_MASK) {\n> - qemu_set_irq(s->rx_overflow, 1);\n> - } else {\n> - qemu_set_irq(s->rx_overflow, 0);\n> + for (int index = 0; index < OT_UART_IRQ_NUM; index++) {\n> + bool level = (state_masked & (1U << index)) != 0;\n> + qemu_set_irq(s->irqs[index], level);\n> }\n> }\n>\n> @@ -291,6 +272,9 @@ static void ot_uart_reset_enter(Object *obj, ResetType type)\n> s->regs[R_STATUS] = 0x0000003c;\n>\n> s->tx_watermark_level = 0;\n> + for (unsigned index = 0; index < ARRAY_SIZE(s->irqs); index++) {\n> + qemu_set_irq(s->irqs[index], 0);\n> + }\n> ot_uart_reset_tx_fifo(s);\n> ot_uart_reset_rx_fifo(s);\n>\n> @@ -562,21 +546,21 @@ static void ot_uart_init(Object *obj)\n> ot_uart_clk_update, s, ClockUpdate);\n> clock_set_hz(s->f_clk, OT_UART_CLOCK);\n>\n> - sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_watermark);\n> - sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_watermark);\n> - sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_empty);\n> - sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_overflow);\n> + for (unsigned index = 0; index < OT_UART_IRQ_NUM; index++) {\n> + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irqs[index]);\n> + }\n>\n> memory_region_init_io(&s->mmio, obj, &ot_uart_ops, s,\n> TYPE_OT_UART, 0x400);\n> sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);\n>\n> /*\n> - * This array has a fixed size in the header. This assertion is used to\n> - * check that it is consistent with the definition in this file. This is\n> + * These arrays have fixed sizes in the header. These assertions are used to\n> + * check that they are consistent with the definitions in this file. This is\n> * ostensibly a runtime check, but may be optimised away by the compiler.\n> */\n> assert(REGS_SIZE == sizeof(s->regs));\n> + assert(OT_UART_IRQ_NUM * sizeof(qemu_irq) == sizeof(s->irqs));\n> }\n>\n> static void ot_uart_realize(DeviceState *dev, Error **errp)\n> diff --git a/include/hw/char/ot_uart.h b/include/hw/char/ot_uart.h\n> index f489612700..a2c5ff8b33 100644\n> --- a/include/hw/char/ot_uart.h\n> +++ b/include/hw/char/ot_uart.h\n> @@ -42,6 +42,7 @@ struct OtUARTState {\n>\n> /* */\n> MemoryRegion mmio;\n> + qemu_irq irqs[9];\n>\n> uint32_t tx_level;\n>\n> @@ -59,10 +60,6 @@ struct OtUARTState {\n> Clock *f_clk;\n>\n> CharFrontend chr;\n> - qemu_irq tx_watermark;\n> - qemu_irq rx_watermark;\n> - qemu_irq tx_empty;\n> - qemu_irq rx_overflow;\n> };\n>\n> struct OtUARTClass {\n> --\n> 2.49.1\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=pjm6RHFi;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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