[{"id":3675579,"web_url":"http://patchwork.ozlabs.org/comment/3675579/","msgid":"","list_archive_url":null,"date":"2026-04-10T01:02:58","subject":"Re: [PATCH v5 1/6] target/riscv: Add basic definitions and CSRs for\n SMMPT","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Thu, Apr 9, 2026 at 12:07 AM LIU Zhiwei wrote:\n>\n> This patch lays the groundwork for the SMMPT (Supervisor Domains Access\n> Protection) extension by introducing its fundamental components.\n>\n> It adds:\n> - New CPU configuration flags, `ext_smmpt` and `ext_smsdid`, to enable\n> the extension.\n> - Bit-field definitions for the `mmpt` CSR in `cpu_bits.h`.\n> - The `mmpt` and `msdcfg` CSR numbers and their read/write handlers in\n> `csr.c`.\n> - New fields in `CPUArchState` to store the state of these new CSRs.\n> - A new translation failure reason `TRANSLATE_MPT_FAIL`.\n>\n> This provides the necessary infrastructure for the core MPT logic and\n> MMU integration that will follow.\n>\n> Co-authored-by: Huang Tao \n> Co-authored-by: TANG Tiancheng \n> Signed-off-by: LIU Zhiwei \n> Reviewed-by: Daniel Henrique Barboza \n\nAcked-by: Alistair Francis \n\nAlistair\n\n> ---\n> target/riscv/cpu.h | 9 ++-\n> target/riscv/cpu_bits.h | 27 +++++++++\n> target/riscv/cpu_cfg_fields.h.inc | 2 +\n> target/riscv/csr.c | 95 +++++++++++++++++++++++++++++++\n> target/riscv/riscv_smmpt.h | 21 +++++++\n> 5 files changed, 153 insertions(+), 1 deletion(-)\n> create mode 100644 target/riscv/riscv_smmpt.h\n>\n> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\n> index 35d1f6362c..f8265c2cc2 100644\n> --- a/target/riscv/cpu.h\n> +++ b/target/riscv/cpu.h\n> @@ -130,7 +130,8 @@ enum {\n> TRANSLATE_SUCCESS,\n> TRANSLATE_FAIL,\n> TRANSLATE_PMP_FAIL,\n> - TRANSLATE_G_STAGE_FAIL\n> + TRANSLATE_G_STAGE_FAIL,\n> + TRANSLATE_MPT_FAIL\n> };\n>\n> /* Extension context status */\n> @@ -181,6 +182,7 @@ extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[];\n> #if !defined(CONFIG_USER_ONLY)\n> #include \"pmp.h\"\n> #include \"debug.h\"\n> +#include \"riscv_smmpt.h\"\n> #endif\n>\n> #define RV_VLEN_MAX 1024\n> @@ -481,6 +483,11 @@ struct CPUArchState {\n> uint64_t hstateen[SMSTATEEN_MAX_COUNT];\n> uint64_t sstateen[SMSTATEEN_MAX_COUNT];\n> uint64_t henvcfg;\n> + /* Smsdid */\n> + uint32_t mptmode;\n> + uint32_t sdid;\n> + uint64_t mptppn;\n> + uint32_t msdcfg;\n> #endif\n>\n> /* Fields from here on are preserved across CPU reset. */\n> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h\n> index b62dd82fe7..c6a34863d1 100644\n> --- a/target/riscv/cpu_bits.h\n> +++ b/target/riscv/cpu_bits.h\n> @@ -1164,4 +1164,31 @@ typedef enum CTRType {\n> #define MCONTEXT64 0x0000000000001FFFULL\n> #define MCONTEXT32_HCONTEXT 0x0000007F\n> #define MCONTEXT64_HCONTEXT 0x0000000000003FFFULL\n> +\n> +/* Smsdid */\n> +#define CSR_MMPT 0xbc0\n> +#define CSR_MSDCFG 0xbd1\n> +\n> +#define MMPT_MODE_MASK_32 0xC0000000\n> +#define MMPT_SDID_MASK_32 0x3F000000\n> +#define MMPT_PPN_MASK_32 0x003FFFFF\n> +\n> +#define MMPT_MODE_SHIFT_32 30\n> +#define MMPT_SDID_SHIFT_32 24\n> +\n> +#define MMPT_MODE_MASK_64 0xF000000000000000ULL\n> +#define MMPT_SDID_MASK_64 0x0FC0000000000000ULL\n> +#define MMPT_PPN_MASK_64 0x000FFFFFFFFFFFFFULL\n> +\n> +#define MPTE_L3_VALID 0x0000100000000000ULL\n> +#define MPTE_L3_RESERVED 0xFFFFE00000000000ULL\n> +\n> +#define MPTE_L2_RESERVED_64 0xFFFF800000000000ULL\n> +#define MPTE_L2_RESERVED_32 0xFE000000\n> +\n> +#define MPTE_L1_RESERVED_64 0xFFFFFFFF00000000ULL\n> +#define MPTE_L1_RESERVED_32 0xFFFF0000\n> +\n> +#define MMPT_MODE_SHIFT_64 60\n> +#define MMPT_SDID_SHIFT_64 54\n> #endif\n> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc\n> index cd1a5ec56b..80644948dd 100644\n> --- a/target/riscv/cpu_cfg_fields.h.inc\n> +++ b/target/riscv/cpu_cfg_fields.h.inc\n> @@ -63,6 +63,8 @@ BOOL_FIELD(ext_smpmpmt)\n> BOOL_FIELD(ext_svrsw60t59b)\n> BOOL_FIELD(ext_svvptc)\n> BOOL_FIELD(ext_svukte)\n> +BOOL_FIELD(ext_smmpt)\n> +BOOL_FIELD(ext_smsdid)\n> BOOL_FIELD(ext_zdinx)\n> BOOL_FIELD(ext_zaamo)\n> BOOL_FIELD(ext_zacas)\n> diff --git a/target/riscv/csr.c b/target/riscv/csr.c\n> index a75281539b..081d2fc2c3 100644\n> --- a/target/riscv/csr.c\n> +++ b/target/riscv/csr.c\n> @@ -793,6 +793,15 @@ static RISCVException rnmi(CPURISCVState *env, int csrno)\n>\n> return RISCV_EXCP_ILLEGAL_INST;\n> }\n> +\n> +static RISCVException smsdid(CPURISCVState *env, int csrno)\n> +{\n> + if (riscv_cpu_cfg(env)->ext_smsdid) {\n> + return RISCV_EXCP_NONE;\n> + }\n> +\n> + return RISCV_EXCP_ILLEGAL_INST;\n> +}\n> #endif\n>\n> static RISCVException seed(CPURISCVState *env, int csrno)\n> @@ -5446,6 +5455,89 @@ static RISCVException write_mnstatus(CPURISCVState *env, int csrno,\n> return RISCV_EXCP_NONE;\n> }\n>\n> +static RISCVException read_mmpt(CPURISCVState *env, int csrno,\n> + target_ulong *val)\n> +{\n> + if (riscv_cpu_xlen(env) == 32) {\n> + uint32_t value = 0;\n> + value |= env->mptmode << MMPT_MODE_SHIFT_32;\n> + value |= (env->sdid << MMPT_SDID_SHIFT_32) & MMPT_SDID_MASK_32;\n> + value |= env->mptppn & MMPT_PPN_MASK_32;\n> + *val = value;\n> + } else if (riscv_cpu_xlen(env) == 64) {\n> + uint64_t value_64 = 0;\n> + uint32_t mode_value = env->mptmode;\n> + /* mpt_mode_t convert to mmpt.mode value */\n> + if (mode_value) {\n> + mode_value -= SMMPT43 - SMMPT34;\n> + }\n> + value_64 |= (uint64_t)mode_value << MMPT_MODE_SHIFT_64;\n> + value_64 |= ((uint64_t)env->sdid << MMPT_SDID_SHIFT_64)\n> + & MMPT_SDID_MASK_64;\n> + value_64 |= (uint64_t)env->mptppn & MMPT_PPN_MASK_64;\n> + *val = value_64;\n> + } else {\n> + return RISCV_EXCP_ILLEGAL_INST;\n> + }\n> + return RISCV_EXCP_NONE;\n> +}\n> +\n> +static RISCVException write_mmpt(CPURISCVState *env, int csrno,\n> + target_ulong val, uintptr_t ra)\n> +{\n> + uint32_t mode_value = 0;\n> + if (!riscv_cpu_cfg(env)->ext_smmpt) {\n> + goto set_remaining_fields_zero;\n> + }\n> +\n> + if (riscv_cpu_xlen(env) == 32) {\n> + mode_value = (val & MMPT_MODE_MASK_32) >> MMPT_MODE_SHIFT_32;\n> + /* If mode is bare, the remaining fields in mmpt must be zero */\n> + if (mode_value == SMMPTBARE) {\n> + goto set_remaining_fields_zero;\n> + } else if (mode_value <= SMMPT34) {\n> + /* Only write the legal value */\n> + env->mptmode = mode_value;\n> + }\n> + env->sdid = (val & MMPT_SDID_MASK_32) >> MMPT_SDID_SHIFT_32;\n> + env->mptppn = val & MMPT_PPN_MASK_32;\n> + } else if (riscv_cpu_xlen(env) == 64) {\n> + mode_value = (val & MMPT_MODE_MASK_64) >> MMPT_MODE_SHIFT_64;\n> + if (mode_value == SMMPTBARE) {\n> + goto set_remaining_fields_zero;\n> + } else if (mode_value < SMMPTMAX) {\n> + /* convert to mpt_mode_t */\n> + mode_value += SMMPT43 - SMMPT34;\n> + env->mptmode = mode_value;\n> + }\n> + env->sdid = (val & MMPT_SDID_MASK_64) >> MMPT_SDID_SHIFT_64;\n> + env->mptppn = val & MMPT_PPN_MASK_64;\n> + } else {\n> + return RISCV_EXCP_ILLEGAL_INST;\n> + }\n> + return RISCV_EXCP_NONE;\n> +\n> +set_remaining_fields_zero:\n> + env->sdid = 0;\n> + env->mptmode = SMMPTBARE;\n> + env->mptppn = 0;\n> + return RISCV_EXCP_NONE;\n> +}\n> +\n> +static RISCVException read_msdcfg(CPURISCVState *env, int csrno,\n> + target_ulong *val)\n> +{\n> + *val = env->msdcfg;\n> + return RISCV_EXCP_NONE;\n> +}\n> +\n> +static RISCVException write_msdcfg(CPURISCVState *env, int csrno,\n> + target_ulong val, uintptr_t ra)\n> +{\n> + env->msdcfg = val;\n> + return RISCV_EXCP_NONE;\n> +}\n> +\n> #endif\n>\n> /* Crypto Extension */\n> @@ -6660,6 +6752,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {\n> write_mhpmcounterh },\n> [CSR_SCOUNTOVF] = { \"scountovf\", sscofpmf, read_scountovf,\n> .min_priv_ver = PRIV_VERSION_1_12_0 },\n> + /* Supervisor Domain Identifier and Protection Registers */\n> + [CSR_MMPT] = { \"mmpt\", smsdid, read_mmpt, write_mmpt },\n> + [CSR_MSDCFG] = { \"msdcfg\", smsdid, read_msdcfg, write_msdcfg },\n>\n> #endif /* !CONFIG_USER_ONLY */\n> };\n> diff --git a/target/riscv/riscv_smmpt.h b/target/riscv/riscv_smmpt.h\n> new file mode 100644\n> index 0000000000..74dcccf4be\n> --- /dev/null\n> +++ b/target/riscv/riscv_smmpt.h\n> @@ -0,0 +1,21 @@\n> +/*\n> + * QEMU RISC-V Smmpt (Memory Protection Table)\n> + *\n> + * Copyright (c) 2024 Alibaba Group. All rights reserved.\n> + *\n> + * SPDX-License-Identifier: GPL-2.0-or-later\n> + */\n> +\n> +#ifndef RISCV_SMMPT_H\n> +#define RISCV_SMMPT_H\n> +\n> +typedef enum {\n> + SMMPTBARE = 0,\n> + SMMPT34 = 1,\n> + SMMPT43 = 2,\n> + SMMPT52 = 3,\n> + SMMPT64 = 4,\n> + SMMPTMAX\n> +} mpt_mode_t;\n> +\n> +#endif\n> --\n> 2.43.0\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=Zii6M/Fc;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with 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liwei1518@gmail.com,\n Huang Tao ,\n TANG Tiancheng ,\n Daniel Henrique Barboza ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Received-SPF":"pass client-ip=2a00:1450:4864:20::52d;\n envelope-from=alistair23@gmail.com; helo=mail-ed1-x52d.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3676305,"web_url":"http://patchwork.ozlabs.org/comment/3676305/","msgid":"","list_archive_url":null,"date":"2026-04-12T15:27:17","subject":"Re: [PATCH v5 1/6] target/riscv: Add basic definitions and CSRs for\n SMMPT","submitter":{"id":79604,"url":"http://patchwork.ozlabs.org/api/people/79604/","name":"Frank Chang","email":"frank.chang@sifive.com"},"content":"LIU Zhiwei 於 2026年4月9日週四 上午3:39寫道：\n>\n> This patch lays the groundwork for the SMMPT (Supervisor Domains Access\n> Protection) extension by introducing its fundamental components.\n>\n> It adds:\n> - New CPU configuration flags, `ext_smmpt` and `ext_smsdid`, to enable\n> the extension.\n> - Bit-field definitions for the `mmpt` CSR in `cpu_bits.h`.\n> - The `mmpt` and `msdcfg` CSR numbers and their read/write handlers in\n> `csr.c`.\n> - New fields in `CPUArchState` to store the state of these new CSRs.\n> - A new translation failure reason `TRANSLATE_MPT_FAIL`.\n>\n> This provides the necessary infrastructure for the core MPT logic and\n> MMU integration that will follow.\n>\n> Co-authored-by: Huang Tao \n> Co-authored-by: TANG Tiancheng \n> Signed-off-by: LIU Zhiwei \n> Reviewed-by: Daniel Henrique Barboza \n> ---\n> target/riscv/cpu.h | 9 ++-\n> target/riscv/cpu_bits.h | 27 +++++++++\n> target/riscv/cpu_cfg_fields.h.inc | 2 +\n> target/riscv/csr.c | 95 +++++++++++++++++++++++++++++++\n> target/riscv/riscv_smmpt.h | 21 +++++++\n> 5 files changed, 153 insertions(+), 1 deletion(-)\n> create mode 100644 target/riscv/riscv_smmpt.h\n>\n> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\n> index 35d1f6362c..f8265c2cc2 100644\n> --- a/target/riscv/cpu.h\n> +++ b/target/riscv/cpu.h\n> @@ -130,7 +130,8 @@ enum {\n> TRANSLATE_SUCCESS,\n> TRANSLATE_FAIL,\n> TRANSLATE_PMP_FAIL,\n> - TRANSLATE_G_STAGE_FAIL\n> + TRANSLATE_G_STAGE_FAIL,\n> + TRANSLATE_MPT_FAIL\n> };\n>\n> /* Extension context status */\n> @@ -181,6 +182,7 @@ extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[];\n> #if !defined(CONFIG_USER_ONLY)\n> #include \"pmp.h\"\n> #include \"debug.h\"\n> +#include \"riscv_smmpt.h\"\n> #endif\n>\n> #define RV_VLEN_MAX 1024\n> @@ -481,6 +483,11 @@ struct CPUArchState {\n> uint64_t hstateen[SMSTATEEN_MAX_COUNT];\n> uint64_t sstateen[SMSTATEEN_MAX_COUNT];\n> uint64_t henvcfg;\n> + /* Smsdid */\n> + uint32_t mptmode;\n> + uint32_t sdid;\n> + uint64_t mptppn;\n> + uint32_t msdcfg;\n> #endif\n>\n> /* Fields from here on are preserved across CPU reset. */\n> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h\n> index b62dd82fe7..c6a34863d1 100644\n> --- a/target/riscv/cpu_bits.h\n> +++ b/target/riscv/cpu_bits.h\n> @@ -1164,4 +1164,31 @@ typedef enum CTRType {\n> #define MCONTEXT64 0x0000000000001FFFULL\n> #define MCONTEXT32_HCONTEXT 0x0000007F\n> #define MCONTEXT64_HCONTEXT 0x0000000000003FFFULL\n> +\n> +/* Smsdid */\n> +#define CSR_MMPT 0xbc0\n> +#define CSR_MSDCFG 0xbd1\n> +\n> +#define MMPT_MODE_MASK_32 0xC0000000\n> +#define MMPT_SDID_MASK_32 0x3F000000\n> +#define MMPT_PPN_MASK_32 0x003FFFFF\n> +\n> +#define MMPT_MODE_SHIFT_32 30\n> +#define MMPT_SDID_SHIFT_32 24\n> +\n> +#define MMPT_MODE_MASK_64 0xF000000000000000ULL\n> +#define MMPT_SDID_MASK_64 0x0FC0000000000000ULL\n> +#define MMPT_PPN_MASK_64 0x000FFFFFFFFFFFFFULL\n> +\n> +#define MPTE_L3_VALID 0x0000100000000000ULL\n> +#define MPTE_L3_RESERVED 0xFFFFE00000000000ULL\n> +\n> +#define MPTE_L2_RESERVED_64 0xFFFF800000000000ULL\n> +#define MPTE_L2_RESERVED_32 0xFE000000\n> +\n> +#define MPTE_L1_RESERVED_64 0xFFFFFFFF00000000ULL\n> +#define MPTE_L1_RESERVED_32 0xFFFF0000\n\nHi Zhiwei,\n\nMPTE_* fields are not used in the pachset.\n\nOtherwise,\nReviewed-by: Frank Chang \n\n> +\n> +#define MMPT_MODE_SHIFT_64 60\n> +#define MMPT_SDID_SHIFT_64 54\n> #endif\n> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc\n> index cd1a5ec56b..80644948dd 100644\n> --- a/target/riscv/cpu_cfg_fields.h.inc\n> +++ b/target/riscv/cpu_cfg_fields.h.inc\n> @@ -63,6 +63,8 @@ BOOL_FIELD(ext_smpmpmt)\n> BOOL_FIELD(ext_svrsw60t59b)\n> BOOL_FIELD(ext_svvptc)\n> BOOL_FIELD(ext_svukte)\n> +BOOL_FIELD(ext_smmpt)\n> +BOOL_FIELD(ext_smsdid)\n> BOOL_FIELD(ext_zdinx)\n> BOOL_FIELD(ext_zaamo)\n> BOOL_FIELD(ext_zacas)\n> diff --git a/target/riscv/csr.c b/target/riscv/csr.c\n> index a75281539b..081d2fc2c3 100644\n> --- a/target/riscv/csr.c\n> +++ b/target/riscv/csr.c\n> @@ -793,6 +793,15 @@ static RISCVException rnmi(CPURISCVState *env, int csrno)\n>\n> return RISCV_EXCP_ILLEGAL_INST;\n> }\n> +\n> +static RISCVException smsdid(CPURISCVState *env, int csrno)\n> +{\n> + if (riscv_cpu_cfg(env)->ext_smsdid) {\n> + return RISCV_EXCP_NONE;\n> + }\n> +\n> + return RISCV_EXCP_ILLEGAL_INST;\n> +}\n> #endif\n>\n> static RISCVException seed(CPURISCVState *env, int csrno)\n> @@ -5446,6 +5455,89 @@ static RISCVException write_mnstatus(CPURISCVState *env, int csrno,\n> return RISCV_EXCP_NONE;\n> }\n>\n> +static RISCVException read_mmpt(CPURISCVState *env, int csrno,\n> + target_ulong *val)\n> +{\n> + if (riscv_cpu_xlen(env) == 32) {\n> + uint32_t value = 0;\n> + value |= env->mptmode << MMPT_MODE_SHIFT_32;\n> + value |= (env->sdid << MMPT_SDID_SHIFT_32) & MMPT_SDID_MASK_32;\n> + value |= env->mptppn & MMPT_PPN_MASK_32;\n> + *val = value;\n> + } else if (riscv_cpu_xlen(env) == 64) {\n> + uint64_t value_64 = 0;\n> + uint32_t mode_value = env->mptmode;\n> + /* mpt_mode_t convert to mmpt.mode value */\n> + if (mode_value) {\n> + mode_value -= SMMPT43 - SMMPT34;\n> + }\n> + value_64 |= (uint64_t)mode_value << MMPT_MODE_SHIFT_64;\n> + value_64 |= ((uint64_t)env->sdid << MMPT_SDID_SHIFT_64)\n> + & MMPT_SDID_MASK_64;\n> + value_64 |= (uint64_t)env->mptppn & MMPT_PPN_MASK_64;\n> + *val = value_64;\n> + } else {\n> + return RISCV_EXCP_ILLEGAL_INST;\n> + }\n> + return RISCV_EXCP_NONE;\n> +}\n> +\n> +static RISCVException write_mmpt(CPURISCVState *env, int csrno,\n> + target_ulong val, uintptr_t ra)\n> +{\n> + uint32_t mode_value = 0;\n> + if (!riscv_cpu_cfg(env)->ext_smmpt) {\n> + goto set_remaining_fields_zero;\n> + }\n> +\n> + if (riscv_cpu_xlen(env) == 32) {\n> + mode_value = (val & MMPT_MODE_MASK_32) >> MMPT_MODE_SHIFT_32;\n> + /* If mode is bare, the remaining fields in mmpt must be zero */\n> + if (mode_value == SMMPTBARE) {\n> + goto set_remaining_fields_zero;\n> + } else if (mode_value <= SMMPT34) {\n> + /* Only write the legal value */\n> + env->mptmode = mode_value;\n> + }\n> + env->sdid = (val & MMPT_SDID_MASK_32) >> MMPT_SDID_SHIFT_32;\n> + env->mptppn = val & MMPT_PPN_MASK_32;\n> + } else if (riscv_cpu_xlen(env) == 64) {\n> + mode_value = (val & MMPT_MODE_MASK_64) >> MMPT_MODE_SHIFT_64;\n> + if (mode_value == SMMPTBARE) {\n> + goto set_remaining_fields_zero;\n> + } else if (mode_value < SMMPTMAX) {\n> + /* convert to mpt_mode_t */\n> + mode_value += SMMPT43 - SMMPT34;\n> + env->mptmode = mode_value;\n> + }\n> + env->sdid = (val & MMPT_SDID_MASK_64) >> MMPT_SDID_SHIFT_64;\n> + env->mptppn = val & MMPT_PPN_MASK_64;\n> + } else {\n> + return RISCV_EXCP_ILLEGAL_INST;\n> + }\n> + return RISCV_EXCP_NONE;\n> +\n> +set_remaining_fields_zero:\n> + env->sdid = 0;\n> + env->mptmode = SMMPTBARE;\n> + env->mptppn = 0;\n> + return RISCV_EXCP_NONE;\n> +}\n> +\n> +static RISCVException read_msdcfg(CPURISCVState *env, int csrno,\n> + target_ulong *val)\n> +{\n> + *val = env->msdcfg;\n> + return RISCV_EXCP_NONE;\n> +}\n> +\n> +static RISCVException write_msdcfg(CPURISCVState *env, int csrno,\n> + target_ulong val, uintptr_t ra)\n> +{\n> + env->msdcfg = val;\n> + return RISCV_EXCP_NONE;\n> +}\n> +\n> #endif\n>\n> /* Crypto Extension */\n> @@ -6660,6 +6752,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {\n> write_mhpmcounterh },\n> [CSR_SCOUNTOVF] = { \"scountovf\", sscofpmf, read_scountovf,\n> .min_priv_ver = PRIV_VERSION_1_12_0 },\n> + /* Supervisor Domain Identifier and Protection Registers */\n> + [CSR_MMPT] = { \"mmpt\", smsdid, read_mmpt, write_mmpt },\n> + [CSR_MSDCFG] = { \"msdcfg\", smsdid, read_msdcfg, write_msdcfg },\n>\n> #endif /* !CONFIG_USER_ONLY */\n> };\n> diff --git a/target/riscv/riscv_smmpt.h b/target/riscv/riscv_smmpt.h\n> new file mode 100644\n> index 0000000000..74dcccf4be\n> --- /dev/null\n> +++ b/target/riscv/riscv_smmpt.h\n> @@ -0,0 +1,21 @@\n> +/*\n> + * QEMU RISC-V Smmpt (Memory Protection Table)\n> + *\n> + * Copyright (c) 2024 Alibaba Group. All rights reserved.\n> + *\n> + * SPDX-License-Identifier: GPL-2.0-or-later\n> + */\n> +\n> +#ifndef RISCV_SMMPT_H\n> +#define RISCV_SMMPT_H\n> +\n> +typedef enum {\n> + SMMPTBARE = 0,\n> + SMMPT34 = 1,\n> + SMMPT43 = 2,\n> + SMMPT52 = 3,\n> + SMMPT64 = 4,\n> + SMMPTMAX\n> +} mpt_mode_t;\n> +\n> +#endif\n> --\n> 2.43.0\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=K6ThKRBO;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 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client-ip=2607:f8b0:4864:20::1032;\n envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1032.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3676445,"web_url":"http://patchwork.ozlabs.org/comment/3676445/","msgid":"","list_archive_url":null,"date":"2026-04-13T04:29:57","subject":"Re: [PATCH v5 1/6] target/riscv: Add basic definitions and CSRs for\n SMMPT","submitter":{"id":91422,"url":"http://patchwork.ozlabs.org/api/people/91422/","name":"Nutty.Liu","email":"nutty.liu@hotmail.com"},"content":"On 4/8/2026 10:06 PM, LIU Zhiwei wrote:\n> This patch lays the groundwork for the SMMPT (Supervisor Domains Access\n> Protection) extension by introducing its fundamental components.\n>\n> It adds:\n> - New CPU configuration flags, `ext_smmpt` and `ext_smsdid`, to enable\n> the extension.\n> - Bit-field definitions for the `mmpt` CSR in `cpu_bits.h`.\n> - The `mmpt` and `msdcfg` CSR numbers and their read/write handlers in\n> `csr.c`.\n> - New fields in `CPUArchState` to store the state of these new CSRs.\n> - A new translation failure reason `TRANSLATE_MPT_FAIL`.\n>\n> This provides the necessary infrastructure for the core MPT logic and\n> MMU integration that will follow.\n>\n> Co-authored-by: Huang Tao \n> Co-authored-by: TANG Tiancheng \n> Signed-off-by: LIU Zhiwei \n> Reviewed-by: Daniel Henrique Barboza \n> ---\n> target/riscv/cpu.h | 9 ++-\n> target/riscv/cpu_bits.h | 27 +++++++++\n> target/riscv/cpu_cfg_fields.h.inc | 2 +\n> target/riscv/csr.c | 95 +++++++++++++++++++++++++++++++\n> target/riscv/riscv_smmpt.h | 21 +++++++\n> 5 files changed, 153 insertions(+), 1 deletion(-)\n> create mode 100644 target/riscv/riscv_smmpt.h\nReviewed-by: Nutty Liu \n\nThanks,\nNutty","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=hotmail.com header.i=@hotmail.com header.a=rsa-sha256\n header.s=selector1 header.b=E7LTmXdf;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org 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