[{"id":3675600,"web_url":"http://patchwork.ozlabs.org/comment/3675600/","msgid":"","list_archive_url":null,"date":"2026-04-10T01:45:40","subject":"Re: [PATCH v5 4/6] target/riscv: Implement SMMPT fence instructions","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Thu, Apr 9, 2026 at 12:08 AM LIU Zhiwei wrote:\n>\n> This patch completes the SMMPT implementation by adding support for the\n> new fence instructions: `mfence.spa` and `minval.spa`.\n>\n> According to the specification, these instructions act as memory ordering\n> fences for MPT updates. In QEMU's TCG model, this is conservatively\n> implemented by flushing the entire TLB, which ensures that any subsequent\n> memory accesses will re-evaluate permissions and see the effects of any prior\n> MPT modifications.\n>\n> The instructions are privileged and will cause an illegal instruction\n> exception if executed outside of M-mode.\n>\n> Co-authored-by: Huang Tao \n> Co-authored-by: TANG Tiancheng \n> Signed-off-by: LIU Zhiwei \n> Reviewed-by: Daniel Henrique Barboza \n\nReviewed-by: Alistair Francis \n\nAlistair\n\n> ---\n> target/riscv/insn32.decode | 2 ++\n> .../riscv/insn_trans/trans_privileged.c.inc | 30 +++++++++++++++++++\n> 2 files changed, 32 insertions(+)\n>\n> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode\n> index 6e35c4b1e6..84cec57daf 100644\n> --- a/target/riscv/insn32.decode\n> +++ b/target/riscv/insn32.decode\n> @@ -120,6 +120,8 @@ sret 0001000 00010 00000 000 00000 1110011\n> mret 0011000 00010 00000 000 00000 1110011\n> wfi 0001000 00101 00000 000 00000 1110011\n> sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma\n> +mfence_spa 1000011 ..... ..... 000 00000 1110011 @sfence_vma\n> +minval_spa 0000011 ..... ..... 000 00000 1110011 @sfence_vma\n>\n> # *** NMI ***\n> mnret 0111000 00010 00000 000 00000 1110011\n> diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc\n> index 8a62b4cfcd..5ec6bf5991 100644\n> --- a/target/riscv/insn_trans/trans_privileged.c.inc\n> +++ b/target/riscv/insn_trans/trans_privileged.c.inc\n> @@ -160,3 +160,33 @@ static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)\n> #endif\n> return false;\n> }\n> +\n> +#define REQUIRE_SMSDID(ctx) do { \\\n> + if (!ctx->cfg_ptr->ext_smsdid) { \\\n> + return false; \\\n> + } \\\n> +} while (0)\n> +\n> +static bool do_mfence_spa(DisasContext *ctx)\n> +{\n> +#ifndef CONFIG_USER_ONLY\n> + REQUIRE_SMSDID(ctx);\n> + if (ctx->priv != PRV_M) {\n> + return false;\n> + }\n> + decode_save_opc(ctx, 0);\n> + gen_helper_tlb_flush_all(tcg_env);\n> + return true;\n> +#endif\n> + return false;\n> +}\n> +\n> +static bool trans_mfence_spa(DisasContext *ctx, arg_mfence_spa *a)\n> +{\n> + return do_mfence_spa(ctx);\n> +}\n> +\n> +static bool trans_minval_spa(DisasContext *ctx, arg_minval_spa *a)\n> +{\n> + return do_mfence_spa(ctx);\n> +}\n> --\n> 2.43.0\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=kA/fTHYR;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Thu, 09 Apr 2026\n 18:46:07 -0700 (PDT)","MIME-Version":"1.0","References":"<20260408140635.42546-1-zhiwei_liu@linux.alibaba.com>\n <20260408140635.42546-5-zhiwei_liu@linux.alibaba.com>","In-Reply-To":"<20260408140635.42546-5-zhiwei_liu@linux.alibaba.com>","From":"Alistair Francis ","Date":"Fri, 10 Apr 2026 11:45:40 +1000","X-Gm-Features":"AQROBzBqoJ7tXl5khSC8HqlK8OpR3lOGe-7FZWCcwcHu5D8d8xnu26uNKatFtxU","Message-ID":"\n ","Subject":"Re: [PATCH v5 4/6] target/riscv: Implement SMMPT fence instructions","To":"LIU Zhiwei ","Cc":"qemu-devel@nongnu.org, qemu-riscv@nongnu.org, chao.liu.zevorn@gmail.com,\n palmer@dabbelt.com, daniel.barboza@oss.qualcomm.com, liwei1518@gmail.com,\n Huang Tao ,\n TANG Tiancheng ,\n Daniel Henrique Barboza ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Received-SPF":"pass client-ip=2a00:1450:4864:20::634;\n envelope-from=alistair23@gmail.com; helo=mail-ej1-x634.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3676548,"web_url":"http://patchwork.ozlabs.org/comment/3676548/","msgid":"","list_archive_url":null,"date":"2026-04-13T08:19:08","subject":"Re: [PATCH v5 4/6] target/riscv: Implement SMMPT fence instructions","submitter":{"id":79604,"url":"http://patchwork.ozlabs.org/api/people/79604/","name":"Frank Chang","email":"frank.chang@sifive.com"},"content":"Hi Zhiwei,\n\nLIU Zhiwei 於 2026年4月9日週四 上午3:24寫道：\n>\n> This patch completes the SMMPT implementation by adding support for the\n> new fence instructions: `mfence.spa` and `minval.spa`.\n>\n> According to the specification, these instructions act as memory ordering\n> fences for MPT updates. In QEMU's TCG model, this is conservatively\n> implemented by flushing the entire TLB, which ensures that any subsequent\n> memory accesses will re-evaluate permissions and see the effects of any prior\n> MPT modifications.\n>\n> The instructions are privileged and will cause an illegal instruction\n> exception if executed outside of M-mode.\n>\n> Co-authored-by: Huang Tao \n> Co-authored-by: TANG Tiancheng \n> Signed-off-by: LIU Zhiwei \n> Reviewed-by: Daniel Henrique Barboza \n> ---\n> target/riscv/insn32.decode | 2 ++\n> .../riscv/insn_trans/trans_privileged.c.inc | 30 +++++++++++++++++++\n> 2 files changed, 32 insertions(+)\n>\n> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode\n> index 6e35c4b1e6..84cec57daf 100644\n> --- a/target/riscv/insn32.decode\n> +++ b/target/riscv/insn32.decode\n> @@ -120,6 +120,8 @@ sret 0001000 00010 00000 000 00000 1110011\n> mret 0011000 00010 00000 000 00000 1110011\n> wfi 0001000 00101 00000 000 00000 1110011\n> sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma\n> +mfence_spa 1000011 ..... ..... 000 00000 1110011 @sfence_vma\n> +minval_spa 0000011 ..... ..... 000 00000 1110011 @sfence_vma\n>\n> # *** NMI ***\n> mnret 0111000 00010 00000 000 00000 1110011\n> diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc\n> index 8a62b4cfcd..5ec6bf5991 100644\n> --- a/target/riscv/insn_trans/trans_privileged.c.inc\n> +++ b/target/riscv/insn_trans/trans_privileged.c.inc\n> @@ -160,3 +160,33 @@ static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)\n> #endif\n> return false;\n> }\n> +\n> +#define REQUIRE_SMSDID(ctx) do { \\\n> + if (!ctx->cfg_ptr->ext_smsdid) { \\\n> + return false; \\\n> + } \\\n> +} while (0)\n> +\n> +static bool do_mfence_spa(DisasContext *ctx)\n> +{\n> +#ifndef CONFIG_USER_ONLY\n> + REQUIRE_SMSDID(ctx);\n> + if (ctx->priv != PRV_M) {\n> + return false;\n> + }\n> + decode_save_opc(ctx, 0);\n> + gen_helper_tlb_flush_all(tcg_env);\n> + return true;\n> +#endif\n> + return false;\n> +}\n> +\n> +static bool trans_mfence_spa(DisasContext *ctx, arg_mfence_spa *a)\n> +{\n> + return do_mfence_spa(ctx);\n> +}\n> +\n> +static bool trans_minval_spa(DisasContext *ctx, arg_minval_spa *a)\n> +{\n> + return do_mfence_spa(ctx);\n> +}\n\nThe spec says that:\n\"When Svinval is implemented with Smsdid, the MINVAL.SPA instruction\nmust be implemented to\nsupport such fine-granular invalidation of physical memory\naccess-permission caches.\"\n\nSo I think we should call REQUIRE_SVINVAL() for MINVAL.SPA.\nHowever, trans_privileged.c.inc is included before trans_svinval.c.inc.\nSo it might be better to separate these instructions into trans_smmpt.c.inc\nand include it after trans_svinval.c.inc.\n\nRegards,\nFrank Chang\n\n> --\n> 2.43.0\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=J9kAr7+K;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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