[{"id":3675599,"web_url":"http://patchwork.ozlabs.org/comment/3675599/","msgid":"","list_archive_url":null,"date":"2026-04-10T01:44:24","subject":"Re: [PATCH v5 3/6] target/riscv: Integrate SMMPT checks into MMU and\n TLB fill","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Thu, Apr 9, 2026 at 12:08 AM LIU Zhiwei wrote:\n>\n> With the core MPT lookup logic in place, this patch integrates the\n> permission checks into QEMU's main MMU processing functions.\n>\n> A new helper, `get_physical_address_mpt`, is introduced to check the\n> permissions for a given physical address against the MPT. This helper\n> is then called at two critical points:\n>\n> 1. During page table walks (`get_physical_address`): The physical\n> address of the Page Table Entry (PTE) itself is checked to ensure\n> the supervisor has permission to read it.\n>\n> 2. After successful address translation (`riscv_cpu_tlb_fill`): The final\n> guest-physical address is checked against the MPT before the access\n> is allowed to proceed.\n>\n> This ensures that SMMPT protection is enforced for both the translation\n> process and the final memory access, as required by the specification.\n>\n> Co-authored-by: Huang Tao \n> Co-authored-by: TANG Tiancheng \n> Signed-off-by: LIU Zhiwei \n> Reviewed-by: Daniel Henrique Barboza \n> ---\n> target/riscv/cpu_helper.c | 76 ++++++++++++++++++++++++++++++++++++++-\n> 1 file changed, 75 insertions(+), 1 deletion(-)\n>\n> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c\n> index e3361fadae..2fab00e9b4 100644\n> --- a/target/riscv/cpu_helper.c\n> +++ b/target/riscv/cpu_helper.c\n> @@ -1161,6 +1161,60 @@ static bool check_svukte_addr(CPURISCVState *env, vaddr addr)\n> return !high_bit;\n> }\n>\n> +/*\n> + * get_physical_address_mpt - check mpt permission for this physical address\n> + *\n> + * Lookup the Memory Protection Table and check permission for this\n> + * physical address. Returns 0 if the permission checking was successful\n> + *\n> + * @env: CPURISCVState\n> + * @prot: The returned protection attributes\n> + * @addr: The physical address to be checked permission\n> + * @access_type: The type of MMU access\n> + * @mode: Indicates current privilege level.\n> + */\n> +static int get_physical_address_mpt(CPURISCVState *env, int *prot, hwaddr addr,\n> + MMUAccessType access_type, int mode)\n> +{\n> + mpt_access_t mpt_access;\n> + bool mpt_has_access;\n> +\n> + /*\n> + * If the extension is not supported or the mmpt.mode is Bare,\n> + * there is no protection, return success.\n> + */\n> + if (!riscv_cpu_cfg(env)->ext_smmpt || env->mptmode == 0) {\n> + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;\n> + return TRANSLATE_SUCCESS;\n> + }\n> +\n> + /*\n> + * MPT is checked for all accesses to physical memory, unless the\n> + * effective privilege mode is M.\n> + *\n> + * Data accesses in M-mode when the MPRV bit in mstatus is set and\n> + * the MPP field in mstatus contains S or U are subject to MPT checks.\n> + *\n> + * In riscv_env_mmu_index, The MPRV and MPP bits are already checked and\n> + * encoded to mmu_idx, So we do not need to check it here.\n> + */\n> + if (mode == PRV_M) {\n> + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;\n> + return TRANSLATE_SUCCESS;\n> + }\n> +\n> + mpt_has_access = smmpt_check_access(env, addr,\n> + &mpt_access, access_type);\n> + if (!mpt_has_access) {\n> + *prot = 0;\n> + return TRANSLATE_MPT_FAIL;\n> + }\n> +\n> + *prot = smmpt_access_to_page_prot(mpt_access);\n> +\n> + return TRANSLATE_SUCCESS;\n> +}\n> +\n> /*\n> * get_physical_address - get the physical address for this virtual address\n> *\n> @@ -1355,6 +1409,13 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,\n> pte_addr = base + idx * ptesize;\n> }\n>\n> + int mpt_prot;\n> + int mpt_ret = get_physical_address_mpt(env, &mpt_prot, pte_addr,\n> + MMU_DATA_LOAD, PRV_S);\n> + if (mpt_ret != TRANSLATE_SUCCESS) {\n> + return TRANSLATE_MPT_FAIL;\n> + }\n> +\n> int pmp_prot;\n> int pmp_ret = get_physical_address_pmp(env, &pmp_prot, pte_addr,\n> sxlen_bytes,\n> @@ -1765,7 +1826,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n> CPURISCVState *env = &cpu->env;\n> vaddr im_address;\n> hwaddr pa = 0;\n> - int prot, prot2, prot_pmp;\n> + int prot, prot2, prot_pmp, mpt_prot;\n> bool pmp_violation = false;\n> bool first_stage_error = true;\n> bool two_stage_lookup = mmuidx_2stage(mmu_idx);\n> @@ -1819,6 +1880,13 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n> prot &= prot2;\n>\n> if (ret == TRANSLATE_SUCCESS) {\n> + ret = get_physical_address_mpt(env, &mpt_prot, pa,\n> + access_type, mode);\n> + qemu_log_mask(CPU_LOG_MMU,\n> + \"%s MPT address=\" HWADDR_FMT_plx \" ret %d prot\"\n> + \" %d\\n\",\n> + __func__, pa, ret, mpt_prot);\n\nWe should only log if the extension is enabled\n\nAlistair","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=DbO1tveA;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Thu, 09 Apr 2026\n 18:44:50 -0700 (PDT)","MIME-Version":"1.0","References":"<20260408140635.42546-1-zhiwei_liu@linux.alibaba.com>\n <20260408140635.42546-4-zhiwei_liu@linux.alibaba.com>","In-Reply-To":"<20260408140635.42546-4-zhiwei_liu@linux.alibaba.com>","From":"Alistair Francis ","Date":"Fri, 10 Apr 2026 11:44:24 +1000","X-Gm-Features":"AQROBzDpV_iVh4rrqz5172hZNcPEZIsOOP4YVkq2NszBw73rYTcuF86betU_J4Q","Message-ID":"\n ","Subject":"Re: [PATCH v5 3/6] target/riscv: Integrate SMMPT checks into MMU and\n TLB fill","To":"LIU Zhiwei ","Cc":"qemu-devel@nongnu.org, qemu-riscv@nongnu.org, chao.liu.zevorn@gmail.com,\n palmer@dabbelt.com, daniel.barboza@oss.qualcomm.com, liwei1518@gmail.com,\n Huang Tao ,\n TANG Tiancheng ,\n Daniel Henrique Barboza ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Received-SPF":"pass client-ip=2a00:1450:4864:20::62e;\n envelope-from=alistair23@gmail.com; helo=mail-ej1-x62e.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3676577,"web_url":"http://patchwork.ozlabs.org/comment/3676577/","msgid":"","list_archive_url":null,"date":"2026-04-13T09:02:30","subject":"Re: [PATCH v5 3/6] target/riscv: Integrate SMMPT checks into MMU and\n TLB fill","submitter":{"id":79604,"url":"http://patchwork.ozlabs.org/api/people/79604/","name":"Frank Chang","email":"frank.chang@sifive.com"},"content":"Hi Zhiwei,\n\nLIU Zhiwei 於 2026年4月9日週四 上午3:12寫道：\n>\n> With the core MPT lookup logic in place, this patch integrates the\n> permission checks into QEMU's main MMU processing functions.\n>\n> A new helper, `get_physical_address_mpt`, is introduced to check the\n> permissions for a given physical address against the MPT. This helper\n> is then called at two critical points:\n>\n> 1. During page table walks (`get_physical_address`): The physical\n> address of the Page Table Entry (PTE) itself is checked to ensure\n> the supervisor has permission to read it.\n>\n> 2. After successful address translation (`riscv_cpu_tlb_fill`): The final\n> guest-physical address is checked against the MPT before the access\n> is allowed to proceed.\n>\n> This ensures that SMMPT protection is enforced for both the translation\n> process and the final memory access, as required by the specification.\n>\n> Co-authored-by: Huang Tao \n> Co-authored-by: TANG Tiancheng \n> Signed-off-by: LIU Zhiwei \n> Reviewed-by: Daniel Henrique Barboza \n> ---\n> target/riscv/cpu_helper.c | 76 ++++++++++++++++++++++++++++++++++++++-\n> 1 file changed, 75 insertions(+), 1 deletion(-)\n>\n> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c\n> index e3361fadae..2fab00e9b4 100644\n> --- a/target/riscv/cpu_helper.c\n> +++ b/target/riscv/cpu_helper.c\n> @@ -1161,6 +1161,60 @@ static bool check_svukte_addr(CPURISCVState *env, vaddr addr)\n> return !high_bit;\n> }\n>\n> +/*\n> + * get_physical_address_mpt - check mpt permission for this physical address\n> + *\n> + * Lookup the Memory Protection Table and check permission for this\n> + * physical address. Returns 0 if the permission checking was successful\n> + *\n> + * @env: CPURISCVState\n> + * @prot: The returned protection attributes\n> + * @addr: The physical address to be checked permission\n> + * @access_type: The type of MMU access\n> + * @mode: Indicates current privilege level.\n> + */\n> +static int get_physical_address_mpt(CPURISCVState *env, int *prot, hwaddr addr,\n> + MMUAccessType access_type, int mode)\n> +{\n> + mpt_access_t mpt_access;\n> + bool mpt_has_access;\n> +\n> + /*\n> + * If the extension is not supported or the mmpt.mode is Bare,\n> + * there is no protection, return success.\n> + */\n> + if (!riscv_cpu_cfg(env)->ext_smmpt || env->mptmode == 0) {\n\nNit: env->mptmode == SMMPTBARE\n\n> + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;\n> + return TRANSLATE_SUCCESS;\n> + }\n> +\n> + /*\n> + * MPT is checked for all accesses to physical memory, unless the\n> + * effective privilege mode is M.\n> + *\n> + * Data accesses in M-mode when the MPRV bit in mstatus is set and\n> + * the MPP field in mstatus contains S or U are subject to MPT checks.\n> + *\n> + * In riscv_env_mmu_index, The MPRV and MPP bits are already checked and\n> + * encoded to mmu_idx, So we do not need to check it here.\n> + */\n> + if (mode == PRV_M) {\n> + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;\n> + return TRANSLATE_SUCCESS;\n> + }\n> +\n> + mpt_has_access = smmpt_check_access(env, addr,\n> + &mpt_access, access_type);\n> + if (!mpt_has_access) {\n> + *prot = 0;\n> + return TRANSLATE_MPT_FAIL;\n> + }\n> +\n> + *prot = smmpt_access_to_page_prot(mpt_access);\n> +\n> + return TRANSLATE_SUCCESS;\n> +}\n> +\n> /*\n> * get_physical_address - get the physical address for this virtual address\n> *\n> @@ -1355,6 +1409,13 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,\n> pte_addr = base + idx * ptesize;\n> }\n>\n> + int mpt_prot;\n> + int mpt_ret = get_physical_address_mpt(env, &mpt_prot, pte_addr,\n> + MMU_DATA_LOAD, PRV_S);\n> + if (mpt_ret != TRANSLATE_SUCCESS) {\n> + return TRANSLATE_MPT_FAIL;\n\nNit: Just return mpt_ret;\n\n> + }\n> +\n> int pmp_prot;\n> int pmp_ret = get_physical_address_pmp(env, &pmp_prot, pte_addr,\n> sxlen_bytes,\n> @@ -1765,7 +1826,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n> CPURISCVState *env = &cpu->env;\n> vaddr im_address;\n> hwaddr pa = 0;\n> - int prot, prot2, prot_pmp;\n> + int prot, prot2, prot_pmp, mpt_prot;\n> bool pmp_violation = false;\n> bool first_stage_error = true;\n> bool two_stage_lookup = mmuidx_2stage(mmu_idx);\n> @@ -1819,6 +1880,13 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n> prot &= prot2;\n>\n> if (ret == TRANSLATE_SUCCESS) {\n> + ret = get_physical_address_mpt(env, &mpt_prot, pa,\n> + access_type, mode);\n> + qemu_log_mask(CPU_LOG_MMU,\n> + \"%s MPT address=\" HWADDR_FMT_plx \" ret %d prot\"\n> + \" %d\\n\",\n> + __func__, pa, ret, mpt_prot);\n> + prot &= mpt_prot;\n\nWe didn't check the return value of get_physical_address_mpt().\nSo it might that get_physical_address_mpt() returns TRANSLATE_MPT_FAIL,\nbut get_physical_address_pmp() returns TRANSLATE_SUCCESS.\nThe final ret will become: TRANSLATE_SUCCESS.\n\n> ret = get_physical_address_pmp(env, &prot_pmp, pa,\n> size, access_type, mode);\n> tlb_size = pmp_get_tlb_size(env, pa);\n> @@ -1854,6 +1922,12 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n> __func__, address, ret, pa, prot);\n>\n> if (ret == TRANSLATE_SUCCESS) {\n> + ret = get_physical_address_mpt(env, &mpt_prot, pa,\n> + access_type, mode);\n> + qemu_log_mask(CPU_LOG_MMU,\n> + \"%s MPT address=\" HWADDR_FMT_plx \" ret %d prot %d\\n\",\n> + __func__, pa, ret, mpt_prot);\n> + prot &= mpt_prot;\n> ret = get_physical_address_pmp(env, &prot_pmp, pa,\n> size, access_type, mode);\n> tlb_size = pmp_get_tlb_size(env, pa);\n> --\n> 2.43.0\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=X56RXcmC;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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