[{"id":3675754,"web_url":"http://patchwork.ozlabs.org/comment/3675754/","msgid":"<7768956d-f1d6-496b-93ef-10525852e95e@redhat.com>","list_archive_url":null,"date":"2026-04-10T09:33:57","subject":"Re: [Intel-wired-lan] [PATCH iwl-net 2/4] ice: perform PHY soft\n reset for E825C ports at initialization","submitter":{"id":74657,"url":"http://patchwork.ozlabs.org/api/people/74657/","name":"Petr Oros","email":"poros@redhat.com"},"content":"On 4/8/26 20:46, Jacob Keller wrote:\n> From: Grzegorz Nitka \n>\n> In some cases the PHY timestamp block of the E825C can become stuck. This\n> is known to occur if the software writes 0 to the Tx timestamp threshold,\n> and with older versions of the ice driver the threshold configuration is\n> buggy and can race in such that hardware briefly operates with a zero\n> threshold enabled. There are no other known ways to trigger this behavior,\n> but once it occurs, the hardware is not recovered by normal reset, a driver\n> reload, or even a warm power cycle of the system. A cold power cycle is\n> sufficient to recover hardware, but this is extremely invasive and can\n> result in significant downtime on customer deployments.\n>\n> The PHY for each port has a timestamping block which has its own reset\n> functionality accessible by programming the PHY_REG_GLOBAL register.\n> Writing to the PHY_REG_GLOBAL_SOFT_RESET_BIT triggers the hardware to\n> perform a complete reset of the timestamping block of the PHY. This\n> includes clearing the timestamp status for the port, clearing all\n> outstanding timestamps in the memory bank, and resetting the PHY timer.\n>\n> The new ice_ptp_phy_soft_reset_eth56g() function toggles the\n> PHY_REG_GLOBAL soft reset bit with the required delays, ensuring the\n> PHY is properly reinitialized without requiring a full device reset.\n> The sequence clears the reset bit, asserts it, then clears it again,\n> with short waits between transitions to allow hardware stabilization.\n>\n> Call this function in the new ice_ptp_init_phc_e825c(), implementing the\n> E825C device specific variant of the ice_ptp_init_phc(). Note that if\n> ice_ptp_init_phc() fails, PTP functionality may be disabled, but the driver\n> will still load to allow basic functionality to continue.\n>\n> This causes the clock owning PF driver to perform a PHY soft reset for\n> every port during initialization. This ensures the driver begins life in a\n> known functional state regardless of how it was previously programmed.\n>\n> This ensures that we properly reconfigure the hardware after a device reset\n> or when loading the driver, even if it was previously misconfigured with an\n> out-of-date or modified driver.\n>\n> Fixes: 7cab44f1c35f (\"ice: Introduce ETH56G PHY model for E825C products\")\n> Signed-off-by: Timothy Miskell \n> Signed-off-by: Grzegorz Nitka \n> Signed-off-by: Jacob Keller \n> Reviewed-by: Aleksandr Loktionov \n> ---\n> drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 4 ++\n> drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 90 ++++++++++++++++++++++++++++-\n> 2 files changed, 93 insertions(+), 1 deletion(-)\n>\n> diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h\n> index 5896b346e579..9d7acc7eb2ce 100644\n> --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h\n> +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h\n> @@ -374,6 +374,7 @@ int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset);\n> int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port);\n> int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold);\n> int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port);\n> +int ice_ptp_phy_soft_reset_eth56g(struct ice_hw *hw, u8 port);\n> \n> #define ICE_ETH56G_NOMINAL_INCVAL\t0x140000000ULL\n> #define ICE_ETH56G_NOMINAL_PCS_REF_TUS\t0x100000000ULL\n> @@ -676,6 +677,9 @@ static inline u64 ice_get_base_incval(struct ice_hw *hw)\n> #define ICE_P0_GNSS_PRSNT_N\tBIT(4)\n> \n> /* ETH56G PHY register addresses */\n> +#define PHY_REG_GLOBAL\t\t\t0x0\n> +#define PHY_REG_GLOBAL_SOFT_RESET_M\tBIT(11)\n> +\n> /* Timestamp PHY incval registers */\n> #define PHY_REG_TIMETUS_L\t\t0x8\n> #define PHY_REG_TIMETUS_U\t\t0xC\n> diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\n> index 67775beb9449..441b5f10e4bb 100644\n> --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\n> +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\n> @@ -377,6 +377,31 @@ static void ice_ptp_cfg_sync_delay(const struct ice_hw *hw, u32 delay)\n> * The following functions operate on devices with the ETH 56G PHY.\n> */\n> \n> +/**\n> + * ice_ptp_init_phc_e825c - Perform E825C specific PHC initialization\n> + * @hw: pointer to HW struct\n> + *\n> + * Perform E825C-specific PTP hardware clock initialization steps.\n> + *\n> + * Return: 0 on success, or a negative error value on failure.\n> + */\n> +static int ice_ptp_init_phc_e825c(struct ice_hw *hw)\n> +{\n> +\tint err;\n> +\n> +\t/* Soft reset all ports, to ensure everything is at a clean state */\n> +\tfor (int port = 0; port < hw->ptp.num_lports; port++) {\n> +\t\terr = ice_ptp_phy_soft_reset_eth56g(hw, port);\n> +\t\tif (err) {\n> +\t\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to soft reset port %d, err %d\\n\",\n> +\t\t\t\t port, err);\n> +\t\t\treturn err;\n> +\t\t}\n> +\t}\n> +\n> +\treturn 0;\n> +}\n> +\n> /**\n> * ice_ptp_get_dest_dev_e825 - get destination PHY for given port number\n> * @hw: pointer to the HW struct\n> @@ -2179,6 +2204,69 @@ int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status)\n> \treturn 0;\n> }\n> \n> +/**\n> + * ice_ptp_phy_soft_reset_eth56g - Perform a PHY soft reset on ETH56G\n> + * @hw: pointer to the HW structure\n> + * @port: PHY port number\n> + *\n> + * Trigger a soft reset of the ETH56G PHY by toggling the soft reset\n> + * bit in the PHY global register. The reset sequence consists of:\n> + * 1. Clearing the soft reset bit\n> + * 2. Asserting the soft reset bit\n> + * 3. Clearing the soft reset bit again\n> + *\n> + * Short delays are inserted between each step to allow the hardware\n> + * to settle. This provides a controlled way to reinitialize the PHY\n> + * without requiring a full device reset.\n> + *\n> + * Return: 0 on success, or a negative error code on failure when\n> + * reading or writing the PHY register.\n> + */\n> +int ice_ptp_phy_soft_reset_eth56g(struct ice_hw *hw, u8 port)\n> +{\n> +\tu32 global_val;\n> +\tint err;\n> +\n> +\terr = ice_read_ptp_reg_eth56g(hw, port, PHY_REG_GLOBAL, &global_val);\n> +\tif (err) {\n> +\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read PHY_REG_GLOBAL for port %d, err %d\\n\",\n> +\t\t\t port, err);\n> +\t\treturn err;\n> +\t}\n> +\n> +\tglobal_val &= ~PHY_REG_GLOBAL_SOFT_RESET_M;\n> +\tice_debug(hw, ICE_DBG_PTP, \"Clearing soft reset bit for port %d, val: 0x%x\\n\",\n> +\t\t port, global_val);\n> +\terr = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_GLOBAL, global_val);\n> +\tif (err) {\n> +\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write PHY_REG_GLOBAL for port %d, err %d\\n\",\n> +\t\t\t port, err);\n> +\t\treturn err;\n> +\t}\n> +\n> +\tusleep_range(5000, 6000);\n> +\n> +\tglobal_val |= PHY_REG_GLOBAL_SOFT_RESET_M;\n> +\tice_debug(hw, ICE_DBG_PTP, \"Set soft reset bit for port %d, val: 0x%x\\n\",\n> +\t\t port, global_val);\n> +\terr = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_GLOBAL, global_val);\n> +\tif (err) {\n> +\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write PHY_REG_GLOBAL for port %d, err %d\\n\",\n> +\t\t\t port, err);\n> +\t\treturn err;\n> +\t}\n> +\tusleep_range(5000, 6000);\n> +\n> +\tglobal_val &= ~PHY_REG_GLOBAL_SOFT_RESET_M;\n> +\tice_debug(hw, ICE_DBG_PTP, \"Clear soft reset bit for port %d, val: 0x%x\\n\",\n> +\t\t port, global_val);\n> +\terr = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_GLOBAL, global_val);\n> +\tif (err)\n> +\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write PHY_REG_GLOBAL for port %d, err %d\\n\",\n> +\t\t\t port, err);\n> +\treturn err;\n> +}\n> +\n> /**\n> * ice_get_phy_tx_tstamp_ready_eth56g - Read the Tx memory status register\n> * @hw: pointer to the HW struct\n> @@ -5591,7 +5679,7 @@ int ice_ptp_init_phc(struct ice_hw *hw)\n> \tcase ICE_MAC_GENERIC:\n> \t\treturn ice_ptp_init_phc_e82x(hw);\n> \tcase ICE_MAC_GENERIC_3K_E825:\n> -\t\treturn 0;\n> +\t\treturn ice_ptp_init_phc_e825c(hw);\n> \tdefault:\n> \t\treturn -EOPNOTSUPP;\n> \t}\n>\nReviewed-by: Petr Oros ","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=XaKBc1rh;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::137; 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