[{"id":3675753,"web_url":"http://patchwork.ozlabs.org/comment/3675753/","msgid":"<515bb9be-5623-4589-ba5c-d8e5e8a4f10c@redhat.com>","list_archive_url":null,"date":"2026-04-10T09:33:21","subject":"Re: [Intel-wired-lan] [PATCH iwl-net 1/4] ice: fix timestamp\n interrupt configuration for E825C","submitter":{"id":74657,"url":"http://patchwork.ozlabs.org/api/people/74657/","name":"Petr Oros","email":"poros@redhat.com"},"content":"On 4/8/26 20:46, Jacob Keller wrote:\n> From: Grzegorz Nitka \n>\n> The E825C ice_phy_cfg_intr_eth56g() function is responsible for programming\n> the PHY interrupt for a given port. This function writes to the\n> PHY_REG_TS_INT_CONFIG register of the port. The register is responsible for\n> configuring whether the port interrupt logic is enabled, as well as\n> programming the threshold of waiting timestamps that will trigger an\n> interrupt from this port.\n>\n> This threshold value must not be programmed to zero while the interrupt is\n> enabled. Doing so puts the port in a misconfigured state where the PHY\n> timestamp interrupt for the quad of connected ports will become stuck.\n>\n> This occurs, because a threshold of zero results in the timestamp interrupt\n> status for the port becoming stuck high. The four ports in the connected\n> quad have their timestamp status indicators muxed together. A new interrupt\n> cannot be generated until the timestamp status indicators return low for\n> all four ports.\n>\n> Normally, the timestamp status for a port will clear once there are fewer\n> timestamps in that ports timestamp memory bank than the threshold. A\n> threshold of zero makes this impossible, so the timestamp status for the\n> port does not clear.\n>\n> The ice driver never intentionally programs the threshold to zero, indeed\n> the driver always programs it to a value of 1, intending to get an\n> interrupt immediately as soon as even a single packet is waiting for a\n> timestamp.\n>\n> However, there is a subtle flaw in the programming logic in the\n> ice_phy_cfg_intr_eth56g() function. Due to the way that the hardware\n> handles enabling the PHY interrupt. If the threshold value is modified at\n> the same time as the interrupt is enabled, the HW PHY state machine might\n> enable the interrupt before the new threshold value is actually updated.\n> This leaves a potential race condition caused by the hardware logic where\n> a PHY timestamp interrupt might be triggered before the non-zero threshold\n> is written, resulting in the PHY timestamp logic becoming stuck.\n>\n> Once the PHY timestamp status is stuck high, it will remain stuck even\n> after attempting to reprogram the PHY block by changing its threshold or\n> disabling the interrupt. Even a typical PF or CORE reset will not reset the\n> particular block of the PHY that becomes stuck. Even a warm power cycle is\n> not guaranteed to cause the PHY block to reset, and a cold power cycle is\n> required.\n>\n> Prevent this by always writing the PHY_REG_TS_INT_CONFIG in two stages.\n> First write the threshold value with the interrupt disabled, and only write\n> the enable bit after the threshold has been programmed. When disabling the\n> interrupt, leave the threshold unchanged. Additionally, re-read the\n> register after writing it to guarantee that the write to the PHY has been\n> flushed upon exit of the function.\n>\n> While we're modifying this function implementation, explicitly reject\n> programming a threshold of 0 when enabling the interrupt. No caller does\n> this today, but the consequences of doing so are significant. An explicit\n> rejection in the code makes this clear.\n>\n> Fixes: 7cab44f1c35f (\"ice: Introduce ETH56G PHY model for E825C products\")\n> Signed-off-by: Grzegorz Nitka \n> Signed-off-by: Jacob Keller \n> Reviewed-by: Aleksandr Loktionov \n> ---\n> drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 36 +++++++++++++++++++++++++----\n> 1 file changed, 32 insertions(+), 4 deletions(-)\n>\n> diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\n> index e3db252c3918..67775beb9449 100644\n> --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\n> +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\n> @@ -1847,6 +1847,8 @@ static int ice_phy_cfg_mac_eth56g(struct ice_hw *hw, u8 port)\n> * @ena: enable or disable interrupt\n> * @threshold: interrupt threshold\n> *\n> + * The threshold cannot be 0 while the interrupt is enabled.\n> + *\n> * Configure TX timestamp interrupt for the specified port\n> *\n> * Return:\n> @@ -1858,19 +1860,45 @@ int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold)\n> \tint err;\n> \tu32 val;\n> \n> +\tif (ena && !threshold)\n> +\t\treturn -EINVAL;\n> +\n> \terr = ice_read_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, &val);\n> \tif (err)\n> \t\treturn err;\n> \n> +\tval &= ~PHY_TS_INT_CONFIG_ENA_M;\n> \tif (ena) {\n> -\t\tval |= PHY_TS_INT_CONFIG_ENA_M;\n> \t\tval &= ~PHY_TS_INT_CONFIG_THRESHOLD_M;\n> \t\tval |= FIELD_PREP(PHY_TS_INT_CONFIG_THRESHOLD_M, threshold);\n> -\t} else {\n> -\t\tval &= ~PHY_TS_INT_CONFIG_ENA_M;\n> +\t\terr = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG,\n> +\t\t\t\t\t val);\n> +\t\tif (err) {\n> +\t\t\tice_debug(hw, ICE_DBG_PTP,\n> +\t\t\t\t \"Failed to update 'threshold' PHY_REG_TS_INT_CONFIG port=%u ena=%u threshold=%u\\n\",\n> +\t\t\t\t port, !!ena, threshold);\n> +\t\t\treturn err;\n> +\t\t}\n> +\t\tval |= PHY_TS_INT_CONFIG_ENA_M;\n> \t}\n> \n> -\treturn ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, val);\n> +\terr = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, val);\n> +\tif (err) {\n> +\t\tice_debug(hw, ICE_DBG_PTP,\n> +\t\t\t \"Failed to update 'ena' PHY_REG_TS_INT_CONFIG port=%u ena=%u threshold=%u\\n\",\n> +\t\t\t port, !!ena, threshold);\n> +\t\treturn err;\n> +\t}\n> +\n> +\terr = ice_read_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, &val);\n> +\tif (err) {\n> +\t\tice_debug(hw, ICE_DBG_PTP,\n> +\t\t\t \"Failed to read PHY_REG_TS_INT_CONFIG port=%u ena=%u threshold=%u\\n\",\n> +\t\t\t port, !!ena, threshold);\n> +\t\treturn err;\n> +\t}\n> +\n> +\treturn 0;\n> }\n> \n> /**\n>\nReviewed-by: Petr Oros ","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=okM18uYR;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=140.211.166.137; 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