[{"id":3675002,"web_url":"http://patchwork.ozlabs.org/comment/3675002/","msgid":"","list_archive_url":null,"date":"2026-04-08T21:56:26","subject":"Re: [PATCH v3 03/16] target/hexagon/cpu: add HVX IEEE FP extension","submitter":{"id":86757,"url":"http://patchwork.ozlabs.org/api/people/86757/","name":"Taylor Simpson","email":"ltaylorsimpson@gmail.com"},"content":"On Wed, Apr 8, 2026 at 10:37 AM Matheus Tavares Bernardino <\nmatheus.bernardino@oss.qualcomm.com> wrote:\n\n> This flag will be used to control the HVX IEEE float instructions, which\n> are only available at some Hexagon cores. When unavailable, the\n> instruction effectively only set the destination registers to 0.\n>\n> Signed-off-by: Matheus Tavares Bernardino <\n> matheus.bernardino@oss.qualcomm.com>\n> ---\n> target/hexagon/cpu.h | 1 +\n> target/hexagon/translate.h | 1 +\n> target/hexagon/attribs_def.h.inc | 3 +++\n> target/hexagon/cpu.c | 1 +\n> target/hexagon/translate.c | 1 +\n> target/hexagon/gen_tcg_funcs.py | 11 ++++++++++\n> target/hexagon/hex_common.py | 35 ++++++++++++++++++++++++++++++++\n> 7 files changed, 53 insertions(+)\n>\n> diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h\n> index 85afd59277..77822a48b6 100644\n> --- a/target/hexagon/cpu.h\n> +++ b/target/hexagon/cpu.h\n> @@ -127,6 +127,7 @@ struct ArchCPU {\n> bool lldb_compat;\n> target_ulong lldb_stack_adjust;\n> bool short_circuit;\n> + bool ieee_fp_extension;\n> };\n>\n> #include \"cpu_bits.h\"\n> diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h\n> index b37cb49238..516aab7038 100644\n> --- a/target/hexagon/translate.h\n> +++ b/target/hexagon/translate.h\n> @@ -70,6 +70,7 @@ typedef struct DisasContext {\n> target_ulong branch_dest;\n> bool is_tight_loop;\n> bool short_circuit;\n> + bool ieee_fp_extension;\n> bool read_after_write;\n> bool has_hvx_overlap;\n> TCGv new_value[TOTAL_PER_THREAD_REGS];\n> diff --git a/target/hexagon/attribs_def.h.inc\n> b/target/hexagon/attribs_def.h.inc\n> index 9e3a05f882..c85cd5d17c 100644\n> --- a/target/hexagon/attribs_def.h.inc\n> +++ b/target/hexagon/attribs_def.h.inc\n> @@ -173,5 +173,8 @@ DEF_ATTRIB(NOTE_SHIFT_RESOURCE, \"Uses the HVX shift\n> resource.\", \"\", \"\")\n> DEF_ATTRIB(RESTRICT_NOSLOT1_STORE, \"Packet must not have slot 1 store\",\n> \"\", \"\")\n> DEF_ATTRIB(RESTRICT_LATEPRED, \"Predicate can not be used as a .new.\", \"\",\n> \"\")\n>\n> +/* HVX IEEE FP extension attributes */\n> +DEF_ATTRIB(HVX_IEEE_FP, \"HVX IEEE FP extension instruction\", \"\", \"\")\n> +\n> /* Keep this as the last attribute: */\n> DEF_ATTRIB(ZZ_LASTATTRIB, \"Last attribute in the file\", \"\", \"\")\n> diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\n> index ffd14bb467..8b72a5d3c8 100644\n> --- a/target/hexagon/cpu.c\n> +++ b/target/hexagon/cpu.c\n> @@ -54,6 +54,7 @@ static const Property hexagon_cpu_properties[] = {\n> DEFINE_PROP_UNSIGNED(\"lldb-stack-adjust\", HexagonCPU,\n> lldb_stack_adjust, 0,\n> qdev_prop_uint32, target_ulong),\n> DEFINE_PROP_BOOL(\"short-circuit\", HexagonCPU, short_circuit, true),\n> + DEFINE_PROP_BOOL(\"ieee-fp\", HexagonCPU, ieee_fp_extension, true),\n> };\n>\n> const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = {\n> diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c\n> index 633401451d..fa8f615a9e 100644\n> --- a/target/hexagon/translate.c\n> +++ b/target/hexagon/translate.c\n> @@ -988,6 +988,7 @@ static void\n> hexagon_tr_init_disas_context(DisasContextBase *dcbase,\n> ctx->branch_cond = TCG_COND_NEVER;\n> ctx->is_tight_loop = FIELD_EX32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP);\n> ctx->short_circuit = hex_cpu->short_circuit;\n> + ctx->ieee_fp_extension = hex_cpu->ieee_fp_extension;\n> }\n>\n> static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu)\n> diff --git a/target/hexagon/gen_tcg_funcs.py\n> b/target/hexagon/gen_tcg_funcs.py\n> index 87b7f10d7f..b752ec883c 100755\n> --- a/target/hexagon/gen_tcg_funcs.py\n> +++ b/target/hexagon/gen_tcg_funcs.py\n> @@ -22,6 +22,14 @@\n> import string\n> import hex_common\n>\n> +def gen_disabled_ieee_insn(f, tag, regs):\n> + f.write(\" if (!ctx->ieee_fp_extension) {\\n\")\n> + for regtype, regid in regs:\n> + reg = hex_common.get_register(tag, regtype, regid)\n> + if reg.is_hvx_reg() and reg.is_written():\n> + reg.gen_zero(f)\n>\n\nWhat happens to the non-HVX registers that are written (e.g., address for a\npost-increment load)? I assume they should also be set to zero.\n\n\n> + f.write(\" return;\\n\")\n> + f.write(\" }\\n\")\n>\n> ##\n> ## Generate the TCG code to call the helper\n> @@ -62,6 +70,9 @@ def gen_tcg_func(f, tag, regs, imms):\n> i = 1 if immlett.isupper() else 0\n> f.write(f\" int {hex_common.imm_name(immlett)} =\n> insn->immed[{i}];\\n\")\n>\n> + if \"A_HVX_IEEE_FP\" in hex_common.attribdict[tag]:\n> + gen_disabled_ieee_insn(f, tag, regs)\n> +\n> if hex_common.is_idef_parser_enabled(tag):\n> declared = []\n> ## Handle registers\n> diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py\n> index c0e9f26aeb..32a61505ce 100755\n> --- a/target/hexagon/hex_common.py\n> +++ b/target/hexagon/hex_common.py\n> @@ -723,6 +723,11 @@ def decl_tcg(self, f, tag, regno):\n> TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n> tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env,\n> {self.hvx_off()});\n> \"\"\"))\n> + def gen_zero(self, f):\n> + f.write(code_fmt(f\"\"\"\\\n> + tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n> + sizeof(MMVector), sizeof(MMVector), 0);\n> + \"\"\"))\n> def gen_write(self, f, tag):\n> pass\n> def helper_hvx_desc(self, f):\n> @@ -789,6 +794,11 @@ def decl_tcg(self, f, tag, regno):\n> TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n> tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env,\n> {self.hvx_off()});\n> \"\"\"))\n> + def gen_zero(self, f):\n> + f.write(code_fmt(f\"\"\"\\\n> + tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n> + sizeof(MMVector), sizeof(MMVector), 0);\n> + \"\"\"))\n> def gen_write(self, f, tag):\n> pass\n> def helper_hvx_desc(self, f):\n> @@ -821,6 +831,11 @@ def decl_tcg(self, f, tag, regno):\n> vreg_src_off(ctx, {self.reg_num}),\n> sizeof(MMVector), sizeof(MMVector));\n> \"\"\"))\n> + def gen_zero(self, f):\n> + f.write(code_fmt(f\"\"\"\\\n> + tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n> + sizeof(MMVector), sizeof(MMVector), 0);\n> + \"\"\"))\n> def gen_write(self, f, tag):\n> f.write(code_fmt(f\"\"\"\\\n> gen_vreg_write(ctx, {self.hvx_off()}, {self.reg_num},\n> @@ -854,6 +869,11 @@ def decl_tcg(self, f, tag, regno):\n> TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n> tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env,\n> {self.hvx_off()});\n> \"\"\"))\n> + def gen_zero(self, f):\n> + f.write(code_fmt(f\"\"\"\\\n> + tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n> + sizeof(MMVectorPair), sizeof(MMVectorPair), 0);\n> + \"\"\"))\n> def gen_write(self, f, tag):\n> pass\n> def helper_hvx_desc(self, f):\n> @@ -913,6 +933,11 @@ def decl_tcg(self, f, tag, regno):\n> TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n> tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env,\n> {self.hvx_off()});\n> \"\"\"))\n> + def gen_zero(self, f):\n> + f.write(code_fmt(f\"\"\"\\\n> + tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n> + sizeof(MMVectorPair), sizeof(MMVectorPair), 0);\n> + \"\"\"))\n> def gen_write(self, f, tag):\n> f.write(code_fmt(f\"\"\"\\\n> gen_vreg_write_pair(ctx, {self.hvx_off()}, {self.reg_num},\n> @@ -946,6 +971,11 @@ def decl_tcg(self, f, tag, regno):\n> TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n> tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env,\n> {self.hvx_off()});\n> \"\"\"))\n> + def gen_zero(self, f):\n> + f.write(code_fmt(f\"\"\"\\\n> + tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n> + sizeof(MMQReg), sizeof(MMQReg), 0);\n> + \"\"\"))\n>\n\nDo any of these instructions write QRegs? If not, this isn't needed.\n\n\n> def gen_write(self, f, tag):\n> pass\n> def helper_hvx_desc(self, f):\n> @@ -993,6 +1023,11 @@ def decl_tcg(self, f, tag, regno):\n> TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n> tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env,\n> {self.hvx_off()});\n> \"\"\"))\n> + def gen_zero(self, f):\n> + f.write(code_fmt(f\"\"\"\\\n> + tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n> + sizeof(MMQReg), sizeof(MMQReg), 0);\n> + \"\"\"))\n>\n\nDitto\n\n\n> def gen_write(self, f, tag):\n> pass\n> def helper_hvx_desc(self, f):\n> --\n> 2.37.2\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=eZzA0uh7;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Wed, 08 Apr 2026\n 14:56:39 -0700 (PDT)","MIME-Version":"1.0","References":"\n ","In-Reply-To":"\n ","From":"Taylor Simpson ","Date":"Wed, 8 Apr 2026 15:56:26 -0600","X-Gm-Features":"AQROBzCmBu6f_hY4tJaYUK9XEEJBfMtw-OAKocoB4r-sP3r2y1AvM5lIRHiHKkM","Message-ID":"\n ","Subject":"Re: [PATCH v3 03/16] target/hexagon/cpu: add HVX IEEE FP extension","To":"Matheus Tavares Bernardino ","Cc":"qemu-devel@nongnu.org, richard.henderson@linaro.org, ale@rev.ng,\n anjo@rev.ng, brian.cain@oss.qualcomm.com, marco.liebel@oss.qualcomm.com,\n philmd@linaro.org, quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com","Content-Type":"multipart/alternative; boundary=\"000000000000743c55064ef9f969\"","Received-SPF":"pass client-ip=2607:f8b0:4864:20::62d;\n envelope-from=ltaylorsimpson@gmail.com; helo=mail-pl1-x62d.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3675968,"web_url":"http://patchwork.ozlabs.org/comment/3675968/","msgid":"","list_archive_url":null,"date":"2026-04-10T16:16:25","subject":"Re: [PATCH v3 03/16] target/hexagon/cpu: add HVX IEEE FP extension","submitter":{"id":90606,"url":"http://patchwork.ozlabs.org/api/people/90606/","name":"Matheus Tavares Bernardino","email":"matheus.bernardino@oss.qualcomm.com"},"content":"On Wed, Apr 8, 2026 at 6:56 PM Taylor Simpson wrote:\n>\n>\n>\n> On Wed, Apr 8, 2026 at 10:37 AM Matheus Tavares Bernardino wrote:\n>>\n>> This flag will be used to control the HVX IEEE float instructions, which\n>> are only available at some Hexagon cores. When unavailable, the\n>> instruction effectively only set the destination registers to 0.\n>>\n>> Signed-off-by: Matheus Tavares Bernardino \n>> ---\n>> target/hexagon/cpu.h | 1 +\n>> target/hexagon/translate.h | 1 +\n>> target/hexagon/attribs_def.h.inc | 3 +++\n>> target/hexagon/cpu.c | 1 +\n>> target/hexagon/translate.c | 1 +\n>> target/hexagon/gen_tcg_funcs.py | 11 ++++++++++\n>> target/hexagon/hex_common.py | 35 ++++++++++++++++++++++++++++++++\n>> 7 files changed, 53 insertions(+)\n>>\n>> diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h\n>> index 85afd59277..77822a48b6 100644\n>> --- a/target/hexagon/cpu.h\n>> +++ b/target/hexagon/cpu.h\n>> @@ -127,6 +127,7 @@ struct ArchCPU {\n>> bool lldb_compat;\n>> target_ulong lldb_stack_adjust;\n>> bool short_circuit;\n>> + bool ieee_fp_extension;\n>> };\n>>\n>> #include \"cpu_bits.h\"\n>> diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h\n>> index b37cb49238..516aab7038 100644\n>> --- a/target/hexagon/translate.h\n>> +++ b/target/hexagon/translate.h\n>> @@ -70,6 +70,7 @@ typedef struct DisasContext {\n>> target_ulong branch_dest;\n>> bool is_tight_loop;\n>> bool short_circuit;\n>> + bool ieee_fp_extension;\n>> bool read_after_write;\n>> bool has_hvx_overlap;\n>> TCGv new_value[TOTAL_PER_THREAD_REGS];\n>> diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc\n>> index 9e3a05f882..c85cd5d17c 100644\n>> --- a/target/hexagon/attribs_def.h.inc\n>> +++ b/target/hexagon/attribs_def.h.inc\n>> @@ -173,5 +173,8 @@ DEF_ATTRIB(NOTE_SHIFT_RESOURCE, \"Uses the HVX shift resource.\", \"\", \"\")\n>> DEF_ATTRIB(RESTRICT_NOSLOT1_STORE, \"Packet must not have slot 1 store\", \"\", \"\")\n>> DEF_ATTRIB(RESTRICT_LATEPRED, \"Predicate can not be used as a .new.\", \"\", \"\")\n>>\n>> +/* HVX IEEE FP extension attributes */\n>> +DEF_ATTRIB(HVX_IEEE_FP, \"HVX IEEE FP extension instruction\", \"\", \"\")\n>> +\n>> /* Keep this as the last attribute: */\n>> DEF_ATTRIB(ZZ_LASTATTRIB, \"Last attribute in the file\", \"\", \"\")\n>> diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\n>> index ffd14bb467..8b72a5d3c8 100644\n>> --- a/target/hexagon/cpu.c\n>> +++ b/target/hexagon/cpu.c\n>> @@ -54,6 +54,7 @@ static const Property hexagon_cpu_properties[] = {\n>> DEFINE_PROP_UNSIGNED(\"lldb-stack-adjust\", HexagonCPU, lldb_stack_adjust, 0,\n>> qdev_prop_uint32, target_ulong),\n>> DEFINE_PROP_BOOL(\"short-circuit\", HexagonCPU, short_circuit, true),\n>> + DEFINE_PROP_BOOL(\"ieee-fp\", HexagonCPU, ieee_fp_extension, true),\n>> };\n>>\n>> const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = {\n>> diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c\n>> index 633401451d..fa8f615a9e 100644\n>> --- a/target/hexagon/translate.c\n>> +++ b/target/hexagon/translate.c\n>> @@ -988,6 +988,7 @@ static void hexagon_tr_init_disas_context(DisasContextBase *dcbase,\n>> ctx->branch_cond = TCG_COND_NEVER;\n>> ctx->is_tight_loop = FIELD_EX32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP);\n>> ctx->short_circuit = hex_cpu->short_circuit;\n>> + ctx->ieee_fp_extension = hex_cpu->ieee_fp_extension;\n>> }\n>>\n>> static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu)\n>> diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py\n>> index 87b7f10d7f..b752ec883c 100755\n>> --- a/target/hexagon/gen_tcg_funcs.py\n>> +++ b/target/hexagon/gen_tcg_funcs.py\n>> @@ -22,6 +22,14 @@\n>> import string\n>> import hex_common\n>>\n>> +def gen_disabled_ieee_insn(f, tag, regs):\n>> + f.write(\" if (!ctx->ieee_fp_extension) {\\n\")\n>> + for regtype, regid in regs:\n>> + reg = hex_common.get_register(tag, regtype, regid)\n>> + if reg.is_hvx_reg() and reg.is_written():\n>> + reg.gen_zero(f)\n>\n>\n> What happens to the non-HVX registers that are written (e.g., address for a post-increment load)? I assume they should also be set to zero.\n\nNone of these instructions write to non-HVX registers.\n\n>>\n>> + f.write(\" return;\\n\")\n>> + f.write(\" }\\n\")\n>>\n>> ##\n>> ## Generate the TCG code to call the helper\n>> @@ -62,6 +70,9 @@ def gen_tcg_func(f, tag, regs, imms):\n>> i = 1 if immlett.isupper() else 0\n>> f.write(f\" int {hex_common.imm_name(immlett)} = insn->immed[{i}];\\n\")\n>>\n>> + if \"A_HVX_IEEE_FP\" in hex_common.attribdict[tag]:\n>> + gen_disabled_ieee_insn(f, tag, regs)\n>> +\n>> if hex_common.is_idef_parser_enabled(tag):\n>> declared = []\n>> ## Handle registers\n>> diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py\n>> index c0e9f26aeb..32a61505ce 100755\n>> --- a/target/hexagon/hex_common.py\n>> +++ b/target/hexagon/hex_common.py\n>> @@ -723,6 +723,11 @@ def decl_tcg(self, f, tag, regno):\n>> TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n>> tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});\n>> \"\"\"))\n>> + def gen_zero(self, f):\n>> + f.write(code_fmt(f\"\"\"\\\n>> + tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n>> + sizeof(MMVector), sizeof(MMVector), 0);\n>> + \"\"\"))\n>> def gen_write(self, f, tag):\n>> pass\n>> def helper_hvx_desc(self, f):\n>> @@ -789,6 +794,11 @@ def decl_tcg(self, f, tag, regno):\n>> TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n>> tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});\n>> \"\"\"))\n>> + def gen_zero(self, f):\n>> + f.write(code_fmt(f\"\"\"\\\n>> + tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n>> + sizeof(MMVector), sizeof(MMVector), 0);\n>> + \"\"\"))\n>> def gen_write(self, f, tag):\n>> pass\n>> def helper_hvx_desc(self, f):\n>> @@ -821,6 +831,11 @@ def decl_tcg(self, f, tag, regno):\n>> vreg_src_off(ctx, {self.reg_num}),\n>> sizeof(MMVector), sizeof(MMVector));\n>> \"\"\"))\n>> + def gen_zero(self, f):\n>> + f.write(code_fmt(f\"\"\"\\\n>> + tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n>> + sizeof(MMVector), sizeof(MMVector), 0);\n>> + \"\"\"))\n>> def gen_write(self, f, tag):\n>> f.write(code_fmt(f\"\"\"\\\n>> gen_vreg_write(ctx, {self.hvx_off()}, {self.reg_num},\n>> @@ -854,6 +869,11 @@ def decl_tcg(self, f, tag, regno):\n>> TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n>> tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});\n>> \"\"\"))\n>> + def gen_zero(self, f):\n>> + f.write(code_fmt(f\"\"\"\\\n>> + tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n>> + sizeof(MMVectorPair), sizeof(MMVectorPair), 0);\n>> + \"\"\"))\n>> def gen_write(self, f, tag):\n>> pass\n>> def helper_hvx_desc(self, f):\n>> @@ -913,6 +933,11 @@ def decl_tcg(self, f, tag, regno):\n>> TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n>> tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});\n>> \"\"\"))\n>> + def gen_zero(self, f):\n>> + f.write(code_fmt(f\"\"\"\\\n>> + tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n>> + sizeof(MMVectorPair), sizeof(MMVectorPair), 0);\n>> + \"\"\"))\n>> def gen_write(self, f, tag):\n>> f.write(code_fmt(f\"\"\"\\\n>> gen_vreg_write_pair(ctx, {self.hvx_off()}, {self.reg_num},\n>> @@ -946,6 +971,11 @@ def decl_tcg(self, f, tag, regno):\n>> TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n>> tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});\n>> \"\"\"))\n>> + def gen_zero(self, f):\n>> + f.write(code_fmt(f\"\"\"\\\n>> + tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n>> + sizeof(MMQReg), sizeof(MMQReg), 0);\n>> + \"\"\"))\n>\n>\n> Do any of these instructions write QRegs? If not, this isn't needed.\n\nThey do not. Let me remove this.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=LNpCHgzO;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=Zz0xs42v;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fshlk3JN1z1yGS\n\tfor ; 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