[{"id":3674865,"web_url":"http://patchwork.ozlabs.org/comment/3674865/","msgid":"<f837da45-2b31-4788-a957-085d3f0570d0@nvidia.com>","list_archive_url":null,"date":"2026-04-08T17:38:45","subject":"Re: [PATCH v2 1/2] ASoC: tegra210_adx: simplify byte map get/put\n logic","submitter":{"id":66273,"url":"http://patchwork.ozlabs.org/api/people/66273/","name":"Jon Hunter","email":"jonathanh@nvidia.com"},"content":"On 08/04/2026 18:08, Piyush Patle wrote:\n> The byte-map controls (\"Byte Map N\") already expose a value range of\n> [0, 256] to userspace via SOC_SINGLE_EXT(), where 256 is the\n> \"disabled\" sentinel. The driver stored this state as a byte-packed\n> u32 map[] array plus a separate byte_mask[] bitmap tracking which\n> slots were enabled, because 256 does not fit in a byte. As a result\n> get_byte_map() had to consult byte_mask[] to decide whether to\n> report the stored byte or 256, and put_byte_map() had to keep the\n> two arrays in sync on every write.\n> \n> Store each slot as a u16 holding the control value directly\n> (0..255 enabled, 256 disabled). This is the native representation\n> for what userspace already sees, so get_byte_map() becomes a direct\n> return and put_byte_map() becomes a compare-and-store. The\n> hardware-facing packed RAM word and the IN_BYTE_EN mask are now\n> derived on the fly inside tegra210_adx_write_map_ram() from the\n> slot array, which is the only place that needs to know about the\n> hardware layout.\n> \n> The byte_mask scratch buffer is allocated dynamically using\n> kcalloc() based on soc_data->byte_mask_size, removing dependency\n> on SoC-specific constants. The byte_mask field is dropped from\n> struct tegra210_adx.\n\nSo this was already the case. However ...\n\n\n> -static void tegra210_adx_write_map_ram(struct tegra210_adx *adx)\n> +static int tegra210_adx_write_map_ram(struct tegra210_adx *adx)\n>   {\n> +\tconst unsigned int bits_per_mask = BITS_PER_TYPE(*adx->map) * BITS_PER_BYTE;\n> +\tunsigned int *byte_mask;\n>   \tint i;\n>   \n> +\tbyte_mask = kcalloc(adx->soc_data->byte_mask_size, sizeof(*byte_mask),\n> +\t\t\t    GFP_KERNEL);\n> +\tif (!byte_mask)\n> +\t\treturn -ENOMEM;\n> +\n\nNow you are allocating this everytime this function is called (which \nhappens on RPM resume) instead of ...\n\n> @@ -700,16 +706,15 @@ static int tegra210_adx_platform_probe(struct platform_device *pdev)\n>   \n>   \tregcache_cache_only(adx->regmap, true);\n>   \n> -\tadx->map = devm_kzalloc(dev, soc_data->ram_depth * sizeof(*adx->map),\n> -\t\t\t\tGFP_KERNEL);\n> +\tadx->map = devm_kcalloc(dev,\n> +\t\t\t\tsoc_data->ram_depth * TEGRA_ADX_SLOTS_PER_WORD,\n> +\t\t\t\tsizeof(*adx->map), GFP_KERNEL);\n>   \tif (!adx->map)\n>   \t\treturn -ENOMEM;\n>   \n> -\tadx->byte_mask = devm_kzalloc(dev,\n> -\t\t\t\t      soc_data->byte_mask_size * sizeof(*adx->byte_mask),\n> -\t\t\t\t      GFP_KERNEL);\n> -\tif (!adx->byte_mask)\n> -\t\treturn -ENOMEM;\n\n... here in the probe function, which makes more sense. IOW I am not \nsure why you have changed this.\n\nJon","headers":{"Return-Path":"\n <linux-tegra+bounces-13618-incoming=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=mcLwKX9l;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; helo=sto.lore.kernel.org;\n envelope-from=linux-tegra+bounces-13618-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=\"mcLwKX9l\"","smtp.subspace.kernel.org;\n arc=fail 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Thunderbird","Subject":"Re: [PATCH v2 1/2] ASoC: tegra210_adx: simplify byte map get/put\n logic","To":"Piyush Patle <piyushpatle228@gmail.com>, Mark Brown <broonie@kernel.org>","Cc":"Sheetal <sheetal@nvidia.com>, Thierry Reding <thierry.reding@gmail.com>,\n Liam Girdwood <lgirdwood@gmail.com>, Jaroslav Kysela <perex@perex.cz>,\n Takashi Iwai <tiwai@suse.com>,\n Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>,\n linux-sound@vger.kernel.org, linux-tegra@vger.kernel.org,\n linux-kernel@vger.kernel.org","References":"<20260407170308.100238-3-piyushpatle228@gmail.com>\n <20260408170818.70322-1-piyushpatle228@gmail.com>\n <20260408170818.70322-2-piyushpatle228@gmail.com>","From":"Jon Hunter <jonathanh@nvidia.com>","Content-Language":"en-US","In-Reply-To":"<20260408170818.70322-2-piyushpatle228@gmail.com>","Content-Type":"text/plain; charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","X-ClientProxiedBy":"DS7PR03CA0156.namprd03.prod.outlook.com\n (2603:10b6:5:3b2::11) To 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Brown","email":"broonie@kernel.org"},"content":"On Wed, Apr 08, 2026 at 10:38:17PM +0530, Piyush Patle wrote:\n\n> +static int tegra210_adx_write_map_ram(struct tegra210_adx *adx)\n>  {\n> +\tconst unsigned int bits_per_mask = BITS_PER_TYPE(*adx->map) * BITS_PER_BYTE;\n\nWhy are we multiplying by BITS_PER_BYTE here?  We've got a number of\nbits already from BITS_PER_TYPE().\n\n> +\tfor (i = 0; i < adx->soc_data->ram_depth; i++) {\n> +\t\tu32 word = 0;\n> +\t\tint b;\n> +\n> +\t\tfor (b = 0; b < TEGRA_ADX_SLOTS_PER_WORD; b++) {\n> +\t\t\tunsigned int slot = i * TEGRA_ADX_SLOTS_PER_WORD + b;\n> +\t\t\tu16 val = adx->map[slot];\n> +\n> +\t\t\tif (val >= 256)\n> +\t\t\t\tcontinue;\n> +\n> +\t\t\tword |= (u32)val << (b * BITS_PER_BYTE);\n> +\t\t\tbyte_mask[slot / bits_per_mask] |= 1U << (slot % bits_per_mask);\n\nHow big can bits_per_mask get?\n\n> @@ -118,9 +144,7 @@ static int tegra210_adx_runtime_resume(struct device *dev)\n>  \tregcache_cache_only(adx->regmap, false);\n>  \tregcache_sync(adx->regmap);\n>  \n> -\ttegra210_adx_write_map_ram(adx);\n> -\n> -\treturn 0;\n> +\treturn tegra210_adx_write_map_ram(adx);\n\nWe need to unwind at least the regcache_cache_only() above if resume\nfails.","headers":{"Return-Path":"\n <linux-tegra+bounces-13620-incoming=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=nkihFGBe;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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micalg=pgp-sha512;\n\tprotocol=\"application/pgp-signature\"; boundary=\"9uJ3Y4c7fwmPojbd\"","Content-Disposition":"inline","In-Reply-To":"<20260408170818.70322-2-piyushpatle228@gmail.com>","X-Cookie":"Often things ARE as bad as they seem!"}},{"id":3674997,"web_url":"http://patchwork.ozlabs.org/comment/3674997/","msgid":"<CAMB+xkaQAaJSZ6nJ_LN9zyRHxFAEMoydbb-BZc3t1qfr71Sd4A@mail.gmail.com>","list_archive_url":null,"date":"2026-04-08T21:19:26","subject":"Re: [PATCH v2 1/2] ASoC: tegra210_adx: simplify byte map get/put\n logic","submitter":{"id":92665,"url":"http://patchwork.ozlabs.org/api/people/92665/","name":"Piyush Patle","email":"piyushpatle228@gmail.com"},"content":"On Wed, Apr 8, 2026 at 11:09 PM Jon Hunter <jonathanh@nvidia.com> wrote:\n>\n>\n> On 08/04/2026 18:08, Piyush Patle wrote:\n> > The byte-map controls (\"Byte Map N\") already expose a value range of\n> > [0, 256] to userspace via SOC_SINGLE_EXT(), where 256 is the\n> > \"disabled\" sentinel. The driver stored this state as a byte-packed\n> > u32 map[] array plus a separate byte_mask[] bitmap tracking which\n> > slots were enabled, because 256 does not fit in a byte. As a result\n> > get_byte_map() had to consult byte_mask[] to decide whether to\n> > report the stored byte or 256, and put_byte_map() had to keep the\n> > two arrays in sync on every write.\n> >\n> > Store each slot as a u16 holding the control value directly\n> > (0..255 enabled, 256 disabled). This is the native representation\n> > for what userspace already sees, so get_byte_map() becomes a direct\n> > return and put_byte_map() becomes a compare-and-store. The\n> > hardware-facing packed RAM word and the IN_BYTE_EN mask are now\n> > derived on the fly inside tegra210_adx_write_map_ram() from the\n> > slot array, which is the only place that needs to know about the\n> > hardware layout.\n> >\n> > The byte_mask scratch buffer is allocated dynamically using\n> > kcalloc() based on soc_data->byte_mask_size, removing dependency\n> > on SoC-specific constants. The byte_mask field is dropped from\n> > struct tegra210_adx.\n>\n> So this was already the case. However ...\n>\n>\n> > -static void tegra210_adx_write_map_ram(struct tegra210_adx *adx)\n> > +static int tegra210_adx_write_map_ram(struct tegra210_adx *adx)\n> >   {\n> > +     const unsigned int bits_per_mask = BITS_PER_TYPE(*adx->map) * BITS_PER_BYTE;\n> > +     unsigned int *byte_mask;\n> >       int i;\n> >\n> > +     byte_mask = kcalloc(adx->soc_data->byte_mask_size, sizeof(*byte_mask),\n> > +                         GFP_KERNEL);\n> > +     if (!byte_mask)\n> > +             return -ENOMEM;\n> > +\n>\n> Now you are allocating this everytime this function is called (which\n> happens on RPM resume) instead of ...\n\nYou're right, I was wrong here. I read Sheetal's v1comment as\n\"allocate it dynamically\" and over-corrected by moving the\nallocation into write_map_ram() itself.\n\n>\n> > @@ -700,16 +706,15 @@ static int tegra210_adx_platform_probe(struct platform_device *pdev)\n> >\n> >       regcache_cache_only(adx->regmap, true);\n> >\n> > -     adx->map = devm_kzalloc(dev, soc_data->ram_depth * sizeof(*adx->map),\n> > -                             GFP_KERNEL);\n> > +     adx->map = devm_kcalloc(dev,\n> > +                             soc_data->ram_depth * TEGRA_ADX_SLOTS_PER_WORD,\n> > +                             sizeof(*adx->map), GFP_KERNEL);\n> >       if (!adx->map)\n> >               return -ENOMEM;\n> >\n> > -     adx->byte_mask = devm_kzalloc(dev,\n> > -                                   soc_data->byte_mask_size * sizeof(*adx->byte_mask),\n> > -                                   GFP_KERNEL);\n> > -     if (!adx->byte_mask)\n> > -             return -ENOMEM;\n>\n> ... here in the probe function, which makes more sense. IOW I am not\n> sure why you have changed this.\n>\n>\nThe intent was only to drop the dependency on\nthe SoC-specific TEGRA264_*_BYTE_MASK_COUNT\nconstant; the lifetime should still be probe-scoped\n\nFor v3 I'll keep byte_mask as a member of struct tegra210_adx and\nallocate it once in probe() with:\n\n  adx->byte_mask = devm_kcalloc(dev, soc_data->byte_mask_size,\n                               sizeof(*adx->byte_mask),\n                               GFP_KERNEL);\n\nThat keeps Sheetal's \"no chip-specific constant\" requirement (size\nis still soc_data->byte_mask_size) while avoiding the per-RPM-resume\nallocation.\nI think that would be better, Right?\n\nSame change in tegra210_amx.c.","headers":{"Return-Path":"\n <linux-tegra+bounces-13625-incoming=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=F8KQW8Bm;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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Wed, 08 Apr 2026\n 14:20:07 -0700 (PDT)","Precedence":"bulk","X-Mailing-List":"linux-tegra@vger.kernel.org","List-Id":"<linux-tegra.vger.kernel.org>","List-Subscribe":"<mailto:linux-tegra+subscribe@vger.kernel.org>","List-Unsubscribe":"<mailto:linux-tegra+unsubscribe@vger.kernel.org>","MIME-Version":"1.0","References":"<20260407170308.100238-3-piyushpatle228@gmail.com>\n <20260408170818.70322-1-piyushpatle228@gmail.com>\n <20260408170818.70322-2-piyushpatle228@gmail.com>\n <f837da45-2b31-4788-a957-085d3f0570d0@nvidia.com>","In-Reply-To":"<f837da45-2b31-4788-a957-085d3f0570d0@nvidia.com>","From":"Piyush Patle <piyushpatle228@gmail.com>","Date":"Thu, 9 Apr 2026 02:49:26 +0530","X-Gm-Features":"AQROBzBUy-it-vv-kjO6ebLVhc04dn2olvWf_81zN6zTyAHrTx2NmaM7LrDNOQo","Message-ID":"\n <CAMB+xkaQAaJSZ6nJ_LN9zyRHxFAEMoydbb-BZc3t1qfr71Sd4A@mail.gmail.com>","Subject":"Re: [PATCH v2 1/2] ASoC: tegra210_adx: simplify byte map get/put\n logic","To":"Jon Hunter <jonathanh@nvidia.com>","Cc":"Mark Brown <broonie@kernel.org>, Sheetal <sheetal@nvidia.com>,\n\tThierry Reding <thierry.reding@gmail.com>,\n Liam Girdwood <lgirdwood@gmail.com>,\n\tJaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.com>,\n\tKuninori Morimoto <kuninori.morimoto.gx@renesas.com>,\n linux-sound@vger.kernel.org,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable"}},{"id":3675000,"web_url":"http://patchwork.ozlabs.org/comment/3675000/","msgid":"<CAMB+xkZbxeOvfjH5kWQxZXJ792wZSWJntw+wO90__artt71+=w@mail.gmail.com>","list_archive_url":null,"date":"2026-04-08T21:25:25","subject":"Re: [PATCH v2 1/2] ASoC: tegra210_adx: simplify byte map get/put\n logic","submitter":{"id":92665,"url":"http://patchwork.ozlabs.org/api/people/92665/","name":"Piyush Patle","email":"piyushpatle228@gmail.com"},"content":"> > +static int tegra210_adx_write_map_ram(struct tegra210_adx *adx)\n> >  {\n> > +     const unsigned int bits_per_mask = BITS_PER_TYPE(*adx->map) * BITS_PER_BYTE;\n>\n> Why are we multiplying by BITS_PER_BYTE here?  We've got a number of\n> bits already from BITS_PER_TYPE().\n\nOkay correct, that's a bug BITS_PER_TYPE() already returns bits,\nso the extra * BITS_PER_BYTE is a unit error. It also references\nthe wrong type: the bitmap word is unsigned int (which is what the\noriginal code's hard-coded 32 came from), not the map element type.\n\nFor v3 I'll change it to:\n    const unsigned int bits_per_mask = BITS_PER_TYPE(*adx->byte_mask);\n\n>\n> > +     for (i = 0; i < adx->soc_data->ram_depth; i++) {\n> > +             u32 word = 0;\n> > +             int b;\n> > +\n> > +             for (b = 0; b < TEGRA_ADX_SLOTS_PER_WORD; b++) {\n> > +                     unsigned int slot = i * TEGRA_ADX_SLOTS_PER_WORD + b;\n> > +                     u16 val = adx->map[slot];\n> > +\n> > +                     if (val >= 256)\n> > +                             continue;\n> > +\n> > +                     word |= (u32)val << (b * BITS_PER_BYTE);\n> > +                     byte_mask[slot / bits_per_mask] |= 1U << (slot % bits_per_mask);\n>\n> How big can bits_per_mask get?\n\nWith the fix above, bits_per_mask == BITS_PER_TYPE(unsigned int) ==\n32,\nmatching the original \"slot / 32\" / \"slot % 32\" expressions exactly.\n\n>\n> > @@ -118,9 +144,7 @@ static int tegra210_adx_runtime_resume(struct device *dev)\n> >       regcache_cache_only(adx->regmap, false);\n> >       regcache_sync(adx->regmap);\n> >\n> > -     tegra210_adx_write_map_ram(adx);\n> > -\n> > -     return 0;\n> > +     return tegra210_adx_write_map_ram(adx);\n>\n> We need to unwind at least the regcache_cache_only() above if resume\n> fails.\n\nAs per Jon's comment on the same patch, I'm moving the\nbyte_mask buffer back to a probe-time devm_kcalloc() in v3, so\nwrite_map_ram() no longer has a failure path. runtime_resume() will\ngo back to returning 0 unconditionally and the regcache_cache_only()\nunwind won't be needed. If write_map_ram() ever grows another failure\nmode in the future, the unwind would have to be added then.\n\nThanks\nPiyush Patle","headers":{"Return-Path":"\n <linux-tegra+bounces-13630-incoming=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=CTndhkJQ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-tegra+bounces-13630-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com\n header.b=\"CTndhkJQ\"","smtp.subspace.kernel.org;\n arc=pass smtp.client-ip=209.85.208.170","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=gmail.com"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frbkm1jqFz1yD3\n\tfor <incoming@patchwork.ozlabs.org>; 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Wed, 08 Apr 2026\n 14:26:05 -0700 (PDT)","Precedence":"bulk","X-Mailing-List":"linux-tegra@vger.kernel.org","List-Id":"<linux-tegra.vger.kernel.org>","List-Subscribe":"<mailto:linux-tegra+subscribe@vger.kernel.org>","List-Unsubscribe":"<mailto:linux-tegra+unsubscribe@vger.kernel.org>","MIME-Version":"1.0","References":"<20260407170308.100238-3-piyushpatle228@gmail.com>\n <20260408170818.70322-1-piyushpatle228@gmail.com>\n <20260408170818.70322-2-piyushpatle228@gmail.com>\n <ae440ab7-e1ba-4f38-8ef9-85371f3236f0@sirena.org.uk>","In-Reply-To":"<ae440ab7-e1ba-4f38-8ef9-85371f3236f0@sirena.org.uk>","From":"Piyush Patle <piyushpatle228@gmail.com>","Date":"Thu, 9 Apr 2026 02:55:25 +0530","X-Gm-Features":"AQROBzBu6KzdQPIYr38nwiFPhnZEm0vYHac0EK6sgh9vp6wbo8mZ1lzGfAkVeSI","Message-ID":"\n <CAMB+xkZbxeOvfjH5kWQxZXJ792wZSWJntw+wO90__artt71+=w@mail.gmail.com>","Subject":"Re: [PATCH v2 1/2] ASoC: tegra210_adx: simplify byte map get/put\n logic","To":"Mark Brown <broonie@kernel.org>","Cc":"Sheetal <sheetal@nvidia.com>, Jonathan Hunter <jonathanh@nvidia.com>,\n\tThierry Reding <thierry.reding@gmail.com>,\n Liam Girdwood <lgirdwood@gmail.com>,\n\tJaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.com>,\n\tKuninori Morimoto <kuninori.morimoto.gx@renesas.com>,\n linux-sound@vger.kernel.org,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org","Content-Type":"text/plain; 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