[{"id":3675041,"web_url":"http://patchwork.ozlabs.org/comment/3675041/","msgid":"","list_archive_url":null,"date":"2026-04-09T01:50:50","subject":"Re: [PATCH v2 2/2] pinctrl: qcom: Add Hawi pinctrl driver","submitter":{"id":84725,"url":"http://patchwork.ozlabs.org/api/people/84725/","name":"Bjorn Andersson","email":"andersson@kernel.org"},"content":"On Wed, Apr 08, 2026 at 07:45:48PM +0530, Mukesh Ojha wrote:\n> Add pinctrl driver for TLMM block found in the Hawi SoC.\n> \n> Reviewed-by: Konrad Dybcio \n> Signed-off-by: Mukesh Ojha \n\nThanks for updating those functions.\n\nReviewed-by: Bjorn Andersson \n\nRegards,\nBjorn\n\n> ---\n> drivers/pinctrl/qcom/Kconfig.msm | 10 +\n> drivers/pinctrl/qcom/Makefile | 1 +\n> drivers/pinctrl/qcom/pinctrl-hawi.c | 1610 +++++++++++++++++++++++++++++++++++\n> 3 files changed, 1621 insertions(+)\n> \n> diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm\n> index 17416dce8e70..836cdeca1006 100644\n> --- a/drivers/pinctrl/qcom/Kconfig.msm\n> +++ b/drivers/pinctrl/qcom/Kconfig.msm\n> @@ -35,6 +35,16 @@ config PINCTRL_GLYMUR\n> \t Say Y here to compile statically, or M here to compile it as a module.\n> \t If unsure, say N.\n> \n> +config PINCTRL_HAWI\n> +\ttristate \"Qualcomm Technologies Inc Hawi pin controller driver\"\n> +\tdepends on ARM64 || COMPILE_TEST\n> +\thelp\n> +\t This is the pinctrl, pinmux, pinconf and gpiolib driver for the\n> +\t Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM)\n> +\t block found on the Qualcomm Technologies Inc Hawi platform.\n> +\t Say Y here to compile statically, or M here to compile it as a module.\n> +\t If unsure, say N.\n> +\n> config PINCTRL_IPQ4019\n> \ttristate \"Qualcomm IPQ4019 pin controller driver\"\n> \tdepends on ARM || COMPILE_TEST\n> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile\n> index 4c585bad813c..84bda3ada874 100644\n> --- a/drivers/pinctrl/qcom/Makefile\n> +++ b/drivers/pinctrl/qcom/Makefile\n> @@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_APQ8064)\t+= pinctrl-apq8064.o\n> obj-$(CONFIG_PINCTRL_APQ8084)\t+= pinctrl-apq8084.o\n> obj-$(CONFIG_PINCTRL_ELIZA)\t+= pinctrl-eliza.o\n> obj-$(CONFIG_PINCTRL_GLYMUR)\t+= pinctrl-glymur.o\n> +obj-$(CONFIG_PINCTRL_HAWI)\t+= pinctrl-hawi.o\n> obj-$(CONFIG_PINCTRL_IPQ4019)\t+= pinctrl-ipq4019.o\n> obj-$(CONFIG_PINCTRL_IPQ5018)\t+= pinctrl-ipq5018.o\n> obj-$(CONFIG_PINCTRL_IPQ8064)\t+= pinctrl-ipq8064.o\n> diff --git a/drivers/pinctrl/qcom/pinctrl-hawi.c b/drivers/pinctrl/qcom/pinctrl-hawi.c\n> new file mode 100644\n> index 000000000000..5c7894f3b9cb\n> --- /dev/null\n> +++ b/drivers/pinctrl/qcom/pinctrl-hawi.c\n> @@ -0,0 +1,1610 @@\n> +// SPDX-License-Identifier: GPL-2.0-only\n> +/*\n> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +\n> +#include \"pinctrl-msm.h\"\n> +\n> +#define REG_SIZE 0x1000\n> +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \\\n> +\t{\t\t\t\t\t\t\\\n> +\t\t.grp = PINCTRL_PINGROUP(\"gpio\" #id,\t\\\n> +\t\t\tgpio##id##_pins,\t\t\\\n> +\t\t\tARRAY_SIZE(gpio##id##_pins)),\t\\\n> +\t\t.funcs = (int[]){\t\t\t\\\n> +\t\t\tmsm_mux_gpio, /* gpio mode */\t\\\n> +\t\t\tmsm_mux_##f1,\t\t\t\\\n> +\t\t\tmsm_mux_##f2,\t\t\t\\\n> +\t\t\tmsm_mux_##f3,\t\t\t\\\n> +\t\t\tmsm_mux_##f4,\t\t\t\\\n> +\t\t\tmsm_mux_##f5,\t\t\t\\\n> +\t\t\tmsm_mux_##f6,\t\t\t\\\n> +\t\t\tmsm_mux_##f7,\t\t\t\\\n> +\t\t\tmsm_mux_##f8,\t\t\t\\\n> +\t\t\tmsm_mux_##f9,\t\t\t\\\n> +\t\t\tmsm_mux_##f10,\t\t\t\\\n> +\t\t\tmsm_mux_##f11 /* egpio mode */\t\\\n> +\t\t},\t\t\t\t\t\\\n> +\t\t.nfuncs = 12,\t\t\t\t\\\n> +\t\t.ctl_reg = REG_SIZE * id,\t\t\\\n> +\t\t.io_reg = 0x4 + REG_SIZE * id,\t\t\\\n> +\t\t.intr_cfg_reg = 0x8 + REG_SIZE * id,\t\\\n> +\t\t.intr_status_reg = 0xc + REG_SIZE * id,\t\\\n> +\t\t.mux_bit = 2,\t\t\t\t\\\n> +\t\t.pull_bit = 0,\t\t\t\t\\\n> +\t\t.drv_bit = 6,\t\t\t\t\\\n> +\t\t.egpio_enable = 12,\t\t\t\\\n> +\t\t.egpio_present = 11,\t\t\t\\\n> +\t\t.oe_bit = 9,\t\t\t\t\\\n> +\t\t.in_bit = 0,\t\t\t\t\\\n> +\t\t.out_bit = 1,\t\t\t\t\\\n> +\t\t.intr_enable_bit = 0,\t\t\t\\\n> +\t\t.intr_status_bit = 0,\t\t\t\\\n> +\t\t.intr_wakeup_present_bit = 6,\t\\\n> +\t\t.intr_wakeup_enable_bit = 7,\t\\\n> +\t\t.intr_target_bit = 8,\t\t\t\\\n> +\t\t.intr_target_kpss_val = 3,\t\t\\\n> +\t\t.intr_raw_status_bit = 4,\t\t\\\n> +\t\t.intr_polarity_bit = 1,\t\t\t\\\n> +\t\t.intr_detection_bit = 2,\t\t\\\n> +\t\t.intr_detection_width = 2,\t\t\\\n> +\t}\n> +\n> +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv)\t\\\n> +\t{\t\t\t\t\t \\\n> +\t\t.grp = PINCTRL_PINGROUP(#pg_name,\t\\\n> +\t\t\tpg_name##_pins,\t\t\t\\\n> +\t\t\tARRAY_SIZE(pg_name##_pins)),\t\\\n> +\t\t.ctl_reg = ctl,\t\t\t\t\\\n> +\t\t.io_reg = 0,\t\t\t\t\\\n> +\t\t.intr_cfg_reg = 0,\t\t\t\\\n> +\t\t.intr_status_reg = 0,\t\t\t\\\n> +\t\t.intr_target_reg = 0,\t\t\t\\\n> +\t\t.mux_bit = -1,\t\t\t\t\\\n> +\t\t.pull_bit = pull,\t\t\t\\\n> +\t\t.drv_bit = drv,\t\t\t\t\\\n> +\t\t.oe_bit = -1,\t\t\t\t\\\n> +\t\t.in_bit = -1,\t\t\t\t\\\n> +\t\t.out_bit = -1,\t\t\t\t\\\n> +\t\t.intr_enable_bit = -1,\t\t\t\\\n> +\t\t.intr_status_bit = -1,\t\t\t\\\n> +\t\t.intr_target_bit = -1,\t\t\t\\\n> +\t\t.intr_raw_status_bit = -1,\t\t\\\n> +\t\t.intr_polarity_bit = -1,\t\t\\\n> +\t\t.intr_detection_bit = -1,\t\t\\\n> +\t\t.intr_detection_width = -1,\t\t\\\n> +\t}\n> +\n> +#define UFS_RESET(pg_name, ctl, io)\t\t\t\\\n> +\t{\t\t\t\t\t\t\\\n> +\t\t.grp = PINCTRL_PINGROUP(#pg_name,\t\\\n> +\t\t\tpg_name##_pins,\t\t\t\\\n> +\t\t\tARRAY_SIZE(pg_name##_pins)),\t\\\n> +\t\t.ctl_reg = ctl,\t\t\t\t\\\n> +\t\t.io_reg = io,\t\t\t\t\\\n> +\t\t.intr_cfg_reg = 0,\t\t\t\\\n> +\t\t.intr_status_reg = 0,\t\t\t\\\n> +\t\t.intr_target_reg = 0,\t\t\t\\\n> +\t\t.mux_bit = -1,\t\t\t\t\\\n> +\t\t.pull_bit = 3,\t\t\t\t\\\n> +\t\t.drv_bit = 0,\t\t\t\t\\\n> +\t\t.oe_bit = -1,\t\t\t\t\\\n> +\t\t.in_bit = -1,\t\t\t\t\\\n> +\t\t.out_bit = 0,\t\t\t\t\\\n> +\t\t.intr_enable_bit = -1,\t\t\t\\\n> +\t\t.intr_status_bit = -1,\t\t\t\\\n> +\t\t.intr_target_bit = -1,\t\t\t\\\n> +\t\t.intr_raw_status_bit = -1,\t\t\\\n> +\t\t.intr_polarity_bit = -1,\t\t\\\n> +\t\t.intr_detection_bit = -1,\t\t\\\n> +\t\t.intr_detection_width = -1,\t\t\\\n> +\t}\n> +\n> +static const struct pinctrl_pin_desc hawi_pins[] = {\n> +\tPINCTRL_PIN(0, \"GPIO_0\"),\n> +\tPINCTRL_PIN(1, \"GPIO_1\"),\n> +\tPINCTRL_PIN(2, \"GPIO_2\"),\n> +\tPINCTRL_PIN(3, \"GPIO_3\"),\n> +\tPINCTRL_PIN(4, \"GPIO_4\"),\n> +\tPINCTRL_PIN(5, \"GPIO_5\"),\n> +\tPINCTRL_PIN(6, \"GPIO_6\"),\n> +\tPINCTRL_PIN(7, \"GPIO_7\"),\n> +\tPINCTRL_PIN(8, \"GPIO_8\"),\n> +\tPINCTRL_PIN(9, \"GPIO_9\"),\n> +\tPINCTRL_PIN(10, \"GPIO_10\"),\n> +\tPINCTRL_PIN(11, \"GPIO_11\"),\n> +\tPINCTRL_PIN(12, \"GPIO_12\"),\n> +\tPINCTRL_PIN(13, \"GPIO_13\"),\n> +\tPINCTRL_PIN(14, \"GPIO_14\"),\n> +\tPINCTRL_PIN(15, \"GPIO_15\"),\n> +\tPINCTRL_PIN(16, \"GPIO_16\"),\n> +\tPINCTRL_PIN(17, \"GPIO_17\"),\n> +\tPINCTRL_PIN(18, \"GPIO_18\"),\n> +\tPINCTRL_PIN(19, \"GPIO_19\"),\n> +\tPINCTRL_PIN(20, \"GPIO_20\"),\n> +\tPINCTRL_PIN(21, \"GPIO_21\"),\n> +\tPINCTRL_PIN(22, \"GPIO_22\"),\n> +\tPINCTRL_PIN(23, \"GPIO_23\"),\n> +\tPINCTRL_PIN(24, \"GPIO_24\"),\n> +\tPINCTRL_PIN(25, \"GPIO_25\"),\n> +\tPINCTRL_PIN(26, \"GPIO_26\"),\n> +\tPINCTRL_PIN(27, \"GPIO_27\"),\n> +\tPINCTRL_PIN(28, \"GPIO_28\"),\n> +\tPINCTRL_PIN(29, \"GPIO_29\"),\n> +\tPINCTRL_PIN(30, \"GPIO_30\"),\n> +\tPINCTRL_PIN(31, \"GPIO_31\"),\n> +\tPINCTRL_PIN(32, \"GPIO_32\"),\n> +\tPINCTRL_PIN(33, \"GPIO_33\"),\n> +\tPINCTRL_PIN(34, \"GPIO_34\"),\n> +\tPINCTRL_PIN(35, \"GPIO_35\"),\n> +\tPINCTRL_PIN(36, \"GPIO_36\"),\n> +\tPINCTRL_PIN(37, \"GPIO_37\"),\n> +\tPINCTRL_PIN(38, \"GPIO_38\"),\n> +\tPINCTRL_PIN(39, \"GPIO_39\"),\n> +\tPINCTRL_PIN(40, \"GPIO_40\"),\n> +\tPINCTRL_PIN(41, \"GPIO_41\"),\n> +\tPINCTRL_PIN(42, \"GPIO_42\"),\n> +\tPINCTRL_PIN(43, \"GPIO_43\"),\n> +\tPINCTRL_PIN(44, \"GPIO_44\"),\n> +\tPINCTRL_PIN(45, \"GPIO_45\"),\n> +\tPINCTRL_PIN(46, \"GPIO_46\"),\n> +\tPINCTRL_PIN(47, \"GPIO_47\"),\n> +\tPINCTRL_PIN(48, \"GPIO_48\"),\n> +\tPINCTRL_PIN(49, \"GPIO_49\"),\n> +\tPINCTRL_PIN(50, \"GPIO_50\"),\n> +\tPINCTRL_PIN(51, \"GPIO_51\"),\n> +\tPINCTRL_PIN(52, \"GPIO_52\"),\n> +\tPINCTRL_PIN(53, \"GPIO_53\"),\n> +\tPINCTRL_PIN(54, \"GPIO_54\"),\n> +\tPINCTRL_PIN(55, \"GPIO_55\"),\n> +\tPINCTRL_PIN(56, \"GPIO_56\"),\n> +\tPINCTRL_PIN(57, \"GPIO_57\"),\n> +\tPINCTRL_PIN(58, \"GPIO_58\"),\n> +\tPINCTRL_PIN(59, \"GPIO_59\"),\n> +\tPINCTRL_PIN(60, \"GPIO_60\"),\n> +\tPINCTRL_PIN(61, \"GPIO_61\"),\n> +\tPINCTRL_PIN(62, \"GPIO_62\"),\n> +\tPINCTRL_PIN(63, \"GPIO_63\"),\n> +\tPINCTRL_PIN(64, \"GPIO_64\"),\n> +\tPINCTRL_PIN(65, \"GPIO_65\"),\n> +\tPINCTRL_PIN(66, \"GPIO_66\"),\n> +\tPINCTRL_PIN(67, \"GPIO_67\"),\n> +\tPINCTRL_PIN(68, \"GPIO_68\"),\n> +\tPINCTRL_PIN(69, \"GPIO_69\"),\n> +\tPINCTRL_PIN(70, \"GPIO_70\"),\n> +\tPINCTRL_PIN(71, \"GPIO_71\"),\n> +\tPINCTRL_PIN(72, \"GPIO_72\"),\n> +\tPINCTRL_PIN(73, \"GPIO_73\"),\n> +\tPINCTRL_PIN(74, \"GPIO_74\"),\n> +\tPINCTRL_PIN(75, \"GPIO_75\"),\n> +\tPINCTRL_PIN(76, \"GPIO_76\"),\n> +\tPINCTRL_PIN(77, \"GPIO_77\"),\n> +\tPINCTRL_PIN(78, \"GPIO_78\"),\n> +\tPINCTRL_PIN(79, \"GPIO_79\"),\n> +\tPINCTRL_PIN(80, \"GPIO_80\"),\n> +\tPINCTRL_PIN(81, \"GPIO_81\"),\n> +\tPINCTRL_PIN(82, \"GPIO_82\"),\n> +\tPINCTRL_PIN(83, \"GPIO_83\"),\n> +\tPINCTRL_PIN(84, \"GPIO_84\"),\n> +\tPINCTRL_PIN(85, \"GPIO_85\"),\n> +\tPINCTRL_PIN(86, \"GPIO_86\"),\n> +\tPINCTRL_PIN(87, \"GPIO_87\"),\n> +\tPINCTRL_PIN(88, \"GPIO_88\"),\n> +\tPINCTRL_PIN(89, \"GPIO_89\"),\n> +\tPINCTRL_PIN(90, \"GPIO_90\"),\n> +\tPINCTRL_PIN(91, \"GPIO_91\"),\n> +\tPINCTRL_PIN(92, \"GPIO_92\"),\n> +\tPINCTRL_PIN(93, \"GPIO_93\"),\n> +\tPINCTRL_PIN(94, \"GPIO_94\"),\n> +\tPINCTRL_PIN(95, \"GPIO_95\"),\n> +\tPINCTRL_PIN(96, \"GPIO_96\"),\n> +\tPINCTRL_PIN(97, \"GPIO_97\"),\n> +\tPINCTRL_PIN(98, \"GPIO_98\"),\n> +\tPINCTRL_PIN(99, \"GPIO_99\"),\n> +\tPINCTRL_PIN(100, \"GPIO_100\"),\n> +\tPINCTRL_PIN(101, \"GPIO_101\"),\n> +\tPINCTRL_PIN(102, \"GPIO_102\"),\n> +\tPINCTRL_PIN(103, \"GPIO_103\"),\n> +\tPINCTRL_PIN(104, \"GPIO_104\"),\n> +\tPINCTRL_PIN(105, \"GPIO_105\"),\n> +\tPINCTRL_PIN(106, \"GPIO_106\"),\n> +\tPINCTRL_PIN(107, \"GPIO_107\"),\n> +\tPINCTRL_PIN(108, \"GPIO_108\"),\n> +\tPINCTRL_PIN(109, \"GPIO_109\"),\n> +\tPINCTRL_PIN(110, \"GPIO_110\"),\n> +\tPINCTRL_PIN(111, \"GPIO_111\"),\n> +\tPINCTRL_PIN(112, \"GPIO_112\"),\n> +\tPINCTRL_PIN(113, \"GPIO_113\"),\n> +\tPINCTRL_PIN(114, \"GPIO_114\"),\n> +\tPINCTRL_PIN(115, \"GPIO_115\"),\n> +\tPINCTRL_PIN(116, \"GPIO_116\"),\n> +\tPINCTRL_PIN(117, \"GPIO_117\"),\n> +\tPINCTRL_PIN(118, \"GPIO_118\"),\n> +\tPINCTRL_PIN(119, \"GPIO_119\"),\n> +\tPINCTRL_PIN(120, \"GPIO_120\"),\n> +\tPINCTRL_PIN(121, \"GPIO_121\"),\n> +\tPINCTRL_PIN(122, \"GPIO_122\"),\n> +\tPINCTRL_PIN(123, \"GPIO_123\"),\n> +\tPINCTRL_PIN(124, \"GPIO_124\"),\n> +\tPINCTRL_PIN(125, \"GPIO_125\"),\n> +\tPINCTRL_PIN(126, \"GPIO_126\"),\n> +\tPINCTRL_PIN(127, \"GPIO_127\"),\n> +\tPINCTRL_PIN(128, \"GPIO_128\"),\n> +\tPINCTRL_PIN(129, \"GPIO_129\"),\n> +\tPINCTRL_PIN(130, \"GPIO_130\"),\n> +\tPINCTRL_PIN(131, \"GPIO_131\"),\n> +\tPINCTRL_PIN(132, \"GPIO_132\"),\n> +\tPINCTRL_PIN(133, \"GPIO_133\"),\n> +\tPINCTRL_PIN(134, \"GPIO_134\"),\n> +\tPINCTRL_PIN(135, \"GPIO_135\"),\n> +\tPINCTRL_PIN(136, \"GPIO_136\"),\n> +\tPINCTRL_PIN(137, \"GPIO_137\"),\n> +\tPINCTRL_PIN(138, \"GPIO_138\"),\n> +\tPINCTRL_PIN(139, \"GPIO_139\"),\n> +\tPINCTRL_PIN(140, \"GPIO_140\"),\n> +\tPINCTRL_PIN(141, \"GPIO_141\"),\n> +\tPINCTRL_PIN(142, \"GPIO_142\"),\n> +\tPINCTRL_PIN(143, \"GPIO_143\"),\n> +\tPINCTRL_PIN(144, \"GPIO_144\"),\n> +\tPINCTRL_PIN(145, \"GPIO_145\"),\n> +\tPINCTRL_PIN(146, \"GPIO_146\"),\n> +\tPINCTRL_PIN(147, \"GPIO_147\"),\n> +\tPINCTRL_PIN(148, \"GPIO_148\"),\n> +\tPINCTRL_PIN(149, \"GPIO_149\"),\n> +\tPINCTRL_PIN(150, \"GPIO_150\"),\n> +\tPINCTRL_PIN(151, \"GPIO_151\"),\n> +\tPINCTRL_PIN(152, \"GPIO_152\"),\n> +\tPINCTRL_PIN(153, \"GPIO_153\"),\n> +\tPINCTRL_PIN(154, \"GPIO_154\"),\n> +\tPINCTRL_PIN(155, \"GPIO_155\"),\n> +\tPINCTRL_PIN(156, \"GPIO_156\"),\n> +\tPINCTRL_PIN(157, \"GPIO_157\"),\n> +\tPINCTRL_PIN(158, \"GPIO_158\"),\n> +\tPINCTRL_PIN(159, \"GPIO_159\"),\n> +\tPINCTRL_PIN(160, \"GPIO_160\"),\n> +\tPINCTRL_PIN(161, \"GPIO_161\"),\n> +\tPINCTRL_PIN(162, \"GPIO_162\"),\n> +\tPINCTRL_PIN(163, \"GPIO_163\"),\n> +\tPINCTRL_PIN(164, \"GPIO_164\"),\n> +\tPINCTRL_PIN(165, \"GPIO_165\"),\n> +\tPINCTRL_PIN(166, \"GPIO_166\"),\n> +\tPINCTRL_PIN(167, \"GPIO_167\"),\n> +\tPINCTRL_PIN(168, \"GPIO_168\"),\n> +\tPINCTRL_PIN(169, \"GPIO_169\"),\n> +\tPINCTRL_PIN(170, \"GPIO_170\"),\n> +\tPINCTRL_PIN(171, \"GPIO_171\"),\n> +\tPINCTRL_PIN(172, \"GPIO_172\"),\n> +\tPINCTRL_PIN(173, \"GPIO_173\"),\n> +\tPINCTRL_PIN(174, \"GPIO_174\"),\n> +\tPINCTRL_PIN(175, \"GPIO_175\"),\n> +\tPINCTRL_PIN(176, \"GPIO_176\"),\n> +\tPINCTRL_PIN(177, \"GPIO_177\"),\n> +\tPINCTRL_PIN(178, \"GPIO_178\"),\n> +\tPINCTRL_PIN(179, \"GPIO_179\"),\n> +\tPINCTRL_PIN(180, \"GPIO_180\"),\n> +\tPINCTRL_PIN(181, \"GPIO_181\"),\n> +\tPINCTRL_PIN(182, \"GPIO_182\"),\n> +\tPINCTRL_PIN(183, \"GPIO_183\"),\n> +\tPINCTRL_PIN(184, \"GPIO_184\"),\n> +\tPINCTRL_PIN(185, \"GPIO_185\"),\n> +\tPINCTRL_PIN(186, \"GPIO_186\"),\n> +\tPINCTRL_PIN(187, \"GPIO_187\"),\n> +\tPINCTRL_PIN(188, \"GPIO_188\"),\n> +\tPINCTRL_PIN(189, \"GPIO_189\"),\n> +\tPINCTRL_PIN(190, \"GPIO_190\"),\n> +\tPINCTRL_PIN(191, \"GPIO_191\"),\n> +\tPINCTRL_PIN(192, \"GPIO_192\"),\n> +\tPINCTRL_PIN(193, \"GPIO_193\"),\n> +\tPINCTRL_PIN(194, \"GPIO_194\"),\n> +\tPINCTRL_PIN(195, \"GPIO_195\"),\n> +\tPINCTRL_PIN(196, \"GPIO_196\"),\n> +\tPINCTRL_PIN(197, \"GPIO_197\"),\n> +\tPINCTRL_PIN(198, \"GPIO_198\"),\n> +\tPINCTRL_PIN(199, \"GPIO_199\"),\n> +\tPINCTRL_PIN(200, \"GPIO_200\"),\n> +\tPINCTRL_PIN(201, \"GPIO_201\"),\n> +\tPINCTRL_PIN(202, \"GPIO_202\"),\n> +\tPINCTRL_PIN(203, \"GPIO_203\"),\n> +\tPINCTRL_PIN(204, \"GPIO_204\"),\n> +\tPINCTRL_PIN(205, \"GPIO_205\"),\n> +\tPINCTRL_PIN(206, \"GPIO_206\"),\n> +\tPINCTRL_PIN(207, \"GPIO_207\"),\n> +\tPINCTRL_PIN(208, \"GPIO_208\"),\n> +\tPINCTRL_PIN(209, \"GPIO_209\"),\n> +\tPINCTRL_PIN(210, \"GPIO_210\"),\n> +\tPINCTRL_PIN(211, \"GPIO_211\"),\n> +\tPINCTRL_PIN(212, \"GPIO_212\"),\n> +\tPINCTRL_PIN(213, \"GPIO_213\"),\n> +\tPINCTRL_PIN(214, \"GPIO_214\"),\n> +\tPINCTRL_PIN(215, \"GPIO_215\"),\n> +\tPINCTRL_PIN(216, \"GPIO_216\"),\n> +\tPINCTRL_PIN(217, \"GPIO_217\"),\n> +\tPINCTRL_PIN(218, \"GPIO_218\"),\n> +\tPINCTRL_PIN(219, \"GPIO_219\"),\n> +\tPINCTRL_PIN(220, \"GPIO_220\"),\n> +\tPINCTRL_PIN(221, \"GPIO_221\"),\n> +\tPINCTRL_PIN(222, \"GPIO_222\"),\n> +\tPINCTRL_PIN(223, \"GPIO_223\"),\n> +\tPINCTRL_PIN(224, \"GPIO_224\"),\n> +\tPINCTRL_PIN(225, \"GPIO_225\"),\n> +\tPINCTRL_PIN(226, \"UFS_RESET\"),\n> +\tPINCTRL_PIN(227, \"SDC2_CLK\"),\n> +\tPINCTRL_PIN(228, \"SDC2_CMD\"),\n> +\tPINCTRL_PIN(229, \"SDC2_DATA\"),\n> +};\n> +\n> +#define DECLARE_MSM_GPIO_PINS(pin) \\\n> +\tstatic const unsigned int gpio##pin##_pins[] = { pin }\n> +DECLARE_MSM_GPIO_PINS(0);\n> +DECLARE_MSM_GPIO_PINS(1);\n> +DECLARE_MSM_GPIO_PINS(2);\n> +DECLARE_MSM_GPIO_PINS(3);\n> +DECLARE_MSM_GPIO_PINS(4);\n> +DECLARE_MSM_GPIO_PINS(5);\n> +DECLARE_MSM_GPIO_PINS(6);\n> +DECLARE_MSM_GPIO_PINS(7);\n> +DECLARE_MSM_GPIO_PINS(8);\n> +DECLARE_MSM_GPIO_PINS(9);\n> +DECLARE_MSM_GPIO_PINS(10);\n> +DECLARE_MSM_GPIO_PINS(11);\n> +DECLARE_MSM_GPIO_PINS(12);\n> +DECLARE_MSM_GPIO_PINS(13);\n> +DECLARE_MSM_GPIO_PINS(14);\n> +DECLARE_MSM_GPIO_PINS(15);\n> +DECLARE_MSM_GPIO_PINS(16);\n> +DECLARE_MSM_GPIO_PINS(17);\n> +DECLARE_MSM_GPIO_PINS(18);\n> +DECLARE_MSM_GPIO_PINS(19);\n> +DECLARE_MSM_GPIO_PINS(20);\n> +DECLARE_MSM_GPIO_PINS(21);\n> +DECLARE_MSM_GPIO_PINS(22);\n> +DECLARE_MSM_GPIO_PINS(23);\n> +DECLARE_MSM_GPIO_PINS(24);\n> +DECLARE_MSM_GPIO_PINS(25);\n> +DECLARE_MSM_GPIO_PINS(26);\n> +DECLARE_MSM_GPIO_PINS(27);\n> +DECLARE_MSM_GPIO_PINS(28);\n> +DECLARE_MSM_GPIO_PINS(29);\n> +DECLARE_MSM_GPIO_PINS(30);\n> +DECLARE_MSM_GPIO_PINS(31);\n> +DECLARE_MSM_GPIO_PINS(32);\n> +DECLARE_MSM_GPIO_PINS(33);\n> +DECLARE_MSM_GPIO_PINS(34);\n> +DECLARE_MSM_GPIO_PINS(35);\n> +DECLARE_MSM_GPIO_PINS(36);\n> +DECLARE_MSM_GPIO_PINS(37);\n> +DECLARE_MSM_GPIO_PINS(38);\n> +DECLARE_MSM_GPIO_PINS(39);\n> +DECLARE_MSM_GPIO_PINS(40);\n> +DECLARE_MSM_GPIO_PINS(41);\n> +DECLARE_MSM_GPIO_PINS(42);\n> +DECLARE_MSM_GPIO_PINS(43);\n> +DECLARE_MSM_GPIO_PINS(44);\n> +DECLARE_MSM_GPIO_PINS(45);\n> +DECLARE_MSM_GPIO_PINS(46);\n> +DECLARE_MSM_GPIO_PINS(47);\n> +DECLARE_MSM_GPIO_PINS(48);\n> +DECLARE_MSM_GPIO_PINS(49);\n> +DECLARE_MSM_GPIO_PINS(50);\n> +DECLARE_MSM_GPIO_PINS(51);\n> +DECLARE_MSM_GPIO_PINS(52);\n> +DECLARE_MSM_GPIO_PINS(53);\n> +DECLARE_MSM_GPIO_PINS(54);\n> +DECLARE_MSM_GPIO_PINS(55);\n> +DECLARE_MSM_GPIO_PINS(56);\n> +DECLARE_MSM_GPIO_PINS(57);\n> +DECLARE_MSM_GPIO_PINS(58);\n> +DECLARE_MSM_GPIO_PINS(59);\n> +DECLARE_MSM_GPIO_PINS(60);\n> +DECLARE_MSM_GPIO_PINS(61);\n> +DECLARE_MSM_GPIO_PINS(62);\n> +DECLARE_MSM_GPIO_PINS(63);\n> +DECLARE_MSM_GPIO_PINS(64);\n> +DECLARE_MSM_GPIO_PINS(65);\n> +DECLARE_MSM_GPIO_PINS(66);\n> +DECLARE_MSM_GPIO_PINS(67);\n> +DECLARE_MSM_GPIO_PINS(68);\n> +DECLARE_MSM_GPIO_PINS(69);\n> +DECLARE_MSM_GPIO_PINS(70);\n> +DECLARE_MSM_GPIO_PINS(71);\n> +DECLARE_MSM_GPIO_PINS(72);\n> +DECLARE_MSM_GPIO_PINS(73);\n> +DECLARE_MSM_GPIO_PINS(74);\n> +DECLARE_MSM_GPIO_PINS(75);\n> +DECLARE_MSM_GPIO_PINS(76);\n> +DECLARE_MSM_GPIO_PINS(77);\n> +DECLARE_MSM_GPIO_PINS(78);\n> +DECLARE_MSM_GPIO_PINS(79);\n> +DECLARE_MSM_GPIO_PINS(80);\n> +DECLARE_MSM_GPIO_PINS(81);\n> +DECLARE_MSM_GPIO_PINS(82);\n> +DECLARE_MSM_GPIO_PINS(83);\n> +DECLARE_MSM_GPIO_PINS(84);\n> +DECLARE_MSM_GPIO_PINS(85);\n> +DECLARE_MSM_GPIO_PINS(86);\n> +DECLARE_MSM_GPIO_PINS(87);\n> +DECLARE_MSM_GPIO_PINS(88);\n> +DECLARE_MSM_GPIO_PINS(89);\n> +DECLARE_MSM_GPIO_PINS(90);\n> +DECLARE_MSM_GPIO_PINS(91);\n> +DECLARE_MSM_GPIO_PINS(92);\n> +DECLARE_MSM_GPIO_PINS(93);\n> +DECLARE_MSM_GPIO_PINS(94);\n> +DECLARE_MSM_GPIO_PINS(95);\n> +DECLARE_MSM_GPIO_PINS(96);\n> +DECLARE_MSM_GPIO_PINS(97);\n> +DECLARE_MSM_GPIO_PINS(98);\n> +DECLARE_MSM_GPIO_PINS(99);\n> +DECLARE_MSM_GPIO_PINS(100);\n> +DECLARE_MSM_GPIO_PINS(101);\n> +DECLARE_MSM_GPIO_PINS(102);\n> +DECLARE_MSM_GPIO_PINS(103);\n> +DECLARE_MSM_GPIO_PINS(104);\n> +DECLARE_MSM_GPIO_PINS(105);\n> +DECLARE_MSM_GPIO_PINS(106);\n> +DECLARE_MSM_GPIO_PINS(107);\n> +DECLARE_MSM_GPIO_PINS(108);\n> +DECLARE_MSM_GPIO_PINS(109);\n> +DECLARE_MSM_GPIO_PINS(110);\n> +DECLARE_MSM_GPIO_PINS(111);\n> +DECLARE_MSM_GPIO_PINS(112);\n> +DECLARE_MSM_GPIO_PINS(113);\n> +DECLARE_MSM_GPIO_PINS(114);\n> +DECLARE_MSM_GPIO_PINS(115);\n> +DECLARE_MSM_GPIO_PINS(116);\n> +DECLARE_MSM_GPIO_PINS(117);\n> +DECLARE_MSM_GPIO_PINS(118);\n> +DECLARE_MSM_GPIO_PINS(119);\n> +DECLARE_MSM_GPIO_PINS(120);\n> +DECLARE_MSM_GPIO_PINS(121);\n> +DECLARE_MSM_GPIO_PINS(122);\n> +DECLARE_MSM_GPIO_PINS(123);\n> +DECLARE_MSM_GPIO_PINS(124);\n> +DECLARE_MSM_GPIO_PINS(125);\n> +DECLARE_MSM_GPIO_PINS(126);\n> +DECLARE_MSM_GPIO_PINS(127);\n> +DECLARE_MSM_GPIO_PINS(128);\n> +DECLARE_MSM_GPIO_PINS(129);\n> +DECLARE_MSM_GPIO_PINS(130);\n> +DECLARE_MSM_GPIO_PINS(131);\n> +DECLARE_MSM_GPIO_PINS(132);\n> +DECLARE_MSM_GPIO_PINS(133);\n> +DECLARE_MSM_GPIO_PINS(134);\n> +DECLARE_MSM_GPIO_PINS(135);\n> +DECLARE_MSM_GPIO_PINS(136);\n> +DECLARE_MSM_GPIO_PINS(137);\n> +DECLARE_MSM_GPIO_PINS(138);\n> +DECLARE_MSM_GPIO_PINS(139);\n> +DECLARE_MSM_GPIO_PINS(140);\n> +DECLARE_MSM_GPIO_PINS(141);\n> +DECLARE_MSM_GPIO_PINS(142);\n> +DECLARE_MSM_GPIO_PINS(143);\n> +DECLARE_MSM_GPIO_PINS(144);\n> +DECLARE_MSM_GPIO_PINS(145);\n> +DECLARE_MSM_GPIO_PINS(146);\n> +DECLARE_MSM_GPIO_PINS(147);\n> +DECLARE_MSM_GPIO_PINS(148);\n> +DECLARE_MSM_GPIO_PINS(149);\n> +DECLARE_MSM_GPIO_PINS(150);\n> +DECLARE_MSM_GPIO_PINS(151);\n> +DECLARE_MSM_GPIO_PINS(152);\n> +DECLARE_MSM_GPIO_PINS(153);\n> +DECLARE_MSM_GPIO_PINS(154);\n> +DECLARE_MSM_GPIO_PINS(155);\n> +DECLARE_MSM_GPIO_PINS(156);\n> +DECLARE_MSM_GPIO_PINS(157);\n> +DECLARE_MSM_GPIO_PINS(158);\n> +DECLARE_MSM_GPIO_PINS(159);\n> +DECLARE_MSM_GPIO_PINS(160);\n> +DECLARE_MSM_GPIO_PINS(161);\n> +DECLARE_MSM_GPIO_PINS(162);\n> +DECLARE_MSM_GPIO_PINS(163);\n> +DECLARE_MSM_GPIO_PINS(164);\n> +DECLARE_MSM_GPIO_PINS(165);\n> +DECLARE_MSM_GPIO_PINS(166);\n> +DECLARE_MSM_GPIO_PINS(167);\n> +DECLARE_MSM_GPIO_PINS(168);\n> +DECLARE_MSM_GPIO_PINS(169);\n> +DECLARE_MSM_GPIO_PINS(170);\n> +DECLARE_MSM_GPIO_PINS(171);\n> +DECLARE_MSM_GPIO_PINS(172);\n> +DECLARE_MSM_GPIO_PINS(173);\n> +DECLARE_MSM_GPIO_PINS(174);\n> +DECLARE_MSM_GPIO_PINS(175);\n> +DECLARE_MSM_GPIO_PINS(176);\n> +DECLARE_MSM_GPIO_PINS(177);\n> +DECLARE_MSM_GPIO_PINS(178);\n> +DECLARE_MSM_GPIO_PINS(179);\n> +DECLARE_MSM_GPIO_PINS(180);\n> +DECLARE_MSM_GPIO_PINS(181);\n> +DECLARE_MSM_GPIO_PINS(182);\n> +DECLARE_MSM_GPIO_PINS(183);\n> +DECLARE_MSM_GPIO_PINS(184);\n> +DECLARE_MSM_GPIO_PINS(185);\n> +DECLARE_MSM_GPIO_PINS(186);\n> +DECLARE_MSM_GPIO_PINS(187);\n> +DECLARE_MSM_GPIO_PINS(188);\n> +DECLARE_MSM_GPIO_PINS(189);\n> +DECLARE_MSM_GPIO_PINS(190);\n> +DECLARE_MSM_GPIO_PINS(191);\n> +DECLARE_MSM_GPIO_PINS(192);\n> +DECLARE_MSM_GPIO_PINS(193);\n> +DECLARE_MSM_GPIO_PINS(194);\n> +DECLARE_MSM_GPIO_PINS(195);\n> +DECLARE_MSM_GPIO_PINS(196);\n> +DECLARE_MSM_GPIO_PINS(197);\n> +DECLARE_MSM_GPIO_PINS(198);\n> +DECLARE_MSM_GPIO_PINS(199);\n> +DECLARE_MSM_GPIO_PINS(200);\n> +DECLARE_MSM_GPIO_PINS(201);\n> +DECLARE_MSM_GPIO_PINS(202);\n> +DECLARE_MSM_GPIO_PINS(203);\n> +DECLARE_MSM_GPIO_PINS(204);\n> +DECLARE_MSM_GPIO_PINS(205);\n> +DECLARE_MSM_GPIO_PINS(206);\n> +DECLARE_MSM_GPIO_PINS(207);\n> +DECLARE_MSM_GPIO_PINS(208);\n> +DECLARE_MSM_GPIO_PINS(209);\n> +DECLARE_MSM_GPIO_PINS(210);\n> +DECLARE_MSM_GPIO_PINS(211);\n> +DECLARE_MSM_GPIO_PINS(212);\n> +DECLARE_MSM_GPIO_PINS(213);\n> +DECLARE_MSM_GPIO_PINS(214);\n> +DECLARE_MSM_GPIO_PINS(215);\n> +DECLARE_MSM_GPIO_PINS(216);\n> +DECLARE_MSM_GPIO_PINS(217);\n> +DECLARE_MSM_GPIO_PINS(218);\n> +DECLARE_MSM_GPIO_PINS(219);\n> +DECLARE_MSM_GPIO_PINS(220);\n> +DECLARE_MSM_GPIO_PINS(221);\n> +DECLARE_MSM_GPIO_PINS(222);\n> +DECLARE_MSM_GPIO_PINS(223);\n> +DECLARE_MSM_GPIO_PINS(224);\n> +DECLARE_MSM_GPIO_PINS(225);\n> +\n> +static const unsigned int ufs_reset_pins[] = { 226 };\n> +static const unsigned int sdc2_clk_pins[] = { 227 };\n> +static const unsigned int sdc2_cmd_pins[] = { 228 };\n> +static const unsigned int sdc2_data_pins[] = { 229 };\n> +\n> +enum hawi_functions {\n> +\tmsm_mux_gpio,\n> +\tmsm_mux_aoss_cti,\n> +\tmsm_mux_atest_char,\n> +\tmsm_mux_atest_usb,\n> +\tmsm_mux_audio_ext_mclk,\n> +\tmsm_mux_audio_ref_clk,\n> +\tmsm_mux_cam_mclk,\n> +\tmsm_mux_cci_async_in,\n> +\tmsm_mux_cci_i2c0,\n> +\tmsm_mux_cci_i2c1,\n> +\tmsm_mux_cci_i2c2,\n> +\tmsm_mux_cci_i2c3,\n> +\tmsm_mux_cci_i2c4,\n> +\tmsm_mux_cci_i2c5,\n> +\tmsm_mux_cci_timer,\n> +\tmsm_mux_coex_espmi,\n> +\tmsm_mux_coex_uart1_rx,\n> +\tmsm_mux_coex_uart1_tx,\n> +\tmsm_mux_dbg_out_clk,\n> +\tmsm_mux_ddr_bist,\n> +\tmsm_mux_ddr_pxi,\n> +\tmsm_mux_dp_hot,\n> +\tmsm_mux_egpio,\n> +\tmsm_mux_gcc_gp,\n> +\tmsm_mux_gnss_adc,\n> +\tmsm_mux_host_rst,\n> +\tmsm_mux_i2chub0_se0,\n> +\tmsm_mux_i2chub0_se1,\n> +\tmsm_mux_i2chub0_se2,\n> +\tmsm_mux_i2chub0_se3,\n> +\tmsm_mux_i2chub0_se4,\n> +\tmsm_mux_i2s0,\n> +\tmsm_mux_i2s1,\n> +\tmsm_mux_ibi_i3c,\n> +\tmsm_mux_jitter_bist,\n> +\tmsm_mux_mdp_esync0,\n> +\tmsm_mux_mdp_esync1,\n> +\tmsm_mux_mdp_esync2,\n> +\tmsm_mux_mdp_vsync,\n> +\tmsm_mux_mdp_vsync_e,\n> +\tmsm_mux_mdp_vsync_p,\n> +\tmsm_mux_mdp_vsync0_out,\n> +\tmsm_mux_mdp_vsync1_out,\n> +\tmsm_mux_mdp_vsync2_out,\n> +\tmsm_mux_mdp_vsync3_out,\n> +\tmsm_mux_mdp_vsync5_out,\n> +\tmsm_mux_modem_pps_in,\n> +\tmsm_mux_modem_pps_out,\n> +\tmsm_mux_nav_gpio,\n> +\tmsm_mux_nav_gpio0,\n> +\tmsm_mux_nav_gpio3,\n> +\tmsm_mux_nav_rffe,\n> +\tmsm_mux_pcie0_clk_req_n,\n> +\tmsm_mux_pcie0_rst_n,\n> +\tmsm_mux_pcie1_clk_req_n,\n> +\tmsm_mux_phase_flag,\n> +\tmsm_mux_pll_bist_sync,\n> +\tmsm_mux_pll_clk_aux,\n> +\tmsm_mux_qdss_cti,\n> +\tmsm_mux_qlink,\n> +\tmsm_mux_qspi,\n> +\tmsm_mux_qspi_clk,\n> +\tmsm_mux_qspi_cs,\n> +\tmsm_mux_qup1_se0,\n> +\tmsm_mux_qup1_se1,\n> +\tmsm_mux_qup1_se2,\n> +\tmsm_mux_qup1_se3,\n> +\tmsm_mux_qup1_se4,\n> +\tmsm_mux_qup1_se5,\n> +\tmsm_mux_qup1_se6,\n> +\tmsm_mux_qup1_se7,\n> +\tmsm_mux_qup2_se0,\n> +\tmsm_mux_qup2_se1,\n> +\tmsm_mux_qup2_se2,\n> +\tmsm_mux_qup2_se3,\n> +\tmsm_mux_qup2_se4_01,\n> +\tmsm_mux_qup2_se4_23,\n> +\tmsm_mux_qup3_se0_01,\n> +\tmsm_mux_qup3_se0_23,\n> +\tmsm_mux_qup3_se1,\n> +\tmsm_mux_qup3_se2,\n> +\tmsm_mux_qup3_se3,\n> +\tmsm_mux_qup3_se4,\n> +\tmsm_mux_qup3_se5,\n> +\tmsm_mux_qup4_se0,\n> +\tmsm_mux_qup4_se1,\n> +\tmsm_mux_qup4_se2,\n> +\tmsm_mux_qup4_se3_01,\n> +\tmsm_mux_qup4_se3_23,\n> +\tmsm_mux_qup4_se3_l3,\n> +\tmsm_mux_qup4_se4_01,\n> +\tmsm_mux_qup4_se4_23,\n> +\tmsm_mux_qup4_se4_l3,\n> +\tmsm_mux_rng_rosc,\n> +\tmsm_mux_sd_write_protect,\n> +\tmsm_mux_sdc4_clk,\n> +\tmsm_mux_sdc4_cmd,\n> +\tmsm_mux_sdc4_data,\n> +\tmsm_mux_sys_throttle,\n> +\tmsm_mux_tb_trig_sdc,\n> +\tmsm_mux_tmess_rng,\n> +\tmsm_mux_tsense_clm,\n> +\tmsm_mux_tsense_pwm,\n> +\tmsm_mux_uim0,\n> +\tmsm_mux_uim1,\n> +\tmsm_mux_usb0_hs,\n> +\tmsm_mux_usb_phy,\n> +\tmsm_mux_vfr,\n> +\tmsm_mux_vsense_trigger_mirnat,\n> +\tmsm_mux_wcn_sw_ctrl,\n> +\tmsm_mux__,\n> +};\n> +\n> +static const char *const gpio_groups[] = {\n> +\t\"gpio0\", \"gpio1\", \"gpio2\", \"gpio3\", \"gpio4\", \"gpio5\",\n> +\t\"gpio6\", \"gpio7\", \"gpio8\", \"gpio9\", \"gpio10\", \"gpio11\",\n> +\t\"gpio12\", \"gpio13\", \"gpio14\", \"gpio15\", \"gpio16\", \"gpio17\",\n> +\t\"gpio18\", \"gpio19\", \"gpio20\", \"gpio21\", \"gpio22\", \"gpio23\",\n> +\t\"gpio24\", \"gpio25\", \"gpio26\", \"gpio27\", \"gpio28\", \"gpio29\",\n> +\t\"gpio30\", \"gpio31\", \"gpio32\", \"gpio33\", \"gpio34\", \"gpio35\",\n> +\t\"gpio36\", \"gpio37\", \"gpio38\", \"gpio39\", \"gpio40\", \"gpio41\",\n> +\t\"gpio42\", \"gpio43\", \"gpio44\", \"gpio45\", \"gpio46\", \"gpio47\",\n> +\t\"gpio48\", \"gpio49\", \"gpio50\", \"gpio51\", \"gpio52\", \"gpio53\",\n> +\t\"gpio54\", \"gpio55\", \"gpio56\", \"gpio57\", \"gpio58\", \"gpio59\",\n> +\t\"gpio60\", \"gpio61\", \"gpio62\", \"gpio63\", \"gpio64\", \"gpio65\",\n> +\t\"gpio66\", \"gpio67\", \"gpio68\", \"gpio69\", \"gpio70\", \"gpio71\",\n> +\t\"gpio72\", \"gpio73\", \"gpio74\", \"gpio75\", \"gpio76\", \"gpio77\",\n> +\t\"gpio78\", \"gpio79\", \"gpio80\", \"gpio81\", \"gpio82\", \"gpio83\",\n> +\t\"gpio84\", \"gpio85\", \"gpio86\", \"gpio87\", \"gpio88\", \"gpio89\",\n> +\t\"gpio90\", \"gpio91\", \"gpio92\", \"gpio93\", \"gpio94\", \"gpio95\",\n> +\t\"gpio96\", \"gpio97\", \"gpio98\", \"gpio99\", \"gpio100\", \"gpio101\",\n> +\t\"gpio102\", \"gpio103\", \"gpio104\", \"gpio105\", \"gpio106\", \"gpio107\",\n> +\t\"gpio108\", \"gpio109\", \"gpio110\", \"gpio111\", \"gpio112\", \"gpio113\",\n> +\t\"gpio114\", \"gpio115\", \"gpio116\", \"gpio117\", \"gpio118\", \"gpio119\",\n> +\t\"gpio120\", \"gpio121\", \"gpio122\", \"gpio123\", \"gpio124\", \"gpio125\",\n> +\t\"gpio126\", \"gpio127\", \"gpio128\", \"gpio129\", \"gpio130\", \"gpio131\",\n> +\t\"gpio132\", \"gpio133\", \"gpio134\", \"gpio135\", \"gpio136\", \"gpio137\",\n> +\t\"gpio138\", \"gpio139\", \"gpio140\", \"gpio141\", \"gpio142\", \"gpio143\",\n> +\t\"gpio144\", \"gpio145\", \"gpio146\", \"gpio147\", \"gpio148\", \"gpio149\",\n> +\t\"gpio150\", \"gpio151\", \"gpio152\", \"gpio153\", \"gpio154\", \"gpio155\",\n> +\t\"gpio156\", \"gpio157\", \"gpio158\", \"gpio159\", \"gpio160\", \"gpio161\",\n> +\t\"gpio162\", \"gpio163\", \"gpio164\", \"gpio165\", \"gpio166\", \"gpio167\",\n> +\t\"gpio168\", \"gpio169\", \"gpio170\", \"gpio171\", \"gpio172\", \"gpio173\",\n> +\t\"gpio174\", \"gpio175\", \"gpio176\", \"gpio177\", \"gpio178\", \"gpio179\",\n> +\t\"gpio180\", \"gpio181\", \"gpio182\", \"gpio183\", \"gpio184\", \"gpio185\",\n> +\t\"gpio186\", \"gpio187\", \"gpio188\", \"gpio189\", \"gpio190\", \"gpio191\",\n> +\t\"gpio192\", \"gpio193\", \"gpio194\", \"gpio195\", \"gpio196\", \"gpio197\",\n> +\t\"gpio198\", \"gpio199\", \"gpio200\", \"gpio201\", \"gpio202\", \"gpio203\",\n> +\t\"gpio204\", \"gpio205\", \"gpio206\", \"gpio207\", \"gpio208\", \"gpio209\",\n> +\t\"gpio210\", \"gpio211\", \"gpio212\", \"gpio213\", \"gpio214\", \"gpio215\",\n> +\t\"gpio216\", \"gpio217\", \"gpio218\", \"gpio219\", \"gpio220\", \"gpio221\",\n> +\t\"gpio222\", \"gpio223\", \"gpio224\", \"gpio225\",\n> +};\n> +\n> +static const char *const aoss_cti_groups[] = {\n> +\t\"gpio74\", \"gpio75\", \"gpio76\", \"gpio77\",\n> +};\n> +\n> +static const char *const atest_char_groups[] = {\n> +\t\"gpio126\", \"gpio127\", \"gpio128\", \"gpio129\", \"gpio133\",\n> +};\n> +\n> +static const char *const atest_usb_groups[] = {\n> +\t\"gpio70\", \"gpio71\", \"gpio72\", \"gpio73\", \"gpio129\",\n> +};\n> +\n> +static const char *const audio_ext_mclk_groups[] = {\n> +\t\"gpio120\", \"gpio121\",\n> +};\n> +\n> +static const char *const audio_ref_clk_groups[] = {\n> +\t\"gpio120\",\n> +};\n> +\n> +static const char *const cam_mclk_groups[] = {\n> +\t\"gpio89\", \"gpio90\", \"gpio91\", \"gpio92\", \"gpio93\", \"gpio94\",\n> +\t\"gpio95\", \"gpio96\",\n> +};\n> +\n> +static const char *const cci_async_in_groups[] = {\n> +\t\"gpio15\", \"gpio109\", \"gpio110\",\n> +};\n> +\n> +static const char *const cci_i2c0_groups[] = {\n> +\t\"gpio109\", \"gpio110\",\n> +};\n> +\n> +static const char *const cci_i2c1_groups[] = {\n> +\t\"gpio111\", \"gpio112\",\n> +};\n> +\n> +static const char *const cci_i2c2_groups[] = {\n> +\t\"gpio113\", \"gpio114\",\n> +};\n> +\n> +static const char *const cci_i2c3_groups[] = {\n> +\t\"gpio107\", \"gpio160\",\n> +};\n> +\n> +static const char *const cci_i2c4_groups[] = {\n> +\t\"gpio108\", \"gpio149\",\n> +};\n> +\n> +static const char *const cci_i2c5_groups[] = {\n> +\t\"gpio115\", \"gpio116\",\n> +};\n> +\n> +static const char *const cci_timer_groups[] = {\n> +\t\"gpio105\", \"gpio106\", \"gpio107\", \"gpio159\", \"gpio160\",\n> +};\n> +\n> +static const char *const coex_espmi_groups[] = {\n> +\t\"gpio144\", \"gpio145\",\n> +};\n> +\n> +static const char *const coex_uart1_rx_groups[] = {\n> +\t\"gpio144\",\n> +};\n> +\n> +static const char *const coex_uart1_tx_groups[] = {\n> +\t\"gpio145\",\n> +};\n> +\n> +static const char *const dbg_out_clk_groups[] = {\n> +\t\"gpio82\",\n> +};\n> +\n> +static const char *const ddr_bist_groups[] = {\n> +\t\"gpio40\", \"gpio41\", \"gpio44\", \"gpio45\",\n> +};\n> +\n> +static const char *const ddr_pxi_groups[] = {\n> +\t\"gpio43\", \"gpio44\", \"gpio45\", \"gpio46\",\n> +\t\"gpio52\", \"gpio53\", \"gpio54\", \"gpio55\",\n> +};\n> +\n> +static const char *const dp_hot_groups[] = {\n> +\t\"gpio47\",\n> +};\n> +\n> +static const char *const egpio_groups[] = {\n> +\t\"gpio0\", \"gpio1\", \"gpio2\", \"gpio3\", \"gpio4\", \"gpio5\",\n> +\t\"gpio6\", \"gpio7\", \"gpio28\", \"gpio29\", \"gpio30\", \"gpio31\",\n> +\t\"gpio48\", \"gpio49\", \"gpio50\", \"gpio51\", \"gpio163\", \"gpio164\",\n> +\t\"gpio165\", \"gpio166\", \"gpio167\", \"gpio168\", \"gpio169\", \"gpio170\",\n> +\t\"gpio171\", \"gpio172\", \"gpio173\", \"gpio174\", \"gpio175\", \"gpio176\",\n> +\t\"gpio177\", \"gpio178\", \"gpio179\", \"gpio180\", \"gpio181\", \"gpio182\",\n> +\t\"gpio183\", \"gpio184\", \"gpio185\", \"gpio186\", \"gpio187\", \"gpio188\",\n> +\t\"gpio189\", \"gpio190\", \"gpio191\", \"gpio192\", \"gpio193\", \"gpio194\",\n> +\t\"gpio195\", \"gpio196\", \"gpio197\", \"gpio198\", \"gpio199\", \"gpio200\",\n> +\t\"gpio201\", \"gpio202\", \"gpio203\", \"gpio204\", \"gpio205\", \"gpio206\",\n> +\t\"gpio207\", \"gpio208\", \"gpio209\", \"gpio212\", \"gpio213\", \"gpio214\",\n> +\t\"gpio215\", \"gpio216\", \"gpio217\", \"gpio218\",\n> +};\n> +\n> +static const char *const gcc_gp_groups[] = {\n> +\t\"gpio86\", \"gpio87\", \"gpio130\", \"gpio131\", \"gpio132\", \"gpio158\",\n> +};\n> +\n> +static const char *const gnss_adc_groups[] = {\n> +\t\"gpio40\", \"gpio41\", \"gpio42\", \"gpio77\",\n> +};\n> +\n> +static const char *const host_rst_groups[] = {\n> +\t\"gpio106\",\n> +};\n> +\n> +static const char *const i2chub0_se0_groups[] = {\n> +\t\"gpio66\", \"gpio67\",\n> +};\n> +\n> +static const char *const i2chub0_se1_groups[] = {\n> +\t\"gpio78\", \"gpio79\",\n> +};\n> +\n> +static const char *const i2chub0_se2_groups[] = {\n> +\t\"gpio68\", \"gpio69\",\n> +};\n> +\n> +static const char *const i2chub0_se3_groups[] = {\n> +\t\"gpio70\", \"gpio71\",\n> +};\n> +\n> +static const char *const i2chub0_se4_groups[] = {\n> +\t\"gpio72\", \"gpio73\",\n> +};\n> +\n> +static const char *const i2s0_groups[] = {\n> +\t\"gpio122\", \"gpio123\", \"gpio124\", \"gpio125\",\n> +};\n> +\n> +static const char *const i2s1_groups[] = {\n> +\t\"gpio117\", \"gpio118\", \"gpio119\", \"gpio120\",\n> +};\n> +\n> +static const char *const ibi_i3c_groups[] = {\n> +\t\"gpio0\", \"gpio1\", \"gpio4\", \"gpio5\", \"gpio8\", \"gpio9\",\n> +\t\"gpio12\", \"gpio13\", \"gpio28\", \"gpio29\", \"gpio32\", \"gpio33\",\n> +\t\"gpio36\", \"gpio37\", \"gpio48\", \"gpio49\", \"gpio60\", \"gpio61\",\n> +};\n> +\n> +static const char *const jitter_bist_groups[] = {\n> +\t\"gpio73\",\n> +};\n> +\n> +static const char *const mdp_esync0_groups[] = {\n> +\t\"gpio88\", \"gpio100\",\n> +};\n> +\n> +static const char *const mdp_esync1_groups[] = {\n> +\t\"gpio86\", \"gpio100\",\n> +};\n> +\n> +static const char *const mdp_esync2_groups[] = {\n> +\t\"gpio87\", \"gpio97\",\n> +};\n> +\n> +static const char *const mdp_vsync_groups[] = {\n> +\t\"gpio86\", \"gpio87\", \"gpio88\", \"gpio97\",\n> +};\n> +\n> +static const char *const mdp_vsync_e_groups[] = {\n> +\t\"gpio98\",\n> +};\n> +\n> +static const char *const mdp_vsync_p_groups[] = {\n> +\t\"gpio98\",\n> +};\n> +\n> +static const char *const mdp_vsync0_out_groups[] = {\n> +\t\"gpio86\",\n> +};\n> +\n> +static const char *const mdp_vsync1_out_groups[] = {\n> +\t\"gpio86\",\n> +};\n> +\n> +static const char *const mdp_vsync2_out_groups[] = {\n> +\t\"gpio87\",\n> +};\n> +\n> +static const char *const mdp_vsync3_out_groups[] = {\n> +\t\"gpio87\",\n> +};\n> +\n> +static const char *const mdp_vsync5_out_groups[] = {\n> +\t\"gpio87\",\n> +};\n> +\n> +static const char *const modem_pps_in_groups[] = {\n> +\t\"gpio151\",\n> +};\n> +\n> +static const char *const modem_pps_out_groups[] = {\n> +\t\"gpio151\",\n> +};\n> +\n> +static const char *const nav_gpio_groups[] = {\n> +\t\"gpio146\", \"gpio147\", \"gpio148\", \"gpio151\",\n> +};\n> +\n> +static const char *const nav_gpio0_groups[] = {\n> +\t\"gpio150\",\n> +};\n> +\n> +static const char *const nav_gpio3_groups[] = {\n> +\t\"gpio150\",\n> +};\n> +\n> +static const char *const nav_rffe_groups[] = {\n> +\t\"gpio134\", \"gpio135\", \"gpio138\", \"gpio139\",\n> +};\n> +\n> +static const char *const pcie0_clk_req_n_groups[] = {\n> +\t\"gpio103\",\n> +};\n> +\n> +static const char *const pcie0_rst_n_groups[] = {\n> +\t\"gpio102\",\n> +};\n> +\n> +static const char *const pcie1_clk_req_n_groups[] = {\n> +\t\"gpio221\",\n> +};\n> +\n> +static const char *const phase_flag_groups[] = {\n> +\t\"gpio117\", \"gpio118\", \"gpio119\", \"gpio123\", \"gpio124\", \"gpio125\",\n> +\t\"gpio169\", \"gpio170\", \"gpio171\", \"gpio172\", \"gpio173\", \"gpio175\",\n> +\t\"gpio176\", \"gpio179\", \"gpio180\", \"gpio181\", \"gpio184\", \"gpio185\",\n> +\t\"gpio192\", \"gpio196\", \"gpio197\", \"gpio198\", \"gpio199\", \"gpio204\",\n> +\t\"gpio206\", \"gpio207\", \"gpio208\", \"gpio210\", \"gpio211\", \"gpio214\",\n> +\t\"gpio215\", \"gpio216\",\n> +};\n> +\n> +static const char *const pll_bist_sync_groups[] = {\n> +\t\"gpio104\",\n> +};\n> +\n> +static const char *const pll_clk_aux_groups[] = {\n> +\t\"gpio94\",\n> +};\n> +\n> +static const char *const qdss_cti_groups[] = {\n> +\t\"gpio27\", \"gpio31\", \"gpio72\", \"gpio73\", \"gpio82\", \"gpio83\",\n> +\t\"gpio152\", \"gpio158\",\n> +};\n> +\n> +static const char *const qlink_groups[] = {\n> +\t\"gpio152\", \"gpio153\", \"gpio154\",\n> +};\n> +\n> +static const char *const qspi_groups[] = {\n> +\t\"gpio80\", \"gpio81\", \"gpio82\", \"gpio147\",\n> +};\n> +\n> +static const char *const qspi_clk_groups[] = {\n> +\t\"gpio83\",\n> +};\n> +\n> +static const char *const qspi_cs_groups[] = {\n> +\t\"gpio146\", \"gpio148\",\n> +};\n> +\n> +static const char *const qup1_se0_groups[] = {\n> +\t\"gpio80\", \"gpio81\", \"gpio82\", \"gpio83\",\n> +};\n> +\n> +static const char *const qup1_se1_groups[] = {\n> +\t\"gpio74\", \"gpio75\", \"gpio76\", \"gpio77\",\n> +};\n> +\n> +static const char *const qup1_se2_groups[] = {\n> +\t\"gpio40\", \"gpio41\", \"gpio42\", \"gpio43\", \"gpio130\", \"gpio131\", \"gpio132\",\n> +};\n> +\n> +static const char *const qup1_se3_groups[] = {\n> +\t\"gpio44\", \"gpio45\", \"gpio46\", \"gpio47\",\n> +};\n> +\n> +static const char *const qup1_se4_groups[] = {\n> +\t\"gpio36\", \"gpio37\", \"gpio38\", \"gpio39\",\n> +};\n> +\n> +static const char *const qup1_se5_groups[] = {\n> +\t\"gpio52\", \"gpio53\", \"gpio54\", \"gpio55\",\n> +};\n> +\n> +static const char *const qup1_se6_groups[] = {\n> +\t\"gpio56\", \"gpio57\", \"gpio58\", \"gpio59\",\n> +};\n> +\n> +static const char *const qup1_se7_groups[] = {\n> +\t\"gpio60\", \"gpio61\", \"gpio62\", \"gpio63\",\n> +};\n> +\n> +static const char *const qup2_se0_groups[] = {\n> +\t\"gpio0\", \"gpio1\", \"gpio2\", \"gpio3\",\n> +};\n> +\n> +static const char *const qup2_se1_groups[] = {\n> +\t\"gpio4\", \"gpio5\", \"gpio6\", \"gpio7\",\n> +};\n> +\n> +static const char *const qup2_se2_groups[] = {\n> +\t\"gpio117\", \"gpio118\", \"gpio119\", \"gpio120\",\n> +};\n> +\n> +static const char *const qup2_se3_groups[] = {\n> +\t\"gpio97\", \"gpio122\", \"gpio123\", \"gpio124\", \"gpio125\",\n> +};\n> +\n> +static const char *const qup2_se4_01_groups[] = {\n> +\t\"gpio208\", \"gpio209\",\n> +};\n> +\n> +static const char *const qup2_se4_23_groups[] = {\n> +\t\"gpio208\", \"gpio209\",\n> +};\n> +\n> +static const char *const qup3_se0_01_groups[] = {\n> +\t\"gpio64\", \"gpio65\",\n> +};\n> +\n> +static const char *const qup3_se0_23_groups[] = {\n> +\t\"gpio64\", \"gpio65\",\n> +};\n> +\n> +static const char *const qup3_se1_groups[] = {\n> +\t\"gpio8\", \"gpio9\", \"gpio10\", \"gpio11\", \"gpio12\", \"gpio13\", \"gpio15\",\n> +};\n> +\n> +static const char *const qup3_se2_groups[] = {\n> +\t\"gpio12\", \"gpio13\", \"gpio14\", \"gpio15\",\n> +};\n> +\n> +static const char *const qup3_se3_groups[] = {\n> +\t\"gpio16\", \"gpio17\", \"gpio18\", \"gpio19\",\n> +};\n> +\n> +static const char *const qup3_se4_groups[] = {\n> +\t\"gpio20\", \"gpio21\", \"gpio22\", \"gpio23\",\n> +};\n> +\n> +static const char *const qup3_se5_groups[] = {\n> +\t\"gpio24\", \"gpio25\", \"gpio26\", \"gpio27\",\n> +};\n> +\n> +static const char *const qup4_se0_groups[] = {\n> +\t\"gpio48\", \"gpio49\", \"gpio50\", \"gpio51\",\n> +};\n> +\n> +static const char *const qup4_se1_groups[] = {\n> +\t\"gpio28\", \"gpio29\", \"gpio30\", \"gpio31\",\n> +};\n> +\n> +static const char *const qup4_se2_groups[] = {\n> +\t\"gpio32\", \"gpio33\", \"gpio34\", \"gpio35\",\n> +};\n> +\n> +static const char *const qup4_se3_01_groups[] = {\n> +\t\"gpio84\", \"gpio121\",\n> +};\n> +\n> +static const char *const qup4_se3_23_groups[] = {\n> +\t\"gpio84\", \"gpio121\",\n> +};\n> +\n> +static const char *const qup4_se3_l3_groups[] = {\n> +\t\"gpio98\",\n> +};\n> +\n> +static const char *const qup4_se4_01_groups[] = {\n> +\t\"gpio161\", \"gpio162\",\n> +};\n> +\n> +static const char *const qup4_se4_23_groups[] = {\n> +\t\"gpio161\", \"gpio162\",\n> +};\n> +\n> +static const char *const qup4_se4_l3_groups[] = {\n> +\t\"gpio88\",\n> +};\n> +\n> +static const char *const rng_rosc_groups[] = {\n> +\t\"gpio64\", \"gpio65\", \"gpio66\", \"gpio84\",\n> +};\n> +\n> +static const char *const sd_write_protect_groups[] = {\n> +\t\"gpio85\",\n> +};\n> +\n> +static const char *const sdc4_clk_groups[] = {\n> +\t\"gpio83\",\n> +};\n> +\n> +static const char *const sdc4_cmd_groups[] = {\n> +\t\"gpio148\",\n> +};\n> +\n> +static const char *const sdc4_data_groups[] = {\n> +\t\"gpio80\", \"gpio81\", \"gpio82\", \"gpio147\",\n> +};\n> +\n> +static const char *const sys_throttle_groups[] = {\n> +\t\"gpio99\",\n> +};\n> +\n> +static const char *const tb_trig_sdc_groups[] = {\n> +\t\"gpio88\", \"gpio146\",\n> +};\n> +\n> +static const char *const tmess_rng_groups[] = {\n> +\t\"gpio64\", \"gpio65\", \"gpio66\", \"gpio84\",\n> +};\n> +\n> +static const char *const tsense_clm_groups[] = {\n> +\t\"gpio10\", \"gpio87\", \"gpio97\", \"gpio99\", \"gpio105\", \"gpio106\",\n> +\t\"gpio159\",\n> +};\n> +\n> +static const char *const tsense_pwm_groups[] = {\n> +\t\"gpio10\", \"gpio87\", \"gpio97\", \"gpio99\", \"gpio223\", \"gpio224\",\n> +\t\"gpio225\",\n> +};\n> +\n> +static const char *const uim0_groups[] = {\n> +\t\"gpio126\", \"gpio127\", \"gpio128\", \"gpio129\",\n> +};\n> +\n> +static const char *const uim1_groups[] = {\n> +\t\"gpio36\", \"gpio37\", \"gpio39\", \"gpio54\", \"gpio55\", \"gpio56\",\n> +\t\"gpio70\", \"gpio71\", \"gpio72\", \"gpio130\", \"gpio131\", \"gpio132\",\n> +\t\"gpio133\",\n> +};\n> +\n> +static const char *const usb0_hs_groups[] = {\n> +\t\"gpio79\",\n> +};\n> +\n> +static const char *const usb_phy_groups[] = {\n> +\t\"gpio59\", \"gpio60\",\n> +};\n> +\n> +static const char *const vfr_groups[] = {\n> +\t\"gpio146\", \"gpio151\",\n> +};\n> +\n> +static const char *const vsense_trigger_mirnat_groups[] = {\n> +\t\"gpio59\",\n> +};\n> +\n> +static const char *const wcn_sw_ctrl_groups[] = {\n> +\t\"gpio18\", \"gpio19\", \"gpio155\", \"gpio156\",\n> +};\n> +\n> +static const struct pinfunction hawi_functions[] = {\n> +\tMSM_GPIO_PIN_FUNCTION(gpio),\n> +\tMSM_PIN_FUNCTION(aoss_cti),\n> +\tMSM_PIN_FUNCTION(atest_char),\n> +\tMSM_PIN_FUNCTION(atest_usb),\n> +\tMSM_PIN_FUNCTION(audio_ext_mclk),\n> +\tMSM_PIN_FUNCTION(audio_ref_clk),\n> +\tMSM_PIN_FUNCTION(cam_mclk),\n> +\tMSM_PIN_FUNCTION(cci_async_in),\n> +\tMSM_PIN_FUNCTION(cci_i2c0),\n> +\tMSM_PIN_FUNCTION(cci_i2c1),\n> +\tMSM_PIN_FUNCTION(cci_i2c2),\n> +\tMSM_PIN_FUNCTION(cci_i2c3),\n> +\tMSM_PIN_FUNCTION(cci_i2c4),\n> +\tMSM_PIN_FUNCTION(cci_i2c5),\n> +\tMSM_PIN_FUNCTION(cci_timer),\n> +\tMSM_PIN_FUNCTION(coex_espmi),\n> +\tMSM_PIN_FUNCTION(coex_uart1_rx),\n> +\tMSM_PIN_FUNCTION(coex_uart1_tx),\n> +\tMSM_PIN_FUNCTION(dbg_out_clk),\n> +\tMSM_PIN_FUNCTION(ddr_bist),\n> +\tMSM_PIN_FUNCTION(ddr_pxi),\n> +\tMSM_PIN_FUNCTION(dp_hot),\n> +\tMSM_PIN_FUNCTION(egpio),\n> +\tMSM_PIN_FUNCTION(gcc_gp),\n> +\tMSM_PIN_FUNCTION(gnss_adc),\n> +\tMSM_PIN_FUNCTION(host_rst),\n> +\tMSM_PIN_FUNCTION(i2chub0_se0),\n> +\tMSM_PIN_FUNCTION(i2chub0_se1),\n> +\tMSM_PIN_FUNCTION(i2chub0_se2),\n> +\tMSM_PIN_FUNCTION(i2chub0_se3),\n> +\tMSM_PIN_FUNCTION(i2chub0_se4),\n> +\tMSM_PIN_FUNCTION(i2s0),\n> +\tMSM_PIN_FUNCTION(i2s1),\n> +\tMSM_PIN_FUNCTION(ibi_i3c),\n> +\tMSM_PIN_FUNCTION(jitter_bist),\n> +\tMSM_PIN_FUNCTION(mdp_esync0),\n> +\tMSM_PIN_FUNCTION(mdp_esync1),\n> +\tMSM_PIN_FUNCTION(mdp_esync2),\n> +\tMSM_PIN_FUNCTION(mdp_vsync),\n> +\tMSM_PIN_FUNCTION(mdp_vsync_e),\n> +\tMSM_PIN_FUNCTION(mdp_vsync_p),\n> +\tMSM_PIN_FUNCTION(mdp_vsync0_out),\n> +\tMSM_PIN_FUNCTION(mdp_vsync1_out),\n> +\tMSM_PIN_FUNCTION(mdp_vsync2_out),\n> +\tMSM_PIN_FUNCTION(mdp_vsync3_out),\n> +\tMSM_PIN_FUNCTION(mdp_vsync5_out),\n> +\tMSM_PIN_FUNCTION(modem_pps_in),\n> +\tMSM_PIN_FUNCTION(modem_pps_out),\n> +\tMSM_PIN_FUNCTION(nav_gpio),\n> +\tMSM_PIN_FUNCTION(nav_gpio0),\n> +\tMSM_PIN_FUNCTION(nav_gpio3),\n> +\tMSM_PIN_FUNCTION(nav_rffe),\n> +\tMSM_PIN_FUNCTION(pcie0_clk_req_n),\n> +\tMSM_PIN_FUNCTION(pcie0_rst_n),\n> +\tMSM_PIN_FUNCTION(pcie1_clk_req_n),\n> +\tMSM_PIN_FUNCTION(phase_flag),\n> +\tMSM_PIN_FUNCTION(pll_bist_sync),\n> +\tMSM_PIN_FUNCTION(pll_clk_aux),\n> +\tMSM_PIN_FUNCTION(qdss_cti),\n> +\tMSM_PIN_FUNCTION(qlink),\n> +\tMSM_PIN_FUNCTION(qspi),\n> +\tMSM_PIN_FUNCTION(qspi_clk),\n> +\tMSM_PIN_FUNCTION(qspi_cs),\n> +\tMSM_PIN_FUNCTION(qup1_se0),\n> +\tMSM_PIN_FUNCTION(qup1_se1),\n> +\tMSM_PIN_FUNCTION(qup1_se2),\n> +\tMSM_PIN_FUNCTION(qup1_se3),\n> +\tMSM_PIN_FUNCTION(qup1_se4),\n> +\tMSM_PIN_FUNCTION(qup1_se5),\n> +\tMSM_PIN_FUNCTION(qup1_se6),\n> +\tMSM_PIN_FUNCTION(qup1_se7),\n> +\tMSM_PIN_FUNCTION(qup2_se0),\n> +\tMSM_PIN_FUNCTION(qup2_se1),\n> +\tMSM_PIN_FUNCTION(qup2_se2),\n> +\tMSM_PIN_FUNCTION(qup2_se3),\n> +\tMSM_PIN_FUNCTION(qup2_se4_01),\n> +\tMSM_PIN_FUNCTION(qup2_se4_23),\n> +\tMSM_PIN_FUNCTION(qup3_se0_01),\n> +\tMSM_PIN_FUNCTION(qup3_se0_23),\n> +\tMSM_PIN_FUNCTION(qup3_se1),\n> +\tMSM_PIN_FUNCTION(qup3_se2),\n> +\tMSM_PIN_FUNCTION(qup3_se3),\n> +\tMSM_PIN_FUNCTION(qup3_se4),\n> +\tMSM_PIN_FUNCTION(qup3_se5),\n> +\tMSM_PIN_FUNCTION(qup4_se0),\n> +\tMSM_PIN_FUNCTION(qup4_se1),\n> +\tMSM_PIN_FUNCTION(qup4_se2),\n> +\tMSM_PIN_FUNCTION(qup4_se3_01),\n> +\tMSM_PIN_FUNCTION(qup4_se3_23),\n> +\tMSM_PIN_FUNCTION(qup4_se3_l3),\n> +\tMSM_PIN_FUNCTION(qup4_se4_01),\n> +\tMSM_PIN_FUNCTION(qup4_se4_23),\n> +\tMSM_PIN_FUNCTION(qup4_se4_l3),\n> +\tMSM_PIN_FUNCTION(rng_rosc),\n> +\tMSM_PIN_FUNCTION(sd_write_protect),\n> +\tMSM_PIN_FUNCTION(sdc4_clk),\n> +\tMSM_PIN_FUNCTION(sdc4_cmd),\n> +\tMSM_PIN_FUNCTION(sdc4_data),\n> +\tMSM_PIN_FUNCTION(sys_throttle),\n> +\tMSM_PIN_FUNCTION(tb_trig_sdc),\n> +\tMSM_PIN_FUNCTION(tmess_rng),\n> +\tMSM_PIN_FUNCTION(tsense_clm),\n> +\tMSM_PIN_FUNCTION(tsense_pwm),\n> +\tMSM_PIN_FUNCTION(uim0),\n> +\tMSM_PIN_FUNCTION(uim1),\n> +\tMSM_PIN_FUNCTION(usb0_hs),\n> +\tMSM_PIN_FUNCTION(usb_phy),\n> +\tMSM_PIN_FUNCTION(vfr),\n> +\tMSM_PIN_FUNCTION(vsense_trigger_mirnat),\n> +\tMSM_PIN_FUNCTION(wcn_sw_ctrl),\n> +};\n> +\n> +/*\n> + * Every pin is maintained as a single group, and missing or non-existing pin\n> + * would be maintained as dummy group to synchronize pin group index with\n> + * pin descriptor registered with pinctrl core.\n> + * Clients would not be able to request these dummy pin groups.\n> + */\n> +static const struct msm_pingroup hawi_groups[] = {\n> +\t[0] = PINGROUP(0, qup2_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),\n> +\t[1] = PINGROUP(1, qup2_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),\n> +\t[2] = PINGROUP(2, qup2_se0, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[3] = PINGROUP(3, qup2_se0, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[4] = PINGROUP(4, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio),\n> +\t[5] = PINGROUP(5, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio),\n> +\t[6] = PINGROUP(6, qup2_se1, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[7] = PINGROUP(7, qup2_se1, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[8] = PINGROUP(8, qup3_se1, ibi_i3c, _, _, _, _, _, _, _, _, _),\n> +\t[9] = PINGROUP(9, qup3_se1, ibi_i3c, _, _, _, _, _, _, _, _, _),\n> +\t[10] = PINGROUP(10, qup3_se1, _, tsense_clm, tsense_pwm, _, _, _, _, _, _, _),\n> +\t[11] = PINGROUP(11, qup3_se1, _, _, _, _, _, _, _, _, _, _),\n> +\t[12] = PINGROUP(12, qup3_se2, ibi_i3c, qup3_se1, _, _, _, _, _, _, _, _),\n> +\t[13] = PINGROUP(13, qup3_se2, ibi_i3c, qup3_se1, _, _, _, _, _, _, _, _),\n> +\t[14] = PINGROUP(14, qup3_se2, _, _, _, _, _, _, _, _, _, _),\n> +\t[15] = PINGROUP(15, qup3_se2, cci_async_in, qup3_se1, _, _, _, _, _, _, _, _),\n> +\t[16] = PINGROUP(16, qup3_se3, _, _, _, _, _, _, _, _, _, _),\n> +\t[17] = PINGROUP(17, qup3_se3, _, _, _, _, _, _, _, _, _, _),\n> +\t[18] = PINGROUP(18, wcn_sw_ctrl, qup3_se3, _, _, _, _, _, _, _, _, _),\n> +\t[19] = PINGROUP(19, wcn_sw_ctrl, qup3_se3, _, _, _, _, _, _, _, _, _),\n> +\t[20] = PINGROUP(20, qup3_se4, _, _, _, _, _, _, _, _, _, _),\n> +\t[21] = PINGROUP(21, qup3_se4, _, _, _, _, _, _, _, _, _, _),\n> +\t[22] = PINGROUP(22, qup3_se4, _, _, _, _, _, _, _, _, _, _),\n> +\t[23] = PINGROUP(23, qup3_se4, _, _, _, _, _, _, _, _, _, _),\n> +\t[24] = PINGROUP(24, qup3_se5, _, _, _, _, _, _, _, _, _, _),\n> +\t[25] = PINGROUP(25, qup3_se5, _, _, _, _, _, _, _, _, _, _),\n> +\t[26] = PINGROUP(26, qup3_se5, _, _, _, _, _, _, _, _, _, _),\n> +\t[27] = PINGROUP(27, qup3_se5, qdss_cti, _, _, _, _, _, _, _, _, _),\n> +\t[28] = PINGROUP(28, qup4_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio),\n> +\t[29] = PINGROUP(29, qup4_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio),\n> +\t[30] = PINGROUP(30, qup4_se1, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[31] = PINGROUP(31, qup4_se1, qdss_cti, _, _, _, _, _, _, _, _, egpio),\n> +\t[32] = PINGROUP(32, qup4_se2, ibi_i3c, _, _, _, _, _, _, _, _, _),\n> +\t[33] = PINGROUP(33, qup4_se2, ibi_i3c, _, _, _, _, _, _, _, _, _),\n> +\t[34] = PINGROUP(34, qup4_se2, _, _, _, _, _, _, _, _, _, _),\n> +\t[35] = PINGROUP(35, qup4_se2, _, _, _, _, _, _, _, _, _, _),\n> +\t[36] = PINGROUP(36, qup1_se4, uim1, ibi_i3c, _, _, _, _, _, _, _, _),\n> +\t[37] = PINGROUP(37, qup1_se4, uim1, ibi_i3c, _, _, _, _, _, _, _, _),\n> +\t[38] = PINGROUP(38, qup1_se4, _, _, _, _, _, _, _, _, _, _),\n> +\t[39] = PINGROUP(39, qup1_se4, uim1, _, _, _, _, _, _, _, _, _),\n> +\t[40] = PINGROUP(40, qup1_se2, ddr_bist, _, gnss_adc, _, _, _, _, _, _, _),\n> +\t[41] = PINGROUP(41, qup1_se2, ddr_bist, _, gnss_adc, _, _, _, _, _, _, _),\n> +\t[42] = PINGROUP(42, qup1_se2, gnss_adc, _, _, _, _, _, _, _, _, _),\n> +\t[43] = PINGROUP(43, qup1_se2, _, ddr_pxi, _, _, _, _, _, _, _, _),\n> +\t[44] = PINGROUP(44, qup1_se3, ddr_bist, ddr_pxi, _, _, _, _, _, _, _, _),\n> +\t[45] = PINGROUP(45, qup1_se3, ddr_bist, ddr_pxi, _, _, _, _, _, _, _, _),\n> +\t[46] = PINGROUP(46, qup1_se3, ddr_pxi, _, _, _, _, _, _, _, _, _),\n> +\t[47] = PINGROUP(47, qup1_se3, dp_hot, _, _, _, _, _, _, _, _, _),\n> +\t[48] = PINGROUP(48, qup4_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),\n> +\t[49] = PINGROUP(49, qup4_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),\n> +\t[50] = PINGROUP(50, qup4_se0, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[51] = PINGROUP(51, qup4_se0, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[52] = PINGROUP(52, qup1_se5, ddr_pxi, _, _, _, _, _, _, _, _, _),\n> +\t[53] = PINGROUP(53, qup1_se5, _, ddr_pxi, _, _, _, _, _, _, _, _),\n> +\t[54] = PINGROUP(54, qup1_se5, uim1, ddr_pxi, _, _, _, _, _, _, _, _),\n> +\t[55] = PINGROUP(55, qup1_se5, uim1, ddr_pxi, _, _, _, _, _, _, _, _),\n> +\t[56] = PINGROUP(56, qup1_se6, uim1, _, _, _, _, _, _, _, _, _),\n> +\t[57] = PINGROUP(57, qup1_se6, _, _, _, _, _, _, _, _, _, _),\n> +\t[58] = PINGROUP(58, qup1_se6, _, _, _, _, _, _, _, _, _, _),\n> +\t[59] = PINGROUP(59, qup1_se6, usb_phy, vsense_trigger_mirnat, _, _, _, _, _, _, _, _),\n> +\t[60] = PINGROUP(60, qup1_se7, usb_phy, ibi_i3c, _, _, _, _, _, _, _, _),\n> +\t[61] = PINGROUP(61, qup1_se7, ibi_i3c, _, _, _, _, _, _, _, _, _),\n> +\t[62] = PINGROUP(62, qup1_se7, _, _, _, _, _, _, _, _, _, _),\n> +\t[63] = PINGROUP(63, qup1_se7, _, _, _, _, _, _, _, _, _, _),\n> +\t[64] = PINGROUP(64, qup3_se0_01, qup3_se0_23, rng_rosc, tmess_rng, _, _, _, _, _, _, _),\n> +\t[65] = PINGROUP(65, qup3_se0_01, qup3_se0_23, rng_rosc, tmess_rng, _, _, _, _, _, _, _),\n> +\t[66] = PINGROUP(66, i2chub0_se0, rng_rosc, tmess_rng, _, _, _, _, _, _, _, _),\n> +\t[67] = PINGROUP(67, i2chub0_se0, _, _, _, _, _, _, _, _, _, _),\n> +\t[68] = PINGROUP(68, i2chub0_se2, _, _, _, _, _, _, _, _, _, _),\n> +\t[69] = PINGROUP(69, i2chub0_se2, _, _, _, _, _, _, _, _, _, _),\n> +\t[70] = PINGROUP(70, i2chub0_se3, uim1, _, atest_usb, _, _, _, _, _, _, _),\n> +\t[71] = PINGROUP(71, i2chub0_se3, uim1, _, atest_usb, _, _, _, _, _, _, _),\n> +\t[72] = PINGROUP(72, i2chub0_se4, uim1, qdss_cti, _, atest_usb, _, _, _, _, _, _),\n> +\t[73] = PINGROUP(73, i2chub0_se4, qdss_cti, jitter_bist, atest_usb, _, _, _, _, _, _, _),\n> +\t[74] = PINGROUP(74, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _),\n> +\t[75] = PINGROUP(75, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _),\n> +\t[76] = PINGROUP(76, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _),\n> +\t[77] = PINGROUP(77, qup1_se1, aoss_cti, gnss_adc, _, _, _, _, _, _, _, _),\n> +\t[78] = PINGROUP(78, i2chub0_se1, _, _, _, _, _, _, _, _, _, _),\n> +\t[79] = PINGROUP(79, i2chub0_se1, usb0_hs, _, _, _, _, _, _, _, _, _),\n> +\t[80] = PINGROUP(80, qup1_se0, sdc4_data, qspi, _, _, _, _, _, _, _, _),\n> +\t[81] = PINGROUP(81, qup1_se0, sdc4_data, qspi, _, _, _, _, _, _, _, _),\n> +\t[82] = PINGROUP(82, qup1_se0, sdc4_data, qdss_cti, qspi, dbg_out_clk, _, _, _, _, _, _),\n> +\t[83] = PINGROUP(83, qup1_se0, sdc4_clk, qdss_cti, qspi_clk, _, _, _, _, _, _, _),\n> +\t[84] = PINGROUP(84, qup4_se3_01, qup4_se3_23, rng_rosc, tmess_rng, _, _, _, _, _, _, _),\n> +\t[85] = PINGROUP(85, sd_write_protect, _, _, _, _, _, _, _, _, _, _),\n> +\t[86] = PINGROUP(86, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, mdp_esync1, gcc_gp,\n> +\t\t\t_, _, _, _, _, _),\n> +\t[87] = PINGROUP(87, mdp_vsync, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out,\n> +\t\t\tmdp_esync2, gcc_gp, _, tsense_clm, tsense_pwm, _, _),\n> +\t[88] = PINGROUP(88, mdp_esync0, mdp_vsync, qup4_se4_l3, tb_trig_sdc, _, _, _, _, _, _, _),\n> +\t[89] = PINGROUP(89, cam_mclk, _, _, _, _, _, _, _, _, _, _),\n> +\t[90] = PINGROUP(90, cam_mclk, _, _, _, _, _, _, _, _, _, _),\n> +\t[91] = PINGROUP(91, cam_mclk, _, _, _, _, _, _, _, _, _, _),\n> +\t[92] = PINGROUP(92, cam_mclk, _, _, _, _, _, _, _, _, _, _),\n> +\t[93] = PINGROUP(93, cam_mclk, _, _, _, _, _, _, _, _, _, _),\n> +\t[94] = PINGROUP(94, cam_mclk, pll_clk_aux, _, _, _, _, _, _, _, _, _),\n> +\t[95] = PINGROUP(95, cam_mclk, _, _, _, _, _, _, _, _, _, _),\n> +\t[96] = PINGROUP(96, cam_mclk, _, _, _, _, _, _, _, _, _, _),\n> +\t[97] = PINGROUP(97, mdp_esync2, qup2_se3, mdp_vsync, tsense_clm, tsense_pwm, _, _,\n> +\t\t\t_, _, _, _),\n> +\t[98] = PINGROUP(98, mdp_vsync_e, qup4_se3_l3, mdp_vsync_p, _, _, _, _, _, _, _, _),\n> +\t[99] = PINGROUP(99, sys_throttle, tsense_clm, tsense_pwm, _, _, _, _, _, _, _, _),\n> +\t[100] = PINGROUP(100, mdp_esync1, mdp_esync0, _, _, _, _, _, _, _, _, _),\n> +\t[101] = PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _),\n> +\t[102] = PINGROUP(102, pcie0_rst_n, _, _, _, _, _, _, _, _, _, _),\n> +\t[103] = PINGROUP(103, pcie0_clk_req_n, _, _, _, _, _, _, _, _, _, _),\n> +\t[104] = PINGROUP(104, pll_bist_sync, _, _, _, _, _, _, _, _, _, _),\n> +\t[105] = PINGROUP(105, cci_timer, tsense_clm, _, _, _, _, _, _, _, _, _),\n> +\t[106] = PINGROUP(106, host_rst, cci_timer, tsense_clm, _, _, _, _, _, _, _, _),\n> +\t[107] = PINGROUP(107, cci_i2c3, cci_timer, _, _, _, _, _, _, _, _, _),\n> +\t[108] = PINGROUP(108, cci_i2c4, _, _, _, _, _, _, _, _, _, _),\n> +\t[109] = PINGROUP(109, cci_i2c0, cci_async_in, _, _, _, _, _, _, _, _, _),\n> +\t[110] = PINGROUP(110, cci_i2c0, cci_async_in, _, _, _, _, _, _, _, _, _),\n> +\t[111] = PINGROUP(111, cci_i2c1, _, _, _, _, _, _, _, _, _, _),\n> +\t[112] = PINGROUP(112, cci_i2c1, _, _, _, _, _, _, _, _, _, _),\n> +\t[113] = PINGROUP(113, cci_i2c2, _, _, _, _, _, _, _, _, _, _),\n> +\t[114] = PINGROUP(114, cci_i2c2, _, _, _, _, _, _, _, _, _, _),\n> +\t[115] = PINGROUP(115, cci_i2c5, _, _, _, _, _, _, _, _, _, _),\n> +\t[116] = PINGROUP(116, cci_i2c5, _, _, _, _, _, _, _, _, _, _),\n> +\t[117] = PINGROUP(117, i2s1, qup2_se2, phase_flag, _, _, _, _, _, _, _, _),\n> +\t[118] = PINGROUP(118, i2s1, qup2_se2, phase_flag, _, _, _, _, _, _, _, _),\n> +\t[119] = PINGROUP(119, i2s1, qup2_se2, phase_flag, _, _, _, _, _, _, _, _),\n> +\t[120] = PINGROUP(120, i2s1, qup2_se2, audio_ext_mclk, audio_ref_clk, _, _,\n> +\t\t\t_, _, _, _, _),\n> +\t[121] = PINGROUP(121, audio_ext_mclk, qup4_se3_01, qup4_se3_23, _, _, _, _, _, _, _, _),\n> +\t[122] = PINGROUP(122, i2s0, qup2_se3, _, _, _, _, _, _, _, _, _),\n> +\t[123] = PINGROUP(123, i2s0, qup2_se3, _, phase_flag, _, _, _, _, _, _, _),\n> +\t[124] = PINGROUP(124, i2s0, qup2_se3, _, phase_flag, _, _, _, _, _, _, _),\n> +\t[125] = PINGROUP(125, i2s0, qup2_se3, phase_flag, _, _, _, _, _, _, _, _),\n> +\t[126] = PINGROUP(126, uim0, atest_char, _, _, _, _, _, _, _, _, _),\n> +\t[127] = PINGROUP(127, uim0, atest_char, _, _, _, _, _, _, _, _, _),\n> +\t[128] = PINGROUP(128, uim0, atest_char, _, _, _, _, _, _, _, _, _),\n> +\t[129] = PINGROUP(129, uim0, atest_usb, atest_char, _, _, _, _, _, _, _, _),\n> +\t[130] = PINGROUP(130, uim1, qup1_se2, gcc_gp, _, _, _, _, _, _, _, _),\n> +\t[131] = PINGROUP(131, uim1, qup1_se2, gcc_gp, _, _, _, _, _, _, _, _),\n> +\t[132] = PINGROUP(132, uim1, qup1_se2, gcc_gp, _, _, _, _, _, _, _, _),\n> +\t[133] = PINGROUP(133, uim1, atest_char, _, _, _, _, _, _, _, _, _),\n> +\t[134] = PINGROUP(134, _, _, nav_rffe, _, _, _, _, _, _, _, _),\n> +\t[135] = PINGROUP(135, _, _, nav_rffe, _, _, _, _, _, _, _, _),\n> +\t[136] = PINGROUP(136, _, _, _, _, _, _, _, _, _, _, _),\n> +\t[137] = PINGROUP(137, _, _, _, _, _, _, _, _, _, _, _),\n> +\t[138] = PINGROUP(138, _, _, nav_rffe, _, _, _, _, _, _, _, _),\n> +\t[139] = PINGROUP(139, _, _, nav_rffe, _, _, _, _, _, _, _, _),\n> +\t[140] = PINGROUP(140, _, _, _, _, _, _, _, _, _, _, _),\n> +\t[141] = PINGROUP(141, _, _, _, _, _, _, _, _, _, _, _),\n> +\t[142] = PINGROUP(142, _, _, _, _, _, _, _, _, _, _, _),\n> +\t[143] = PINGROUP(143, _, _, _, _, _, _, _, _, _, _, _),\n> +\t[144] = PINGROUP(144, coex_uart1_rx, coex_espmi, _, _, _, _, _, _, _, _, _),\n> +\t[145] = PINGROUP(145, coex_uart1_tx, coex_espmi, _, _, _, _, _, _, _, _, _),\n> +\t[146] = PINGROUP(146, _, vfr, nav_gpio, tb_trig_sdc, qspi_cs, _, _, _, _, _, _),\n> +\t[147] = PINGROUP(147, _, nav_gpio, sdc4_data, qspi, _, _, _, _, _, _, _),\n> +\t[148] = PINGROUP(148, nav_gpio, _, sdc4_cmd, qspi_cs, _, _, _, _, _, _, _),\n> +\t[149] = PINGROUP(149, cci_i2c4, _, _, _, _, _, _, _, _, _, _),\n> +\t[150] = PINGROUP(150, nav_gpio0, nav_gpio3, _, _, _, _, _, _, _, _, _),\n> +\t[151] = PINGROUP(151, nav_gpio, vfr, modem_pps_in, modem_pps_out, _, _, _, _, _, _, _),\n> +\t[152] = PINGROUP(152, qlink, qdss_cti, _, _, _, _, _, _, _, _, _),\n> +\t[153] = PINGROUP(153, qlink, _, _, _, _, _, _, _, _, _, _),\n> +\t[154] = PINGROUP(154, qlink, _, _, _, _, _, _, _, _, _, _),\n> +\t[155] = PINGROUP(155, wcn_sw_ctrl, _, _, _, _, _, _, _, _, _, _),\n> +\t[156] = PINGROUP(156, wcn_sw_ctrl, _, _, _, _, _, _, _, _, _, _),\n> +\t[157] = PINGROUP(157, _, _, _, _, _, _, _, _, _, _, _),\n> +\t[158] = PINGROUP(158, qdss_cti, gcc_gp, _, _, _, _, _, _, _, _, _),\n> +\t[159] = PINGROUP(159, cci_timer, tsense_clm, _, _, _, _, _, _, _, _, _),\n> +\t[160] = PINGROUP(160, cci_timer, cci_i2c3, _, _, _, _, _, _, _, _, _),\n> +\t[161] = PINGROUP(161, qup4_se4_01, qup4_se4_23, _, _, _, _, _, _, _, _, _),\n> +\t[162] = PINGROUP(162, qup4_se4_01, qup4_se4_23, _, _, _, _, _, _, _, _, _),\n> +\t[163] = PINGROUP(163, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[164] = PINGROUP(164, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[165] = PINGROUP(165, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[166] = PINGROUP(166, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[167] = PINGROUP(167, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[168] = PINGROUP(168, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[169] = PINGROUP(169, phase_flag, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[170] = PINGROUP(170, phase_flag, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[171] = PINGROUP(171, phase_flag, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[172] = PINGROUP(172, phase_flag, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[173] = PINGROUP(173, phase_flag, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[174] = PINGROUP(174, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[175] = PINGROUP(175, phase_flag, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[176] = PINGROUP(176, phase_flag, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[177] = PINGROUP(177, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[178] = PINGROUP(178, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[179] = PINGROUP(179, phase_flag, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[180] = PINGROUP(180, phase_flag, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[181] = PINGROUP(181, phase_flag, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[182] = PINGROUP(182, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[183] = PINGROUP(183, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[184] = PINGROUP(184, phase_flag, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[185] = PINGROUP(185, phase_flag, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[186] = PINGROUP(186, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[187] = PINGROUP(187, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[188] = PINGROUP(188, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[189] = PINGROUP(189, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[190] = PINGROUP(190, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[191] = PINGROUP(191, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[192] = PINGROUP(192, phase_flag, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[193] = PINGROUP(193, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[194] = PINGROUP(194, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[195] = PINGROUP(195, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[196] = PINGROUP(196, phase_flag, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[197] = PINGROUP(197, phase_flag, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[198] = PINGROUP(198, phase_flag, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[199] = PINGROUP(199, phase_flag, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[200] = PINGROUP(200, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[201] = PINGROUP(201, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[202] = PINGROUP(202, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[203] = PINGROUP(203, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[204] = PINGROUP(204, phase_flag, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[205] = PINGROUP(205, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[206] = PINGROUP(206, phase_flag, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[207] = PINGROUP(207, phase_flag, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[208] = PINGROUP(208, qup2_se4_01, qup2_se4_23, phase_flag, _, _, _, _, _, _, _, egpio),\n> +\t[209] = PINGROUP(209, qup2_se4_01, qup2_se4_23, _, _, _, _, _, _, _, _, egpio),\n> +\t[210] = PINGROUP(210, phase_flag, _, _, _, _, _, _, _, _, _, _),\n> +\t[211] = PINGROUP(211, phase_flag, _, _, _, _, _, _, _, _, _, _),\n> +\t[212] = PINGROUP(212, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[213] = PINGROUP(213, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[214] = PINGROUP(214, phase_flag, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[215] = PINGROUP(215, phase_flag, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[216] = PINGROUP(216, phase_flag, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[217] = PINGROUP(217, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[218] = PINGROUP(218, _, _, _, _, _, _, _, _, _, _, egpio),\n> +\t[219] = PINGROUP(219, _, _, _, _, _, _, _, _, _, _, _),\n> +\t[220] = PINGROUP(220, _, _, _, _, _, _, _, _, _, _, _),\n> +\t[221] = PINGROUP(221, pcie1_clk_req_n, _, _, _, _, _, _, _, _, _, _),\n> +\t[222] = PINGROUP(222, _, _, _, _, _, _, _, _, _, _, _),\n> +\t[223] = PINGROUP(223, tsense_pwm, _, _, _, _, _, _, _, _, _, _),\n> +\t[224] = PINGROUP(224, tsense_pwm, _, _, _, _, _, _, _, _, _, _),\n> +\t[225] = PINGROUP(225, tsense_pwm, _, _, _, _, _, _, _, _, _, _),\n> +\t[226] = UFS_RESET(ufs_reset, 0xf1004, 0xf2000),\n> +\t[227] = SDC_QDSD_PINGROUP(sdc2_clk, 0xe6000, 14, 6),\n> +\t[228] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xe6000, 11, 3),\n> +\t[229] = SDC_QDSD_PINGROUP(sdc2_data, 0xe6000, 9, 0),\n> +};\n> +\n> +static const struct msm_gpio_wakeirq_map hawi_pdc_map[] = {\n> +\t{ 0, 105 }, { 3, 113 }, { 4, 106 }, { 7, 107 }, { 8, 108 }, { 11, 109 },\n> +\t{ 12, 115 }, { 15, 131 }, { 16, 116 }, { 17, 141 }, { 18, 143 }, { 19, 112 },\n> +\t{ 23, 117 }, { 24, 118 }, { 27, 119 }, { 28, 125 }, { 31, 126 }, { 32, 127 },\n> +\t{ 35, 101 }, { 36, 128 }, { 39, 129 }, { 43, 130 }, { 47, 154 }, { 48, 135 },\n> +\t{ 51, 114 }, { 55, 104 }, { 57, 136 }, { 58, 137 }, { 59, 138 }, { 60, 139 },\n> +\t{ 61, 145 }, { 63, 124 }, { 64, 110 }, { 65, 123 }, { 67, 132 }, { 68, 146 },\n> +\t{ 69, 147 }, { 75, 151 }, { 77, 148 }, { 78, 149 }, { 79, 155 }, { 80, 156 },\n> +\t{ 81, 157 }, { 82, 158 }, { 84, 134 }, { 85, 159 }, { 86, 160 }, { 87, 161 },\n> +\t{ 88, 162 }, { 95, 163 }, { 96, 164 }, { 97, 133 }, { 98, 150 }, { 99, 111 },\n> +\t{ 101, 165 }, { 102, 166 }, { 103, 167 }, { 104, 168 }, { 120, 169 }, { 123, 170 },\n> +\t{ 125, 171 }, { 129, 153 }, { 133, 100 }, { 144, 172 }, { 146, 173 }, { 151, 174 },\n> +\t{ 152, 175 }, { 155, 122 }, { 158, 120 }, { 162, 142 }, { 164, 176 }, { 165, 177 },\n> +\t{ 167, 178 }, { 168, 179 }, { 174, 180 }, { 177, 181 }, { 179, 182 }, { 183, 183 },\n> +\t{ 184, 184 }, { 185, 185 }, { 186, 152 }, { 188, 144 }, { 202, 102 }, { 203, 103 },\n> +\t{ 205, 140 }, { 209, 186 }, { 213, 121 }, { 216, 187 }, { 221, 188 }, { 222, 189 },\n> +\t{ 223, 190 }, { 224, 191 }, { 225, 192 },\n> +};\n> +\n> +static const struct msm_pinctrl_soc_data hawi_tlmm = {\n> +\t.pins = hawi_pins,\n> +\t.npins = ARRAY_SIZE(hawi_pins),\n> +\t.functions = hawi_functions,\n> +\t.nfunctions = ARRAY_SIZE(hawi_functions),\n> +\t.groups = hawi_groups,\n> +\t.ngroups = ARRAY_SIZE(hawi_groups),\n> +\t.ngpios = 227,\n> +\t.wakeirq_map = hawi_pdc_map,\n> +\t.nwakeirq_map = ARRAY_SIZE(hawi_pdc_map),\n> +\t.egpio_func = 11,\n> +};\n> +\n> +static int hawi_tlmm_probe(struct platform_device *pdev)\n> +{\n> +\treturn msm_pinctrl_probe(pdev, &hawi_tlmm);\n> +}\n> +\n> +static const struct of_device_id hawi_tlmm_of_match[] = {\n> +\t{ .compatible = \"qcom,hawi-tlmm\", },\n> +\t{},\n> +};\n> +\n> +static struct platform_driver hawi_tlmm_driver = {\n> +\t.driver = {\n> +\t\t.name = \"hawi-tlmm\",\n> +\t\t.of_match_table = hawi_tlmm_of_match,\n> +\t},\n> +\t.probe = hawi_tlmm_probe,\n> +};\n> +\n> +static int __init hawi_tlmm_init(void)\n> +{\n> +\treturn platform_driver_register(&hawi_tlmm_driver);\n> +}\n> +arch_initcall(hawi_tlmm_init);\n> +\n> +static void __exit hawi_tlmm_exit(void)\n> +{\n> +\tplatform_driver_unregister(&hawi_tlmm_driver);\n> +}\n> +module_exit(hawi_tlmm_exit);\n> +\n> +MODULE_DESCRIPTION(\"QTI Hawi TLMM driver\");\n> +MODULE_LICENSE(\"GPL\");\n> +MODULE_DEVICE_TABLE(of, hawi_tlmm_of_match);\n> \n> -- \n> 2.53.0\n>","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=dKIRMtae;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; helo=sin.lore.kernel.org;\n envelope-from=linux-gpio+bounces-34909-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"dKIRMtae\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sin.lore.kernel.org (sin.lore.kernel.org\n [IPv6:2600:3c15:e001:75::12fc:5321])\n\t(using TLSv1.3 with cipher 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smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1775699453;\n\tbh=+I4F8AB7F9q+OaQsfem/7VTxoVXkkpWtXf/DncAKoJU=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=dKIRMtaeVR6rGlV2pUTFUwyK1K5ixWdcqdP7Ns3KV03bgtycLb01vwf5CFwP22cHW\n\t XPl8VwJS+xZnwzfeVuVujfo77Xi5yM2kTaAaPvuaQX5LuB2tTXSEzfbxsvq3s1AT6o\n\t 0SiQzVysf1dOzkwgXHSojxKcWxAmvq2SFUeA4yT09Y8qFfbWRV22dnTjCDVPOOsseH\n\t tGZAopw6gQ2SDku9gZC8l5atoXMrmomox4KWxXr+fNTroNKJkv9p/+DFOPn8I2fznr\n\t adFqbB7ZoUDmnnu1NAdmd1i7jANpmgU0N9yYNoqHphb5SgxukqZ3aRI5em7xsLGbuP\n\t X0HQPeawX5F4w==","Date":"Wed, 8 Apr 2026 20:50:50 -0500","From":"Bjorn Andersson ","To":"Mukesh Ojha ","Cc":"Linus Walleij , Rob Herring ,\n\tKrzysztof Kozlowski , Conor Dooley ,\n\tlinux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,\n devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, Konrad Dybcio ","Subject":"Re: [PATCH v2 2/2] pinctrl: qcom: Add Hawi pinctrl driver","Message-ID":"","References":"<20260408-hawi-pinctrl-v2-0-fd7f681f5e05@oss.qualcomm.com>\n <20260408-hawi-pinctrl-v2-2-fd7f681f5e05@oss.qualcomm.com>","Precedence":"bulk","X-Mailing-List":"linux-gpio@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20260408-hawi-pinctrl-v2-2-fd7f681f5e05@oss.qualcomm.com>"}}]