[{"id":3676636,"web_url":"http://patchwork.ozlabs.org/comment/3676636/","msgid":"<20260413103050.GL469338@kernel.org>","list_archive_url":null,"date":"2026-04-13T10:30:50","subject":"Re: [Intel-wired-lan] [PATCH iwl-net v2 2/6] ixgbe: add bounds\n check for debugfs register access","submitter":{"id":82748,"url":"http://patchwork.ozlabs.org/api/people/82748/","name":"Simon Horman","email":"horms@kernel.org"},"content":"On Wed, Apr 08, 2026 at 03:11:50PM +0200, Aleksandr Loktionov wrote:\n> From: Paul Greenwalt \n> \n> Prevent out-of-bounds MMIO accesses triggered through user-controlled\n> register offsets. IXGBE_HFDR (0x15FE8) is the highest valid MMIO\n> register in the ixgbe register map; any offset beyond it would address\n> unmapped memory.\n> \n> Add a defense-in-depth check at two levels:\n> \n> 1. ixgbe_read_reg() -- the noinline register read accessor. A\n> WARN_ON_ONCE() guard here catches any future code path (including\n> ioctl extensions) that might inadvertently pass an out-of-range\n> offset without relying on higher layers to catch it first.\n> ixgbe_write_reg() is a static inline called from the TX/RX hot path;\n> adding WARN_ON_ONCE there would inline the check at every call site,\n> so only the read path gets this guard.\n> \n> 2. ixgbe_dbg_reg_ops_write() -- the debugfs 'reg_ops' interface is the\n> only current path where a raw, user-supplied offset enters the driver.\n> Gating it before invoking the register accessors provides a clean,\n> user-visible failure (silent ignore with no kernel splat) for\n> deliberately malformed debugfs writes.\n> \n> Add a reg <= IXGBE_HFDR guard to both the read and write paths in\n> ixgbe_dbg_reg_ops_write(), and a WARN_ON_ONCE + early-return guard to\n> ixgbe_read_reg().\n> \n> Fixes: 91fbd8f081e2 (\"ixgbe: added reg_ops file to debugfs\")\n> Signed-off-by: Paul Greenwalt \n> Cc: stable@vger.kernel.org\n> Signed-off-by: Aleksandr Loktionov \n> ---\n> v1 -> v2:\n> - Add Fixes: tag; reroute from iwl-next to iwl-net (security-relevant\n> hardening for user-controllable out-of-bounds MMIO).\n\nThanks for the update.\n\nAnd sorry for not thinking to ask this earlier: this patch\naddresses possible overruns of the mapped address space if the\nsupplied value for reg is too large. But do we also need a\nguard against underrun if the value for reg is too small?\n\n...","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=97xs6mSH;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=140.211.166.136; helo=smtp3.osuosl.org;\n envelope-from=intel-wired-lan-bounces@osuosl.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from smtp3.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fvNwk2rslz1xtJ\n\tfor ; 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IXGBE_HFDR (0x15FE8) is the highest valid MMIO\n>> register in the ixgbe register map; any offset beyond it would address\n>> unmapped memory.\n>>\n>> Add a defense-in-depth check at two levels:\n>>\n>> 1. ixgbe_read_reg() -- the noinline register read accessor. A\n>> WARN_ON_ONCE() guard here catches any future code path (including\n>> ioctl extensions) that might inadvertently pass an out-of-range\n>> offset without relying on higher layers to catch it first.\n>> ixgbe_write_reg() is a static inline called from the TX/RX hot path;\n>> adding WARN_ON_ONCE there would inline the check at every call site,\n>> so only the read path gets this guard.\n>>\n>> 2. ixgbe_dbg_reg_ops_write() -- the debugfs 'reg_ops' interface is the\n>> only current path where a raw, user-supplied offset enters the driver.\n>> Gating it before invoking the register accessors provides a clean,\n>> user-visible failure (silent ignore with no kernel splat) for\n>> deliberately malformed debugfs writes.\n>>\n>> Add a reg <= IXGBE_HFDR guard to both the read and write paths in\n>> ixgbe_dbg_reg_ops_write(), and a WARN_ON_ONCE + early-return guard to\n>> ixgbe_read_reg().\n>>\n>> Fixes: 91fbd8f081e2 (\"ixgbe: added reg_ops file to debugfs\")\n>> Signed-off-by: Paul Greenwalt \n>> Cc: stable@vger.kernel.org\n>> Signed-off-by: Aleksandr Loktionov \n>> ---\n>> v1 -> v2:\n>> - Add Fixes: tag; reroute from iwl-next to iwl-net (security-relevant\n>> hardening for user-controllable out-of-bounds MMIO).\n> \n> Thanks for the update.\n> \n> And sorry for not thinking to ask this earlier: this patch\n> addresses possible overruns of the mapped address space if the\n> supplied value for reg is too large. But do we also need a\n> guard against underrun if the value for reg is too small?\n> \n\nI don't think so. This is bounds checking a register offset which is an\nunsigned 32-bit value and begins at 0, so the map goes from 0 to\nIXGBE_HFDR. Since the value is unsigned, if it does underflow somehow it\nwould then get caught by the check for IXGBE_HFDR right?\n\nThanks,\nJake\n\n> ...","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=FxUVsAzx;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::137; helo=smtp4.osuosl.org;\n envelope-from=intel-wired-lan-bounces@osuosl.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from smtp4.osuosl.org (smtp4.osuosl.org [IPv6:2605:bc80:3010::137])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fvmD83HDtz1yCv\n\tfor ; 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IXGBE_HFDR (0x15FE8) is the highest valid MMIO\n> >> register in the ixgbe register map; any offset beyond it would address\n> >> unmapped memory.\n> >>\n> >> Add a defense-in-depth check at two levels:\n> >>\n> >> 1. ixgbe_read_reg() -- the noinline register read accessor. A\n> >> WARN_ON_ONCE() guard here catches any future code path (including\n> >> ioctl extensions) that might inadvertently pass an out-of-range\n> >> offset without relying on higher layers to catch it first.\n> >> ixgbe_write_reg() is a static inline called from the TX/RX hot path;\n> >> adding WARN_ON_ONCE there would inline the check at every call site,\n> >> so only the read path gets this guard.\n> >>\n> >> 2. ixgbe_dbg_reg_ops_write() -- the debugfs 'reg_ops' interface is the\n> >> only current path where a raw, user-supplied offset enters the driver.\n> >> Gating it before invoking the register accessors provides a clean,\n> >> user-visible failure (silent ignore with no kernel splat) for\n> >> deliberately malformed debugfs writes.\n> >>\n> >> Add a reg <= IXGBE_HFDR guard to both the read and write paths in\n> >> ixgbe_dbg_reg_ops_write(), and a WARN_ON_ONCE + early-return guard to\n> >> ixgbe_read_reg().\n> >>\n> >> Fixes: 91fbd8f081e2 (\"ixgbe: added reg_ops file to debugfs\")\n> >> Signed-off-by: Paul Greenwalt \n> >> Cc: stable@vger.kernel.org\n> >> Signed-off-by: Aleksandr Loktionov \n> >> ---\n> >> v1 -> v2:\n> >> - Add Fixes: tag; reroute from iwl-next to iwl-net (security-relevant\n> >> hardening for user-controllable out-of-bounds MMIO).\n> > \n> > Thanks for the update.\n> > \n> > And sorry for not thinking to ask this earlier: this patch\n> > addresses possible overruns of the mapped address space if the\n> > supplied value for reg is too large. But do we also need a\n> > guard against underrun if the value for reg is too small?\n> > \n> \n> I don't think so. This is bounds checking a register offset which is an\n> unsigned 32-bit value and begins at 0, so the map goes from 0 to\n> IXGBE_HFDR. Since the value is unsigned, if it does underflow somehow it\n> would then get caught by the check for IXGBE_HFDR right?\n\nIf the entire range from 0 to IXGBE_HFDR is mapped,\nand it's ok for reg to have any value in that range,\nthen I agree there is no problem here.\n\nReviewed-by: Simon Horman ","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=VsesJfI3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::138; helo=smtp1.osuosl.org;\n envelope-from=intel-wired-lan-bounces@osuosl.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from smtp1.osuosl.org (smtp1.osuosl.org [IPv6:2605:bc80:3010::138])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fw9tJ6D4Vz1yCv\n\tfor ; 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