[{"id":3674755,"web_url":"http://patchwork.ozlabs.org/comment/3674755/","msgid":"<2f19cd1b-b1ff-4053-8507-675f5bd02133@linaro.org>","list_archive_url":null,"date":"2026-04-08T09:26:55","subject":"Re: [PATCH v1 5/9] misc: qcom_geni: Add minicore support","submitter":{"id":90679,"url":"http://patchwork.ozlabs.org/api/people/90679/","name":"Casey Connolly","email":"casey.connolly@linaro.org"},"content":"Hi Varadarajan,\n\nOn 08/04/2026 11:11, Varadarajan Narayanan wrote:\n> The qcom_geni driver reads an ELF from storage and configures a set of\n> registers and programs the firmware to the GENI Serial Engine (GENI-SE)\n> wrapper device for the expected functionality.\n> \n> Unlike the GENI-SE wrapper found in MSM SoCs, the IPQ5210's GENI-SE\n> wrapper is pre-configured for one of the functions defined in 'enum\n> geni_se_protocol_type'. Hence, the firmware download is not needed.\n> Only the register configuration part is needed.\n\nI don't think we should be embedding this ~1kb of data for just these\nplatforms.\n\nPlease move these to a separate file gated behind some new kconfig option.\n\n> \n> Earlier, the boot stages before U-Boot would configure the GENI-SE (to\n> access UART/SPI etc). Since for IPQ5210 U-Boot SPL, the previous stage\n> (i.e. boot ROM) doesn't do that modify the driver to do the register\n> configuration part alone without reading an ELF from the storage.\n> \n> Signed-off-by: Varadarajan Narayanan \n> ---\n> drivers/misc/qcom_geni.c | 168 ++++++++++++++++++++++++++++++---\n> include/soc/qcom/geni-se.h | 5 +\n> include/soc/qcom/qup-fw-load.h | 15 +++\n> 3 files changed, 175 insertions(+), 13 deletions(-)\n> \n> diff --git a/drivers/misc/qcom_geni.c b/drivers/misc/qcom_geni.c\n> index a62ae6a2478..d02ea804c33 100644\n> --- a/drivers/misc/qcom_geni.c\n> +++ b/drivers/misc/qcom_geni.c\n> @@ -34,6 +34,102 @@ struct qup_se_rsc {\n> \n> struct geni_se_plat {\n> \tbool need_firmware_load;\n> +\tbool is_mini_core;\n> +};\n> +\n> +/*\n> + * Register configuration for the QUP minicores to setup the corresponding\n> + * functionality of SPI/I2C/UART.\n> + */\n> +static u8 cfg_reg_idx[] = {\n> +\t/* 0 to 18 */\n> +\t0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,\n> +\t/* 64 to 113 */\n> +\t64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,\n> +\t81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,\n> +\t98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,\n> +\t112, 113,\n> +};\n> +\n> +static u32 spi_cfg_val[] = {\n> +\t/* 0 to 18 */\n> +\t0x00000000, 0x00000400, 0x00000000, 0x00000000, 0x00240E78, 0x00011088,\n> +\t0x00240007, 0x00000000, 0x00000000, 0x0001000A, 0x00000300, 0x00000000,\n> +\t0x00000000, 0x00000000, 0x00154400, 0x001483A0, 0x00AA8128, 0x00641002,\n> +\t0x00004000,\n> +\t/* 64 to 113 */\n> +\t0x00000201, 0x0001FE05, 0x0002C2E7, 0x0A435C00, 0x0010011A, 0x08800000,\n> +\t0x00000000, 0x100CAC00, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n> +\t0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000018E4, 0x00000000,\n> +\t0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n> +\t0x0007F807, 0x000FFEFE, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n> +\t0x00200000, 0x00000004, 0x00000009, 0x0007F807, 0x000FFEFE, 0x00000000,\n> +\t0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n> +\t0x00000000, 0x00000000, 0x00C0033F, 0x00000000, 0x00000000, 0x00000000,\n> +\t0x00000000, 0x00000055,\n> +};\n> +\n> +static u32 uart_cfg_val[] = {\n> +\t/* 0 to 18 */\n> +\t0x00000024, 0x00000000, 0x00000024, 0x00000000, 0x00019A00, 0x00400000,\n> +\t0x00E00000, 0x00010020, 0x00000000, 0x00000000, 0x00000300, 0x00000700,\n> +\t0x00000400, 0x00000000, 0x00000000, 0x00C00000, 0x00000000, 0x00C00024,\n> +\t0x00000B00,\n> +\t/* 64 to 113 */\n> +\t0x00020231, 0x0000CE05, 0x000360E7, 0x0941E6A8, 0x00100510, 0x42C01E51,\n> +\t0x00000401, 0x002E8400, 0x1694581A, 0x00000000, 0x00000000, 0x00000000,\n> +\t0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x0000031C, 0x00000000,\n> +\t0x0000000F, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n> +\t0x00081C06, 0x00004010, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n> +\t0x00000000, 0x0000000D, 0x00000000, 0x00081C06, 0x00004010, 0x00000000,\n> +\t0x00000000, 0x00000000, 0x00000000, 0x00C02415, 0x0000000E, 0x00000001,\n> +\t0x00000001, 0x00000000, 0x00C00000, 0x00000000, 0x00000000, 0x00000000,\n> +\t0x00000000, 0x00000055,\n> +};\n> +\n> +static u32 i2c_cfg_val[] = {\n> +\t/* 0 to 18 */\n> +\t0x00000090, 0x00000000, 0x00000090, 0x00000000, 0x00038028, 0x00084080,\n> +\t0x00000343, 0x00010000, 0x00000000, 0x00001A00, 0x00000100, 0x00000000,\n> +\t0x00000000, 0x00000000, 0x00808008, 0x001C0020, 0x00000000, 0x00020000,\n> +\t0x00000000,\n> +\t/* 64 to 113 */\n> +\t0x00000201, 0x0001FC01, 0x00036222, 0x09C01FFC, 0x00100120, 0x02C00000,\n> +\t0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n> +\t0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000409, 0x00000003,\n> +\t0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n> +\t0x0007F8FE, 0x000FFEFE, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n> +\t0x00000000, 0x00000000, 0x00000001, 0x0007F807, 0x000FFEFE, 0x00000000,\n> +\t0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n> +\t0x00000000, 0x00000000, 0x00C00000, 0x00000000, 0x00000000, 0x00000000,\n> +\t0x00000000, 0x00000055,\n> +};\n> +\n> +static struct qup_mini_core_info qup_mini_cores[] = {\n> +\t{\n> +\t\t.serial_protocol = GENI_SE_SPI,\n> +\t\t.fw_version = 0xb02,\n> +\t\t.cfg_version = 0x9,\n> +\t\t.cfg_count = ARRAY_SIZE(spi_cfg_val),\n> +\t\t.cfg_val = spi_cfg_val,\n> +\t\t.cfg_idx = cfg_reg_idx,\n> +\t}, {\n> +\t\t.serial_protocol = GENI_SE_UART,\n> +\t\t.fw_version = 0x405,\n> +\t\t.cfg_version = 0xa,\n> +\t\t.cfg_count = ARRAY_SIZE(uart_cfg_val),\n> +\t\t.cfg_val = uart_cfg_val,\n> +\t\t.cfg_idx = cfg_reg_idx,\n> +\t}, {\n> +\t\t.serial_protocol = GENI_SE_I2C,\n> +\t\t.fw_version = 0x204,\n> +\t\t.cfg_version = 0x9,\n> +\t\t.cfg_count = ARRAY_SIZE(i2c_cfg_val),\n> +\t\t.cfg_val = i2c_cfg_val,\n> +\t\t.cfg_idx = cfg_reg_idx,\n> +\t}, {\n> +\t\t.serial_protocol = GENI_SE_INVALID_PROTO,\n> +\t},\n> };\n> \n> /**\n> @@ -163,16 +259,38 @@ static void geni_config_common_control(struct qup_se_rsc *rsc)\n> \t\t COMMON_CSR_SLV_CLK_CGC_ON_BMASK);\n> }\n> \n> -static int load_se_firmware(struct qup_se_rsc *rsc, struct elf_se_hdr *hdr)\n> +static int load_se_firmware(struct qup_se_rsc *rsc, int elf, void *info)\n\nPlease make this a \"bool\", if you're using clangd or ctags there might\nbe a configuration issue if they're suggesting that \"bool\" isn't a valid\ntype (I've had to deal with that in the past).\n\n> {\n> +\tstruct elf_se_hdr *hdr, tmp_hdr;\n> \tconst u32 *fw_val_arr, *cfg_val_arr;\n> \tconst u8 *cfg_idx_arr;\n> \tu32 i, reg_value, mask, ramn_cnt;\n> \tint ret;\n> \n> -\tfw_val_arr = (const u32 *)((u8 *)hdr + hdr->fw_offset);\n> -\tcfg_idx_arr = (const u8 *)hdr + hdr->cfg_idx_offset;\n> -\tcfg_val_arr = (const u32 *)((u8 *)hdr + hdr->cfg_val_offset);\n> +\tif (elf) {\n> +\t\thdr = info;\n> +\t\tfw_val_arr = (const u32 *)((u8 *)hdr + hdr->fw_offset);\n> +\t\tcfg_idx_arr = (const u8 *)hdr + hdr->cfg_idx_offset;\n> +\t\tcfg_val_arr = (const u32 *)((u8 *)hdr + hdr->cfg_val_offset);\n> +\t} else {\n\nPlease add a comment here briefly explaining that this is for minicore\ncontrollers which don't need the whole firmware.\n\n> +\t\tstruct qup_mini_core_info *qmc = info;\n> +\n> +\t\tfor (; qmc->serial_protocol != GENI_SE_INVALID_PROTO; qmc++)\n> +\t\t\tif (qmc->serial_protocol == rsc->protocol)\n> +\t\t\t\tbreak;\n> +\n> +\t\ttmp_hdr.magic = MAGIC_NUM_SE;\n> +\t\ttmp_hdr.version = 1;\n> +\t\ttmp_hdr.serial_protocol = rsc->protocol;\n> +\t\ttmp_hdr.fw_version = qmc->fw_version;\n> +\t\ttmp_hdr.cfg_version = qmc->cfg_version;\n> +\t\ttmp_hdr.fw_size_in_items = qmc->cfg_ram_count;\n> +\t\ttmp_hdr.cfg_size_in_items = qmc->cfg_count;\n> +\t\thdr = &tmp_hdr;\n> +\t\tfw_val_arr = (const u32 *)qmc->cfg_ram;\n> +\t\tcfg_idx_arr = (const u8 *)qmc->cfg_idx;\n> +\t\tcfg_val_arr = (const u32 *)qmc->cfg_val;\n> +\t}\n> \n> \tgeni_config_common_control(rsc);\n> \n> @@ -350,8 +468,8 @@ int qcom_geni_load_firmware(phys_addr_t qup_base,\n> {\n> \tstruct qup_se_rsc rsc;\n> \tstruct elf_se_hdr *hdr;\n> -\tint ret;\n> -\tvoid *fw;\n> +\tint ret, elf;\n> +\tvoid *fw, *info;\n> \n> \trsc.dev = dev;\n> \trsc.base = qup_base;\n> @@ -377,15 +495,22 @@ int qcom_geni_load_firmware(phys_addr_t qup_base,\n> \t/* The firmware blob is the private data of the GENI wrapper (parent) */\n> \tfw = dev_get_priv(dev->parent);\n> \n> -\tret = read_elf(&rsc, fw, &hdr);\n> -\tif (ret) {\n> -\t\tdev_err(dev, \"Failed to read ELF: %d\\n\", ret);\n> -\t\treturn ret;\n> +\tif (IS_ELF(*(Elf32_Ehdr *)fw)) {\n> +\t\tret = read_elf(&rsc, fw, &hdr);\n> +\t\tif (ret) {\n> +\t\t\tdev_err(dev, \"Failed to read ELF: %d\\n\", ret);\n> +\t\t\treturn ret;\n> +\t\t}\n> +\t\telf = 1;\n> +\t\tinfo = hdr;\n> +\t} else {\n> +\t\telf = 0;\n> +\t\tinfo = fw;\n> \t}\n> \n> \tdev_info(dev, \"Loading QUP firmware...\\n\");\n> \n> -\treturn load_se_firmware(&rsc, hdr);\n> +\treturn load_se_firmware(&rsc, elf, info);\n> }\n> \n> /*\n> @@ -414,6 +539,9 @@ static int geni_se_of_to_plat(struct udevice *dev)\n> \n> \t\tif (proto == GENI_SE_INVALID_PROTO)\n> \t\t\tplat->need_firmware_load = true;\n> +\n> +\t\tif (readl(res.start + QUPV3_SE_HW_PARAM_2) & GEN_USE_MINICORES)\n> +\t\t\tplat->is_mini_core = true;\n> \t}\n> \n> \treturn 0;\n> @@ -473,7 +601,7 @@ static int probe_children_load_firmware(struct udevice *dev)\n> \t\tret = 0;\n> \t\t/* Find the device for this ofnode, or bind it */\n> \t\tif (device_find_global_by_ofnode(child, &child_dev))\n> -\t\t\tret = lists_bind_fdt(dev, child, &child_dev, NULL, false);\t\n> +\t\t\tret = lists_bind_fdt(dev, child, &child_dev, NULL, false);\n> \t\tif (ret) {\n> \t\t\t/* Skip nodes that don't have drivers */\n> \t\t\tdebug(\"Failed to probe child %s: %d\\n\", ofnode_get_name(child), ret);\n> @@ -492,7 +620,11 @@ static int probe_children_load_firmware(struct udevice *dev)\n> * Load firmware for QCOM GENI peripherals from the dedicated partition on storage and bind/probe\n> * all the peripheral devices that need firmware to be loaded.\n> */\n> -static int qcom_geni_fw_initialise(void)\n> +#if CONFIG_XPL_BUILD\n> +int qcom_geni_fw_initialise(struct udevice *dev)\n> +#else\n> +int qcom_geni_fw_initialise(void)\n> +#endif\n> {\n> \tdebug(\"Loading firmware for QCOM GENI SE\\n\");\n> \tstruct udevice *geni_wrapper, *blk_dev;\n> @@ -520,6 +652,10 @@ static int qcom_geni_fw_initialise(void)\n> \n> \tret = find_qupfw_part(&blk_dev, &part_info);\n> \tif (ret) {\n> +\t\tif (plat->is_mini_core) {\n> +\t\t\tfw_buf = qup_mini_cores;\n> +\t\t\tgoto mini_core;\n\nWhy still call find_qupfw_part() in the minicore case? If this is\nintentional please add a comment.\n\n> +\t\t}\n> \t\tpr_err(\"QUP firmware partition not found\\n\");\n> \t\treturn 0;\n> \t}\n> @@ -544,6 +680,7 @@ static int qcom_geni_fw_initialise(void)\n> \t\treturn 0;\n> \t}\n> \n> +mini_core:\n> \t/*\n> \t * OK! Firmware is loaded, now bind and probe remaining children. They will attempt to load\n> \t * firmware during probe. Do this for each GENI SE wrapper that needs firmware loading.\n> @@ -563,7 +700,9 @@ static int qcom_geni_fw_initialise(void)\n> \treturn 0;\n> }\n> \n> +#if !CONFIG_XPL_BUILD\n> EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, qcom_geni_fw_initialise);\n> +#endif\n> \n> static const struct udevice_id geni_ids[] = {\n> \t{ .compatible = \"qcom,geni-se-qup\" },\n> @@ -577,4 +716,7 @@ U_BOOT_DRIVER(geni_se_qup) = {\n> \t.of_to_plat = geni_se_of_to_plat,\n> \t.plat_auto = sizeof(struct geni_se_plat),\n> \t.flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,\n> +#if CONFIG_XPL_BUILD\n> +\t.probe = qcom_geni_fw_initialise,\n> +#endif\n> };\n> diff --git a/include/soc/qcom/geni-se.h b/include/soc/qcom/geni-se.h\n> index fc9a8e82cd8..e51dd06fa94 100644\n> --- a/include/soc/qcom/geni-se.h\n> +++ b/include/soc/qcom/geni-se.h\n> @@ -77,6 +77,7 @@ enum geni_se_protocol_type {\n> #define SE_IRQ_EN\t\t\t0xe1c\n> #define SE_HW_PARAM_0\t\t\t0xe24\n> #define SE_HW_PARAM_1\t\t\t0xe28\n> +#define SE_HW_PARAM_2\t\t\t0xe2c\n> #define SE_DMA_GENERAL_CFG\t\t0xe30\n> \n> /* GENI_DFS_IF_CFG fields */\n> @@ -248,6 +249,10 @@ enum geni_se_protocol_type {\n> /* SE_HW_PARAM_0 fields */\n> #define TX_FIFO_WIDTH_MSK\t\tGENMASK(29, 24)\n> #define TX_FIFO_WIDTH_SHFT\t\t24\n> +\n> +/* SE_HW_PARAM_2 fields */\n> +#define GEN_USE_MINICORES\t\tBIT(12)\n\nGENI_USE_MINICORES\n\nKind regards,\n\n> +\n> /*\n> * For QUP HW Version >= 3.10 Tx fifo depth support is increased\n> * to 256bytes and corresponding bits are 16 to 23\n> diff --git a/include/soc/qcom/qup-fw-load.h b/include/soc/qcom/qup-fw-load.h\n> index a67a93c72a4..a3ae4122681 100644\n> --- a/include/soc/qcom/qup-fw-load.h\n> +++ b/include/soc/qcom/qup-fw-load.h\n> @@ -14,6 +14,7 @@\n> #define GENI_INIT_CFG_REVISION\t\t0x0\n> #define GENI_S_INIT_CFG_REVISION\t0x4\n> #define GENI_FORCE_DEFAULT_REG\t\t0x20\n> +#define GENI_OUTPUT_CTRL\t\t0x24\n> #define GENI_CGC_CTRL\t\t\t0x28\n> #define GENI_CFG_REG0\t\t\t0x100\n> \n> @@ -21,6 +22,9 @@\n> #define RX_FIFO_WIDTH_BIT\t\t24\n> #define RX_FIFO_WIDTH_MASK\t\t0x3F\n> \n> +#define QUPV3_SE_HW_PARAM_2\t\t0xe2c\n> +#define GEN_USE_MINICORES\t\tBIT(12)\n> +\n> /*Same registers as GENI_DMA_MODE_EN*/\n> #define QUPV3_SE_GENI_DMA_MODE_EN\t0x258\n> #define GENI_M_IRQ_ENABLE\t\t0x614\n> @@ -173,6 +177,17 @@ struct elf_se_hdr {\n> \n> struct udevice;\n> \n> +struct qup_mini_core_info {\n> +\tu16 serial_protocol;\n> +\tu16 fw_version;\n> +\tu16 cfg_version;\n> +\tu16 cfg_count;\n> +\tu32 *cfg_val;\n> +\tu8 *cfg_idx;\n> +\tu32 *cfg_ram;\n> +\tu32 cfg_ram_count;\n> +};\n> +\n> int qcom_geni_load_firmware(phys_addr_t qup_base, struct udevice *dev);\n> \n> #endif /* _LINUX_QCOM_QUP_FW_LOAD */","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=cWYU3YvX;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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