[{"id":3682235,"web_url":"http://patchwork.ozlabs.org/comment/3682235/","msgid":"","list_archive_url":null,"date":"2026-04-25T00:46:27","subject":"Re: [Intel-wired-lan] [PATCH iwl-net v2] ice: fix SMA and U.FL pin\n state changes affecting paired pin","submitter":{"id":91947,"url":"http://patchwork.ozlabs.org/api/people/91947/","name":"Nowlin, Alexander","email":"alexander.nowlin@intel.com"},"content":"> -----Original Message-----\n> From: Intel-wired-lan On Behalf Of Petr Oros\n> Sent: Wednesday, April 8, 2026 4:05 AM\n> To: netdev@vger.kernel.org\n> Cc: Kitszel, Przemyslaw ; Eric Dumazet ; Kubalewski, Arkadiusz ; Andrew Lunn ; Nguyen, \n> Anthony L ; Simon Horman ; intel-wired-lan@lists.osuosl.org; Jakub Kicinski ; Paolo Abeni ; David S. Miller \n> ; linux-kernel@vger.kernel.org\n> Subject: [Intel-wired-lan] [PATCH iwl-net v2] ice: fix SMA and U.FL pin state changes affecting paired pin\n> \n> SMA and U.FL pins share physical signal paths in pairs (SMA1/U.FL1 and\n> SMA2/U.FL2) controlled by the PCA9575 GPIO expander. Each pair can only have one active pin at a time: SMA1 output and U.FL1 output share the same CGU output, SMA2 input and U.FL2 input share the \n> same CGU input. The PCA9575 register bits determine which connector in each pair owns the signal path.\n> \n> The driver does not account for this pairing in two places:\n> \n> ice_dpll_ufl_pin_state_set() modifies PCA9575 bits and disables the backing CGU pin without checking whether the U.FL pin is currently active. Disconnecting an already inactive U.FL pin flips bits that the \n> paired SMA pin relies on, breaking its connection.\n> \n> ice_dpll_sma_direction_set() does not propagate direction changes to the paired U.FL pin. For SMA2/U.FL2 the ICE_SMA2_UFL2_RX_DIS bit is never managed, so U.FL2 stays disconnected after SMA2 switches \n> to output. For both pairs the backing CGU pin of the U.FL side is never enabled when a direction change activates it, so userspace sees the pin as disconnected even though the routing is correct.\n> \n> Fix by guarding the U.FL disconnect path against inactive pins and by updating the paired U.FL pin fully on SMA direction changes: manage ICE_SMA2_UFL2_RX_DIS for the SMA2/U.FL2 pair and enable the \n> backing CGU pin whenever the peer becomes active.\n> \n> Fixes: 2dd5d03c77e2 (\"ice: redesign dpll sma/u.fl pins control\")\n> Signed-off-by: Petr Oros \n> ---\n> v2:\n> - fix ice_dpll_sma_direction_set() to manage ICE_SMA2_UFL2_RX_DIS\n> when SMA2 direction changes\n> - enable paired U.FL backing CGU pin when direction change makes\n> it active, so it reports as connected immediately\n> - (both reported by Intel test on the SMA init and notification\n> patch threads)\n> v1: https://lore.kernel.org/all/20260325151050.2081977-1-poros@redhat.com/\n> ---\n> drivers/net/ethernet/intel/ice/ice_dpll.c | 50 ++++++++++++++++++++++-\n> 1 file changed, 49 insertions(+), 1 deletion(-)\n\nTested-by: Alexander Nowlin ","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=R0y1fr3G;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=140.211.166.136; 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a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1777077999; x=1808613999;\n h=from:to:cc:subject:date:message-id:references:\n in-reply-to:content-transfer-encoding:mime-version;\n bh=nNNPulpGDXutWdaXSVtQkUTZthwqly6gqKXlM6316uk=;\n b=Cspjbx4WVjzjG1+/bvDy0hDkT2r/BoKCdrYsPI5Ti8RgI1U/CSK6hG+X\n XkQeN3Vxr5jedKF5oznI4srxn7fjTuqx84A2X7PtYpPiv72l2B1TANihQ\n IcJ4S0lyba68RnZNYolw6brfhyuEeidVwZ/pzajQ/cUW7cOtl0r5p+v7P\n wiQKo/XKlhtztlx5kaVJe2/WGI2rKDIgAHAvAw+qIfbjHzlKQLGxIBgCE\n BP1x+6SCyAlJy9H9t4xYXCQSCvbiUx/6jpgG600JVHSEUt2/w6w/UxyHa\n 7FH2vjP9Kjcu/f0AU3LaGx//g9yb3fZS8FmIDlWJl04jEF2UMJaZbEHHf\n w==;","X-Mailman-Original-Authentication-Results":["smtp2.osuosl.org;\n dmarc=pass (p=none dis=none)\n header.from=intel.com","smtp2.osuosl.org;\n dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com\n header.a=rsa-sha256 header.s=Intel header.b=Cspjbx4W","dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=intel.com;"],"Subject":"Re: [Intel-wired-lan] [PATCH iwl-net v2] ice: fix SMA and U.FL pin\n state changes affecting paired pin","X-BeenThere":"intel-wired-lan@osuosl.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Intel Wired Ethernet Linux Kernel Driver Development\n ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"intel-wired-lan-bounces@osuosl.org","Sender":"\"Intel-wired-lan\" "}},{"id":3682733,"web_url":"http://patchwork.ozlabs.org/comment/3682733/","msgid":"","list_archive_url":null,"date":"2026-04-27T14:14:33","subject":"Re: [Intel-wired-lan] [PATCH iwl-net v2] ice: fix SMA and U.FL pin\n state changes affecting paired pin","submitter":{"id":78857,"url":"http://patchwork.ozlabs.org/api/people/78857/","name":"Kubalewski, Arkadiusz","email":"arkadiusz.kubalewski@intel.com"},"content":">From: Petr Oros \n>Sent: Wednesday, April 8, 2026 1:05 PM\n>\n>SMA and U.FL pins share physical signal paths in pairs (SMA1/U.FL1 and\n>SMA2/U.FL2) controlled by the PCA9575 GPIO expander. Each pair can\n>only have one active pin at a time: SMA1 output and U.FL1 output share\n>the same CGU output, SMA2 input and U.FL2 input share the same CGU\n>input. The PCA9575 register bits determine which connector in each\n>pair owns the signal path.\n>\n>The driver does not account for this pairing in two places:\n>\n>ice_dpll_ufl_pin_state_set() modifies PCA9575 bits and disables the\n>backing CGU pin without checking whether the U.FL pin is currently\n>active. Disconnecting an already inactive U.FL pin flips bits that\n>the paired SMA pin relies on, breaking its connection.\n>\n>ice_dpll_sma_direction_set() does not propagate direction changes to\n>the paired U.FL pin. For SMA2/U.FL2 the ICE_SMA2_UFL2_RX_DIS bit is\n>never managed, so U.FL2 stays disconnected after SMA2 switches to\n>output. For both pairs the backing CGU pin of the U.FL side is never\n>enabled when a direction change activates it, so userspace sees the\n>pin as disconnected even though the routing is correct.\n>\n>Fix by guarding the U.FL disconnect path against inactive pins and by\n>updating the paired U.FL pin fully on SMA direction changes: manage\n>ICE_SMA2_UFL2_RX_DIS for the SMA2/U.FL2 pair and enable the backing\n>CGU pin whenever the peer becomes active.\n>\n>Fixes: 2dd5d03c77e2 (\"ice: redesign dpll sma/u.fl pins control\")\n\nLGTM,\n\nReviewed-by: Arkadiusz Kubalewski \n\n>Signed-off-by: Petr Oros \n>---\n>v2:\n> - fix ice_dpll_sma_direction_set() to manage ICE_SMA2_UFL2_RX_DIS\n> when SMA2 direction changes\n> - enable paired U.FL backing CGU pin when direction change makes\n> it active, so it reports as connected immediately\n> - (both reported by Intel test on the SMA init and notification\n> patch threads)\n>v1: https://lore.kernel.org/all/20260325151050.2081977-1-poros@redhat.com/\n>---\n> drivers/net/ethernet/intel/ice/ice_dpll.c | 50 ++++++++++++++++++++++-\n> 1 file changed, 49 insertions(+), 1 deletion(-)\n>\n>diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c\n>b/drivers/net/ethernet/intel/ice/ice_dpll.c\n>index 498ec2c045f384..3f8cd5b8298b57 100644\n>--- a/drivers/net/ethernet/intel/ice/ice_dpll.c\n>+++ b/drivers/net/ethernet/intel/ice/ice_dpll.c\n>@@ -1171,6 +1171,8 @@ static int ice_dpll_sma_direction_set(struct\n>ice_dpll_pin *p,\n> \t\t\t\t enum dpll_pin_direction direction,\n> \t\t\t\t struct netlink_ext_ack *extack)\n> {\n>+\tstruct ice_dplls *d = &p->pf->dplls;\n>+\tstruct ice_dpll_pin *peer;\n> \tu8 data;\n> \tint ret;\n>\n>@@ -1189,8 +1191,9 @@ static int ice_dpll_sma_direction_set(struct\n>ice_dpll_pin *p,\n> \tcase ICE_DPLL_PIN_SW_2_IDX:\n> \t\tif (direction == DPLL_PIN_DIRECTION_INPUT) {\n> \t\t\tdata &= ~ICE_SMA2_DIR_EN;\n>+\t\t\tdata |= ICE_SMA2_UFL2_RX_DIS;\n> \t\t} else {\n>-\t\t\tdata &= ~ICE_SMA2_TX_EN;\n>+\t\t\tdata &= ~(ICE_SMA2_TX_EN | ICE_SMA2_UFL2_RX_DIS);\n> \t\t\tdata |= ICE_SMA2_DIR_EN;\n> \t\t}\n> \t\tbreak;\n>@@ -1202,6 +1205,34 @@ static int ice_dpll_sma_direction_set(struct\n>ice_dpll_pin *p,\n> \t\tret = ice_dpll_pin_state_update(p->pf, p,\n> \t\t\t\t\t\tICE_DPLL_PIN_TYPE_SOFTWARE,\n> \t\t\t\t\t\textack);\n>+\tif (ret)\n>+\t\treturn ret;\n>+\n>+\t/* When a direction change activates the paired U.FL pin, enable\n>+\t * its backing CGU pin so the pin reports as connected. Without\n>+\t * this the U.FL routing is correct but the CGU pin stays disabled\n>+\t * and userspace sees the pin as disconnected. Do not disable the\n>+\t * backing pin when U.FL becomes inactive because the SMA pin may\n>+\t * still be using it.\n>+\t */\n>+\tpeer = &d->ufl[p->idx];\n>+\tif (peer->active) {\n>+\t\tstruct ice_dpll_pin *target;\n>+\t\tenum ice_dpll_pin_type type;\n>+\n>+\t\tif (peer->output) {\n>+\t\t\ttarget = peer->output;\n>+\t\t\ttype = ICE_DPLL_PIN_TYPE_OUTPUT;\n>+\t\t} else {\n>+\t\t\ttarget = peer->input;\n>+\t\t\ttype = ICE_DPLL_PIN_TYPE_INPUT;\n>+\t\t}\n>+\t\tret = ice_dpll_pin_enable(&p->pf->hw, target,\n>+\t\t\t\t\t d->eec.dpll_idx, type, extack);\n>+\t\tif (!ret)\n>+\t\t\tret = ice_dpll_pin_state_update(p->pf, target,\n>+\t\t\t\t\t\t\ttype, extack);\n>+\t}\n>\n> \treturn ret;\n> }\n>@@ -1253,6 +1284,14 @@ ice_dpll_ufl_pin_state_set(const struct dpll_pin\n>*pin, void *pin_priv,\n> \t\t\tdata &= ~ICE_SMA1_MASK;\n> \t\t\tenable = true;\n> \t\t} else if (state == DPLL_PIN_STATE_DISCONNECTED) {\n>+\t\t\t/* Skip if U.FL1 is not active, setting TX_EN\n>+\t\t\t * while DIR_EN is set would also deactivate\n>+\t\t\t * the paired SMA1 output.\n>+\t\t\t */\n>+\t\t\tif (data & (ICE_SMA1_DIR_EN | ICE_SMA1_TX_EN)) {\n>+\t\t\t\tret = 0;\n>+\t\t\t\tgoto unlock;\n>+\t\t\t}\n> \t\t\tdata |= ICE_SMA1_TX_EN;\n> \t\t\tenable = false;\n> \t\t} else {\n>@@ -1267,6 +1306,15 @@ ice_dpll_ufl_pin_state_set(const struct dpll_pin\n>*pin, void *pin_priv,\n> \t\t\tdata &= ~ICE_SMA2_UFL2_RX_DIS;\n> \t\t\tenable = true;\n> \t\t} else if (state == DPLL_PIN_STATE_DISCONNECTED) {\n>+\t\t\t/* Skip if U.FL2 is not active, setting\n>+\t\t\t * UFL2_RX_DIS could also disable the paired\n>+\t\t\t * SMA2 input.\n>+\t\t\t */\n>+\t\t\tif (!(data & ICE_SMA2_DIR_EN) ||\n>+\t\t\t (data & ICE_SMA2_UFL2_RX_DIS)) {\n>+\t\t\t\tret = 0;\n>+\t\t\t\tgoto unlock;\n>+\t\t\t}\n> \t\t\tdata |= ICE_SMA2_UFL2_RX_DIS;\n> \t\t\tenable = false;\n> \t\t} else {\n>--\n>2.52.0","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=Jp9XDuGf;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::136; 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a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1777299282; x=1808835282;\n h=from:to:cc:subject:date:message-id:references:\n in-reply-to:content-transfer-encoding:mime-version;\n bh=yeVyIkjNcc6BvEWbTVXnjky/MbhD7OYsevG8scQXC00=;\n b=JHHxI7Qa1h6JJjIxGlSCXILW9vwv04n691yakwu9qLLABzpl/Qgm6GND\n NLLKkqByUUSeb4/Rx/ql+CtkbeN1ZlCCxZf/tnE6+Jz5cy7upvJaBxjG6\n +NoQPOdgO8lNK+/vff6VyqfU/e2udg8hRgXnycOuGgoYRNBLseP9koF2I\n aFcGENCJa9qSTj42ocPl6Z1NGVxvcwSIHt1Bh3t+qGLRKv6kAQS6q4egF\n loFV0O4FErFkASsM3KBBwIdAouM8DXyKGjJxc+0aPPzKq/b1k0jp6mzFM\n 45T7kbfT3YW8A+GmocUBS5etquIdu/U0EI5HSrpJdnzUWgjuFioPkSiSy\n g==;","X-Mailman-Original-Authentication-Results":["smtp4.osuosl.org;\n dmarc=pass (p=none dis=none)\n header.from=intel.com","smtp4.osuosl.org;\n dkim=pass (2048-bit key,\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=JHHxI7Qa","dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=intel.com;"],"Subject":"Re: [Intel-wired-lan] [PATCH iwl-net v2] ice: fix SMA and U.FL pin\n state changes affecting paired pin","X-BeenThere":"intel-wired-lan@osuosl.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Intel Wired Ethernet Linux Kernel Driver Development\n ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Cc":"\"Kitszel, Przemyslaw\" ,\n Eric Dumazet ,\n \"linux-kernel@vger.kernel.org\" ,\n Andrew Lunn , \"Nguyen,\n Anthony L\" , Simon Horman ,\n \"intel-wired-lan@lists.osuosl.org\" , Jakub\n Kicinski , Paolo Abeni , \"David\n S. Miller\" ","Errors-To":"intel-wired-lan-bounces@osuosl.org","Sender":"\"Intel-wired-lan\" "}},{"id":3683209,"web_url":"http://patchwork.ozlabs.org/comment/3683209/","msgid":"","list_archive_url":null,"date":"2026-04-28T07:51:36","subject":"Re: [Intel-wired-lan] [PATCH iwl-net v2] ice: fix SMA and U.FL pin\n state changes affecting paired pin","submitter":{"id":75597,"url":"http://patchwork.ozlabs.org/api/people/75597/","name":"Loktionov, Aleksandr","email":"aleksandr.loktionov@intel.com"},"content":"> -----Original Message-----\n> From: Intel-wired-lan On Behalf\n> Of Petr Oros\n> Sent: Wednesday, April 8, 2026 1:05 PM\n> To: netdev@vger.kernel.org\n> Cc: Kitszel, Przemyslaw ; Eric Dumazet\n> ; Kubalewski, Arkadiusz\n> ; Andrew Lunn ;\n> Nguyen, Anthony L ; Simon Horman\n> ; intel-wired-lan@lists.osuosl.org; Jakub Kicinski\n> ; Paolo Abeni ; David S. Miller\n> ; linux-kernel@vger.kernel.org\n> Subject: [Intel-wired-lan] [PATCH iwl-net v2] ice: fix SMA and U.FL\n> pin state changes affecting paired pin\n> \n> SMA and U.FL pins share physical signal paths in pairs (SMA1/U.FL1 and\n> SMA2/U.FL2) controlled by the PCA9575 GPIO expander. Each pair can\n> only have one active pin at a time: SMA1 output and U.FL1 output share\n> the same CGU output, SMA2 input and U.FL2 input share the same CGU\n> input. The PCA9575 register bits determine which connector in each\n> pair owns the signal path.\n> \n> The driver does not account for this pairing in two places:\n> \n> ice_dpll_ufl_pin_state_set() modifies PCA9575 bits and disables the\n> backing CGU pin without checking whether the U.FL pin is currently\n> active. Disconnecting an already inactive U.FL pin flips bits that\n> the paired SMA pin relies on, breaking its connection.\n> \n> ice_dpll_sma_direction_set() does not propagate direction changes to\n> the paired U.FL pin. For SMA2/U.FL2 the ICE_SMA2_UFL2_RX_DIS bit is\n> never managed, so U.FL2 stays disconnected after SMA2 switches to\n> output. For both pairs the backing CGU pin of the U.FL side is never\n> enabled when a direction change activates it, so userspace sees the\n> pin as disconnected even though the routing is correct.\n> \n> Fix by guarding the U.FL disconnect path against inactive pins and by\n> updating the paired U.FL pin fully on SMA direction changes: manage\n> ICE_SMA2_UFL2_RX_DIS for the SMA2/U.FL2 pair and enable the backing\n> CGU pin whenever the peer becomes active.\n> \n> Fixes: 2dd5d03c77e2 (\"ice: redesign dpll sma/u.fl pins control\")\n> Signed-off-by: Petr Oros \n> ---\n> v2:\n> - fix ice_dpll_sma_direction_set() to manage ICE_SMA2_UFL2_RX_DIS\n> when SMA2 direction changes\n> - enable paired U.FL backing CGU pin when direction change makes\n> it active, so it reports as connected immediately\n> - (both reported by Intel test on the SMA init and notification\n> patch threads)\n> v1: https://lore.kernel.org/all/20260325151050.2081977-1-\n> poros@redhat.com/\n> ---\n> drivers/net/ethernet/intel/ice/ice_dpll.c | 50\n> ++++++++++++++++++++++-\n> 1 file changed, 49 insertions(+), 1 deletion(-)\n> \n> diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c\n> b/drivers/net/ethernet/intel/ice/ice_dpll.c\n> index 498ec2c045f384..3f8cd5b8298b57 100644\n> --- a/drivers/net/ethernet/intel/ice/ice_dpll.c\n> +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c\n> @@ -1171,6 +1171,8 @@ static int ice_dpll_sma_direction_set(struct\n> ice_dpll_pin *p,\n> \t\t\t\t enum dpll_pin_direction direction,\n> \t\t\t\t struct netlink_ext_ack *extack) {\n\n...\n\n> \t\t\tdata |= ICE_SMA2_UFL2_RX_DIS;\n> \t\t\tenable = false;\n> \t\t} else {\n> --\n> 2.52.0\n\n\nReviewed-by: Aleksandr Loktionov ","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=JdCwEHrx;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=140.211.166.137; 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