[{"id":3674617,"web_url":"http://patchwork.ozlabs.org/comment/3674617/","msgid":"","list_archive_url":null,"date":"2026-04-08T07:31:29","subject":"Re: [PATCH v2 3/4] gpio: realtek: Add driver for Realtek DHC RTD1625\n SoC","submitter":{"id":92191,"url":"http://patchwork.ozlabs.org/api/people/92191/","name":"Bartosz Golaszewski","email":"brgl@kernel.org"},"content":"On Wed, 8 Apr 2026 04:52:42 +0200, Yu-Chun Lin said:\n> From: Tzuyi Chang \n>\n> Add support for the GPIO controller found on Realtek DHC RTD1625 SoCs.\n>\n> Unlike the existing Realtek GPIO driver (drivers/gpio/gpio-rtd.c),\n> which manages pins via shared bank registers, the RTD1625 introduces\n> a per-pin register architecture. Each GPIO line now has its own\n> dedicated 32-bit control register to manage configuration independently,\n> including direction, output value, input value, interrupt enable, and\n> debounce. Therefore, this distinct hardware design requires a separate\n> driver.\n>\n> Reviewed-by: Linus Walleij \n> Signed-off-by: Tzuyi Chang \n> Signed-off-by: Yu-Chun Lin \n> ---\n> Changes in v2:\n> - Remove \"default y\".\n> - Add base_offset member to struct rtd1625_gpio_info to handle merged regions.\n> ---\n> drivers/gpio/Kconfig | 11 +\n> drivers/gpio/Makefile | 1 +\n> drivers/gpio/gpio-rtd1625.c | 584 ++++++++++++++++++++++++++++++++++++\n> 3 files changed, 596 insertions(+)\n> create mode 100644 drivers/gpio/gpio-rtd1625.c\n>\n> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig\n> index 5ee11a889867..281549ad72ac 100644\n> --- a/drivers/gpio/Kconfig\n> +++ b/drivers/gpio/Kconfig\n> @@ -638,6 +638,17 @@ config GPIO_RTD\n> \t Say yes here to support GPIO functionality and GPIO interrupt on\n> \t Realtek DHC SoCs.\n>\n> +config GPIO_RTD1625\n> +\ttristate \"Realtek DHC RTD1625 GPIO support\"\n> +\tdepends on ARCH_REALTEK || COMPILE_TEST\n> +\tselect GPIOLIB_IRQCHIP\n> +\thelp\n> +\t This option enables support for the GPIO controller on Realtek\n> +\t DHC (Digital Home Center) RTD1625 SoC.\n> +\n> +\t Say yes here to support both basic GPIO line functionality\n> +\t and GPIO interrupt handling capabilities for this platform.\n> +\n> config GPIO_SAMA5D2_PIOBU\n> \ttristate \"SAMA5D2 PIOBU GPIO support\"\n> \tdepends on MFD_SYSCON\n> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile\n> index c05f7d795c43..c95ba218d53a 100644\n> --- a/drivers/gpio/Makefile\n> +++ b/drivers/gpio/Makefile\n> @@ -159,6 +159,7 @@ obj-$(CONFIG_GPIO_REALTEK_OTTO)\t\t+= gpio-realtek-otto.o\n> obj-$(CONFIG_GPIO_REG)\t\t\t+= gpio-reg.o\n> obj-$(CONFIG_GPIO_ROCKCHIP)\t+= gpio-rockchip.o\n> obj-$(CONFIG_GPIO_RTD)\t\t\t+= gpio-rtd.o\n> +obj-$(CONFIG_GPIO_RTD1625)\t\t+= gpio-rtd1625.o\n> obj-$(CONFIG_ARCH_SA1100)\t\t+= gpio-sa1100.o\n> obj-$(CONFIG_GPIO_SAMA5D2_PIOBU)\t+= gpio-sama5d2-piobu.o\n> obj-$(CONFIG_GPIO_SCH311X)\t\t+= gpio-sch311x.o\n> diff --git a/drivers/gpio/gpio-rtd1625.c b/drivers/gpio/gpio-rtd1625.c\n> new file mode 100644\n> index 000000000000..bcc1bbb115fa\n> --- /dev/null\n> +++ b/drivers/gpio/gpio-rtd1625.c\n> @@ -0,0 +1,584 @@\n> +// SPDX-License-Identifier: GPL-2.0-or-later\n> +/*\n> + * Realtek DHC RTD1625 gpio driver\n> + *\n> + * Copyright (c) 2023 Realtek Semiconductor Corp.\n\nNo modifications since 2023?\n\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#define RTD1625_GPIO_DIR BIT(0)\n> +#define RTD1625_GPIO_OUT BIT(2)\n> +#define RTD1625_GPIO_IN BIT(4)\n> +#define RTD1625_GPIO_EDGE_INT_DP BIT(6)\n> +#define RTD1625_GPIO_EDGE_INT_EN BIT(8)\n> +#define RTD1625_GPIO_LEVEL_INT_EN BIT(16)\n> +#define RTD1625_GPIO_LEVEL_INT_DP BIT(18)\n> +#define RTD1625_GPIO_DEBOUNCE GENMASK(30, 28)\n> +#define RTD1625_GPIO_DEBOUNCE_WREN BIT(31)\n> +\n> +#define RTD1625_GPIO_WREN(x) ((x) << 1)\n> +\n> +/* Write-enable masks for all GPIO configs and reserved hardware bits */\n> +#define RTD1625_ISO_GPIO_WREN_ALL 0x8000aa8a\n> +#define RTD1625_ISOM_GPIO_WREN_ALL 0x800aaa8a\n> +\n> +#define RTD1625_GPIO_DEBOUNCE_1US 0\n> +#define RTD1625_GPIO_DEBOUNCE_10US 1\n> +#define RTD1625_GPIO_DEBOUNCE_100US 2\n> +#define RTD1625_GPIO_DEBOUNCE_1MS 3\n> +#define RTD1625_GPIO_DEBOUNCE_10MS 4\n> +#define RTD1625_GPIO_DEBOUNCE_20MS 5\n> +#define RTD1625_GPIO_DEBOUNCE_30MS 6\n> +#define RTD1625_GPIO_DEBOUNCE_50MS 7\n> +\n> +#define GPIO_CONTROL(gpio) ((gpio) * 4)\n> +\n> +/**\n> + * struct rtd1625_gpio_info - Specific GPIO register information\n> + * @num_gpios: The number of GPIOs\n> + * @irq_type_support: Supported IRQ types\n> + * @gpa_offset: Offset for GPIO assert interrupt status registers\n> + * @gpda_offset: Offset for GPIO deassert interrupt status registers\n> + * @level_offset: Offset of level interrupt status register\n> + * @write_en_all: Write-enable mask for all configurable bits\n> + */\n> +struct rtd1625_gpio_info {\n> +\tunsigned int\tnum_gpios;\n> +\tunsigned int\tirq_type_support;\n> +\tunsigned int\tbase_offset;\n> +\tunsigned int\tgpa_offset;\n> +\tunsigned int\tgpda_offset;\n> +\tunsigned int\tlevel_offset;\n> +\tunsigned int\twrite_en_all;\n> +};\n\nPlease remove the tabs in the above struct.\n\n> +\n> +struct rtd1625_gpio {\n> +\tstruct gpio_chip\t\tgpio_chip;\n> +\tconst struct rtd1625_gpio_info\t*info;\n> +\tvoid __iomem\t\t\t*base;\n> +\tvoid __iomem\t\t\t*irq_base;\n> +\tunsigned int\t\t\tirqs[3];\n> +\traw_spinlock_t\t\t\tlock;\n> +\tunsigned int\t\t\t*save_regs;\n> +};\n\nI'd also personally remove these tabs here but won't die on that hill.\n\n> +\n> +static unsigned int rtd1625_gpio_gpa_offset(struct rtd1625_gpio *data, unsigned int offset)\n> +{\n> +\treturn data->info->gpa_offset + ((offset / 32) * 4);\n> +}\n> +\n> +static unsigned int rtd1625_gpio_gpda_offset(struct rtd1625_gpio *data, unsigned int offset)\n> +{\n> +\treturn data->info->gpda_offset + ((offset / 32) * 4);\n> +}\n> +\n> +static unsigned int rtd1625_gpio_level_offset(struct rtd1625_gpio *data, unsigned int offset)\n> +{\n> +\treturn data->info->level_offset + ((offset / 32) * 4);\n> +}\n\nLooking at these, I'm under the impression that this driver could quite easily\nbe converted to using gpio-mmio or even gpio-regmap with an MMIO regmap, have\nyou looked into it by any chance?\n\nBart","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=V2dJR7dQ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n 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t=1775633492;\n\tbh=kTCKrQL00F1TtK9Lwc24qq0fGDc6kjFjWFKBMs3ppAI=;\n\th=From:In-Reply-To:References:Date:Subject:To:Cc:From;\n\tb=V2dJR7dQPnPRwc13ZdP55Rlj1GFe4mgJhxJ6yZkIcek7h8pamPD7FeqI+osD7Gp5g\n\t udUrN7iGrBo94H7sJ0AwHlqzA1+2K5bnTeRueNwXPWqzfoafJsManetQ2AsrB2rFCI\n\t Ju7gA52R+mngm/6yQFaGaWxyrrhLdMcVNz/YOuiN7lBAdhdwXpG75VuUoJOPco0p2U\n\t G93sboc+zXveOLyYEE4YHKc7VaJiKXudCCL8RQsmEfIq3YrO/VESiru8soc8HrUMwy\n\t aRHylJ3ZXNa4c+4UnszFw0qyR0plSc+XZWaJNeizU9XTmenBY1HmlTlYINhbLJE+sX\n\t dNbX8iZ3Ommog==","X-Gm-Message-State":"AOJu0YzfjQ0bdtYGhsevC8NRsggNx++HlStZs89ZEDvG7Q2LbQ5Ybcyg\n\tkdJEYChzHjx3XH1Xj16xo+EdBysOtp3I6OE0E6rHsvTHHduSsiomPz67PEJBJhgcZbif0KGK/Uh\n\tQaxonECJNy6V+7oOLpDCoxNUdymp1NfgZsiiUJG+lOA==","X-Received":"by 2002:a05:651c:154c:b0:38e:1714:b64e with SMTP id\n 38308e7fff4ca-38e1714bf45mr17377281fa.3.1775633490684; Wed, 08 Apr 2026\n 00:31:30 -0700 (PDT)","From":"Bartosz Golaszewski ","In-Reply-To":"<20260408025243.1155482-4-eleanor.lin@realtek.com>","Precedence":"bulk","X-Mailing-List":"linux-gpio@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","References":"<20260408025243.1155482-1-eleanor.lin@realtek.com>\n <20260408025243.1155482-4-eleanor.lin@realtek.com>","Date":"Wed, 8 Apr 2026 00:31:29 -0700","X-Gmail-Original-Message-ID":"\n ","X-Gm-Features":"AQROBzB5exLZ5SG0QSPEWBvRd7DGoi1G63K1Vi7bJ14rkJY_dk0S6b0kTI6vPfY","Message-ID":"\n ","Subject":"Re: [PATCH v2 3/4] gpio: realtek: Add driver for Realtek DHC RTD1625\n SoC","To":"Yu-Chun Lin ","Cc":"linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-realtek-soc@lists.infradead.org, cy.huang@realtek.com,\n\tstanley_chang@realtek.com, james.tai@realtek.com, linusw@kernel.org,\n\tbrgl@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,\n\tafaerber@suse.com, tychang@realtek.com","Content-Type":"text/plain; charset=\"UTF-8\""}},{"id":3675761,"web_url":"http://patchwork.ozlabs.org/comment/3675761/","msgid":"<52bf9ce2b7754af8af69b0afee0d07b2@realtek.com>","list_archive_url":null,"date":"2026-04-10T09:39:51","subject":"RE: [PATCH v2 3/4] gpio: realtek: Add driver for Realtek DHC RTD1625\n SoC","submitter":{"id":92797,"url":"http://patchwork.ozlabs.org/api/people/92797/","name":"Yu-Chun Lin [林祐君]","email":"eleanor.lin@realtek.com"},"content":"Hi Bart,\n\n> On Wed, 8 Apr 2026 04:52:42 +0200, Yu-Chun Lin \n> said:\n> > From: Tzuyi Chang \n> >\n> > Add support for the GPIO controller found on Realtek DHC RTD1625 SoCs.\n> >\n> > Unlike the existing Realtek GPIO driver (drivers/gpio/gpio-rtd.c),\n> > which manages pins via shared bank registers, the RTD1625 introduces a\n> > per-pin register architecture. Each GPIO line now has its own\n> > dedicated 32-bit control register to manage configuration\n> > independently, including direction, output value, input value,\n> > interrupt enable, and debounce. Therefore, this distinct hardware\n> > design requires a separate driver.\n> >\n> > Reviewed-by: Linus Walleij \n> > Signed-off-by: Tzuyi Chang \n> > Signed-off-by: Yu-Chun Lin \n> > ---\n> > Changes in v2:\n> > - Remove \"default y\".\n> > - Add base_offset member to struct rtd1625_gpio_info to handle merged\n> regions.\n> > ---\n> > drivers/gpio/Kconfig | 11 +\n> > drivers/gpio/Makefile | 1 +\n> > drivers/gpio/gpio-rtd1625.c | 584\n> > ++++++++++++++++++++++++++++++++++++\n> > 3 files changed, 596 insertions(+)\n> > create mode 100644 drivers/gpio/gpio-rtd1625.c\n> >\n> > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index\n> > 5ee11a889867..281549ad72ac 100644\n> > --- a/drivers/gpio/Kconfig\n> > +++ b/drivers/gpio/Kconfig\n> > @@ -638,6 +638,17 @@ config GPIO_RTD\n> > Say yes here to support GPIO functionality and GPIO interrupt on\n> > Realtek DHC SoCs.\n> >\n> > +config GPIO_RTD1625\n> > + tristate \"Realtek DHC RTD1625 GPIO support\"\n> > + depends on ARCH_REALTEK || COMPILE_TEST\n> > + select GPIOLIB_IRQCHIP\n> > + help\n> > + This option enables support for the GPIO controller on Realtek\n> > + DHC (Digital Home Center) RTD1625 SoC.\n> > +\n> > + Say yes here to support both basic GPIO line functionality\n> > + and GPIO interrupt handling capabilities for this platform.\n> > +\n> > config GPIO_SAMA5D2_PIOBU\n> > tristate \"SAMA5D2 PIOBU GPIO support\"\n> > depends on MFD_SYSCON\n> > diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index\n> > c05f7d795c43..c95ba218d53a 100644\n> > --- a/drivers/gpio/Makefile\n> > +++ b/drivers/gpio/Makefile\n> > @@ -159,6 +159,7 @@ obj-$(CONFIG_GPIO_REALTEK_OTTO)\n> += gpio-realtek-otto.o\n> > obj-$(CONFIG_GPIO_REG) += gpio-reg.o\n> > obj-$(CONFIG_GPIO_ROCKCHIP) += gpio-rockchip.o\n> > obj-$(CONFIG_GPIO_RTD) += gpio-rtd.o\n> > +obj-$(CONFIG_GPIO_RTD1625) += gpio-rtd1625.o\n> > obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o\n> > obj-$(CONFIG_GPIO_SAMA5D2_PIOBU) += gpio-sama5d2-piobu.o\n> > obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o\n> > diff --git a/drivers/gpio/gpio-rtd1625.c b/drivers/gpio/gpio-rtd1625.c\n> > new file mode 100644 index 000000000000..bcc1bbb115fa\n> > --- /dev/null\n> > +++ b/drivers/gpio/gpio-rtd1625.c\n> > @@ -0,0 +1,584 @@\n> > +// SPDX-License-Identifier: GPL-2.0-or-later\n> > +/*\n> > + * Realtek DHC RTD1625 gpio driver\n> > + *\n> > + * Copyright (c) 2023 Realtek Semiconductor Corp.\n> \n> No modifications since 2023?\n> \n\nWill include 2026.\n\n> > + */\n> > +\n> > +#include \n> > +#include \n> > +#include \n> > +#include \n> > +#include \n> > +#include #include \n> > +#include #include #include\n> > + #include #include\n> > +\n> > +\n> > +#define RTD1625_GPIO_DIR BIT(0)\n> > +#define RTD1625_GPIO_OUT BIT(2)\n> > +#define RTD1625_GPIO_IN BIT(4)\n> > +#define RTD1625_GPIO_EDGE_INT_DP BIT(6) #define\n> > +RTD1625_GPIO_EDGE_INT_EN BIT(8) #define\n> RTD1625_GPIO_LEVEL_INT_EN\n> > +BIT(16) #define RTD1625_GPIO_LEVEL_INT_DP BIT(18) #define\n> > +RTD1625_GPIO_DEBOUNCE GENMASK(30, 28) #define\n> > +RTD1625_GPIO_DEBOUNCE_WREN BIT(31)\n> > +\n> > +#define RTD1625_GPIO_WREN(x) ((x) << 1)\n> > +\n> > +/* Write-enable masks for all GPIO configs and reserved hardware bits\n> > +*/ #define RTD1625_ISO_GPIO_WREN_ALL 0x8000aa8a #define\n> > +RTD1625_ISOM_GPIO_WREN_ALL 0x800aaa8a\n> > +\n> > +#define RTD1625_GPIO_DEBOUNCE_1US 0\n> > +#define RTD1625_GPIO_DEBOUNCE_10US 1\n> > +#define RTD1625_GPIO_DEBOUNCE_100US 2 #define\n> > +RTD1625_GPIO_DEBOUNCE_1MS 3 #define\n> RTD1625_GPIO_DEBOUNCE_10MS 4\n> > +#define RTD1625_GPIO_DEBOUNCE_20MS 5 #define\n> > +RTD1625_GPIO_DEBOUNCE_30MS 6 #define\n> RTD1625_GPIO_DEBOUNCE_50MS 7\n> > +\n> > +#define GPIO_CONTROL(gpio) ((gpio) * 4)\n> > +\n> > +/**\n> > + * struct rtd1625_gpio_info - Specific GPIO register information\n> > + * @num_gpios: The number of GPIOs\n> > + * @irq_type_support: Supported IRQ types\n> > + * @gpa_offset: Offset for GPIO assert interrupt status registers\n> > + * @gpda_offset: Offset for GPIO deassert interrupt status registers\n> > + * @level_offset: Offset of level interrupt status register\n> > + * @write_en_all: Write-enable mask for all configurable bits */\n> > +struct rtd1625_gpio_info {\n> > + unsigned int num_gpios;\n> > + unsigned int irq_type_support;\n> > + unsigned int base_offset;\n> > + unsigned int gpa_offset;\n> > + unsigned int gpda_offset;\n> > + unsigned int level_offset;\n> > + unsigned int write_en_all;\n> > +};\n> \n> Please remove the tabs in the above struct.\n> \n\nAck.\n\n> > +\n> > +struct rtd1625_gpio {\n> > + struct gpio_chip gpio_chip;\n> > + const struct rtd1625_gpio_info *info;\n> > + void __iomem *base;\n> > + void __iomem *irq_base;\n> > + unsigned int irqs[3];\n> > + raw_spinlock_t lock;\n> > + unsigned int *save_regs;\n> > +};\n> \n> I'd also personally remove these tabs here but won't die on that hill.\n> \n\nAck.\n\n> > +\n> > +static unsigned int rtd1625_gpio_gpa_offset(struct rtd1625_gpio\n> > +*data, unsigned int offset) {\n> > + return data->info->gpa_offset + ((offset / 32) * 4); }\n> > +\n> > +static unsigned int rtd1625_gpio_gpda_offset(struct rtd1625_gpio\n> > +*data, unsigned int offset) {\n> > + return data->info->gpda_offset + ((offset / 32) * 4); }\n> > +\n> > +static unsigned int rtd1625_gpio_level_offset(struct rtd1625_gpio\n> > +*data, unsigned int offset) {\n> > + return data->info->level_offset + ((offset / 32) * 4); }\n> \n> Looking at these, I'm under the impression that this driver could quite easily be\n> converted to using gpio-mmio or even gpio-regmap with an MMIO regmap,\n> have you looked into it by any chance?\n> \n> Bart\n\n\nWe did look into gpio-mmio and gpio-regmap, but they are not quite suitable for\nour platform due to the specific hardware design:\n\n1. Per-GPIO Dedicated Registers: Unlike typical GPIO controllers that pack 32 pins\ninto a single 32-bit register (1 bit per pin), our hardware uses a dedicated 32-bit\nregister for each individual GPIO. This single register controls the\ninput/output state, direction, and interrupt trigger type for that specific pin.\n\n2. Write-Enable (WREN) Mask Mechanism: Our hardware requires a specific Write-Enable\nmask to be written simultaneously when updating the register values.\n\n3. Hardware Debounce: We also need to support hardware debounce settings per pin,\nwhich requires custom configuration via set_config mapped to these specific per-pin\nregisters.\n\nBecause of these hardware constraints, manually implementing the gpio_chip callbacks\nseems to be the most straightforward\n\nBest Regards,\nYu-Chun","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=realtek.com header.i=@realtek.com header.a=rsa-sha256\n header.s=dkim header.b=MaHrQpcP;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-gpio+bounces-34992-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com\n header.b=\"MaHrQpcP\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=211.75.126.72","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=realtek.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=realtek.com"],"Received":["from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fsX8z6vSDz1yGb\n\tfor ; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Precedence":"bulk","X-Mailing-List":"linux-gpio@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0"}},{"id":3679142,"web_url":"http://patchwork.ozlabs.org/comment/3679142/","msgid":"","list_archive_url":null,"date":"2026-04-19T21:19:40","subject":"Re: [PATCH v2 3/4] gpio: realtek: Add driver for Realtek DHC RTD1625\n SoC","submitter":{"id":92050,"url":"http://patchwork.ozlabs.org/api/people/92050/","name":"Linus Walleij","email":"linusw@kernel.org"},"content":"Hi Yu-Chun,\n\nOn Fri, Apr 10, 2026 at 11:39 AM Yu-Chun Lin [林祐君]\n wrote:\n\n> We did look into gpio-mmio and gpio-regmap, but they are not quite suitable for\n> our platform due to the specific hardware design:\n>\n> 1. Per-GPIO Dedicated Registers: Unlike typical GPIO controllers that pack 32 pins\n> into a single 32-bit register (1 bit per pin), our hardware uses a dedicated 32-bit\n> register for each individual GPIO. This single register controls the\n> input/output state, direction, and interrupt trigger type for that specific pin.\n\nIsn't that attainable by:\n\n- setting .ngpio_per_reg to 1 in struct gpio_regmap_config\n\n- extend .reg_mask_xlate callback with an enum for each operation\n (need to change all users of the .reg_mask_xlate callback but\n who cares, they are not many):\n\ne.g.\n\nenum gpio_regmap_operation {\n GPIO_REGMAP_GET_OP,\n GPIO_REGMAP_SET_OP,\n GPIO_REGMAP_SET_WITH_CLEAR_OP,\n GPIO_REGMAP_GET_DIR_OP,\n GPIO_REGMAP_SET_DIR_OP,\n};\n\n int (*reg_mask_xlate)(struct gpio_regmap *gpio,\n enum_gpio_regmap_operation op,\n unsigned int base,\n unsigned int offset, unsigned int *reg,\n unsigned int *mask);\n\nThis way .reg_mask_xlate() can hit different bits in the returned\n*mask depending on operation and it will be find to pack all of\nthe bits into one 32bit register.\n\nAdded Michael Walle to the the thread, he will know if this is a\ngood idea.\n\n> 2. Write-Enable (WREN) Mask Mechanism: Our hardware requires a specific Write-Enable\n> mask to be written simultaneously when updating the register values.\n\nWhich is to just set bit 31.\n\nWith the above scheme your .reg_mask_xlate callback can just set bit 31\nno matter what operating you're doing. Piece of cake.\n\n> 3. Hardware Debounce: We also need to support hardware debounce settings per pin,\n> which requires custom configuration via set_config mapped to these specific per-pin\n> registers.\n\nJust add a version of an optional .set_config() call to gpio-regmap.c\nto handle this using .reg_mask_xlate() per above and add a new\nGPIO_REGMAP_CONFIG_OP to the above enum, problem solved.\n\nIf it seems too hard I can write patch 1 & 2 adding this infrastructure\nbut I bet you can easily see what can be done with gpio-regmap.c\nhere provided Michael W approves the idea.\n\nYours,\nLinus Walleij","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=EBLgetj9;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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Sun, 19 Apr 2026\n 14:19:52 -0700 (PDT)","Precedence":"bulk","X-Mailing-List":"linux-gpio@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","References":"<20260408025243.1155482-1-eleanor.lin@realtek.com>\n <20260408025243.1155482-4-eleanor.lin@realtek.com>\n \n <52bf9ce2b7754af8af69b0afee0d07b2@realtek.com>","In-Reply-To":"<52bf9ce2b7754af8af69b0afee0d07b2@realtek.com>","From":"Linus Walleij ","Date":"Sun, 19 Apr 2026 23:19:40 +0200","X-Gmail-Original-Message-ID":"\n ","X-Gm-Features":"AQROBzAE2Y02h6LgmsVRXzFjBD7tYm8hngF_phTFw6dYL2PfXyxOmjtiC-kfPNE","Message-ID":"\n ","Subject":"Re: [PATCH v2 3/4] gpio: realtek: Add driver for Realtek DHC RTD1625\n SoC","To":"=?utf-8?b?WXUtQ2h1biBMaW4gW+ael+elkOWQm10=?= ,\n Michael Walle ","Cc":"Bartosz Golaszewski ,\n \"linux-gpio@vger.kernel.org\" ,\n \"devicetree@vger.kernel.org\" ,\n \"linux-kernel@vger.kernel.org\" ,\n \"linux-arm-kernel@lists.infradead.org\"\n ,\n \"linux-realtek-soc@lists.infradead.org\"\n , =?utf-8?b?Q1lfSHVhbmdb6buD6Ymm5pmP?=\n\t=?utf-8?b?XQ==?= , =?utf-8?b?U3RhbmxleSBDaGFuZ1vmmIw=?=\n\t=?utf-8?b?6IKy5b63XQ==?= , =?utf-8?b?SmFtZXMg?=\n\t=?utf-8?b?VGFpIFvmiLTlv5fls7Bd?= ,\n \"robh@kernel.org\" ,\n \"krzk+dt@kernel.org\" ,\n \"conor+dt@kernel.org\" ,\n \"afaerber@suse.com\" , =?utf-8?b?VFlfQ2hhbmdb5by15a2Q6YC4?=\n\t=?utf-8?b?XQ==?= ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable"}},{"id":3679261,"web_url":"http://patchwork.ozlabs.org/comment/3679261/","msgid":"","list_archive_url":null,"date":"2026-04-20T07:22:13","subject":"Re: [PATCH v2 3/4] gpio: realtek: Add driver for Realtek DHC\n RTD1625 SoC","submitter":{"id":86646,"url":"http://patchwork.ozlabs.org/api/people/86646/","name":"Michael Walle","email":"mwalle@kernel.org"},"content":"Hi,\n\nOn Sun Apr 19, 2026 at 11:19 PM CEST, Linus Walleij wrote:\n> Hi Yu-Chun,\n>\n> On Fri, Apr 10, 2026 at 11:39 AM Yu-Chun Lin [林祐君]\n> wrote:\n>\n>> We did look into gpio-mmio and gpio-regmap, but they are not quite suitable for\n>> our platform due to the specific hardware design:\n>>\n>> 1. Per-GPIO Dedicated Registers: Unlike typical GPIO controllers that pack 32 pins\n>> into a single 32-bit register (1 bit per pin), our hardware uses a dedicated 32-bit\n>> register for each individual GPIO. This single register controls the\n>> input/output state, direction, and interrupt trigger type for that specific pin.\n>\n> Isn't that attainable by:\n>\n> - setting .ngpio_per_reg to 1 in struct gpio_regmap_config\n\nWhich is just used by the gpio_regmap_simple_xlate() anyway. So it\ndoesn't really matter. But yeah, 1 would be the correct value here,\nassuming that the registers are consecutive.\n\n> - extend .reg_mask_xlate callback with an enum for each operation\n> (need to change all users of the .reg_mask_xlate callback but\n> who cares, they are not many):\n>\n> e.g.\n>\n> enum gpio_regmap_operation {\n> GPIO_REGMAP_GET_OP,\n> GPIO_REGMAP_SET_OP,\n> GPIO_REGMAP_SET_WITH_CLEAR_OP,\n> GPIO_REGMAP_GET_DIR_OP,\n> GPIO_REGMAP_SET_DIR_OP,\n> };\n>\n> int (*reg_mask_xlate)(struct gpio_regmap *gpio,\n> enum_gpio_regmap_operation op,\n> unsigned int base,\n> unsigned int offset, unsigned int *reg,\n> unsigned int *mask);\n>\n> This way .reg_mask_xlate() can hit different bits in the returned\n> *mask depending on operation and it will be find to pack all of\n> the bits into one 32bit register.\n>\n> Added Michael Walle to the the thread, he will know if this is a\n> good idea.\n\nNice idea, though the information is then redundant in the usual\ncase, i.e. drivers which need to translate specific registers\nwill do a \"switch (base)\" at the moment. These should be converted\nto \"switch (op)\" just to keep all the drivers aligned and prevent\nnew drivers from using the old method. You'd need to touch them\nanyway.\n\nI was briefly thinking about making it somewhat possible to embed\nthe op into the base, if it would otherwise be all the same. That\nway, you could gpio-regmap as is. A special case like\nGPIO_REGMAP_ADDR_ZERO, that could be used by these kind of drivers,\nbut that is probably too hacky.\n\nI'm fine with either way.\n\n>> 2. Write-Enable (WREN) Mask Mechanism: Our hardware requires a specific Write-Enable\n>> mask to be written simultaneously when updating the register values.\n>\n> Which is to just set bit 31.\n>\n> With the above scheme your .reg_mask_xlate callback can just set bit 31\n> no matter what operating you're doing. Piece of cake.\n\nKeep in mind, that this will make reading and writing somewhat\ndifferent. reading assumes there is only one bit set in mask,\nbecause of the \"!!(val & mask)\" op, which is hardcoded. I'm not\nagainst using the write like that though.\n\n-michael\n\n>> 3. Hardware Debounce: We also need to support hardware debounce settings per pin,\n>> which requires custom configuration via set_config mapped to these specific per-pin\n>> registers.\n>\n> Just add a version of an optional .set_config() call to gpio-regmap.c\n> to handle this using .reg_mask_xlate() per above and add a new\n> GPIO_REGMAP_CONFIG_OP to the above enum, problem solved.\n>\n> If it seems too hard I can write patch 1 & 2 adding this infrastructure\n> but I bet you can easily see what can be done with gpio-regmap.c\n> here provided Michael W approves the idea.\n>\n> Yours,\n> Linus Walleij","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=IMey3crY;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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protocol=\"application/pgp-signature\"","Date":"Mon, 20 Apr 2026 09:22:13 +0200","Message-Id":"","Subject":"Re: [PATCH v2 3/4] gpio: realtek: Add driver for Realtek DHC\n RTD1625 SoC","Cc":"\"Bartosz Golaszewski\" ,\n \"linux-gpio@vger.kernel.org\" ,\n \"devicetree@vger.kernel.org\" ,\n \"linux-kernel@vger.kernel.org\" ,\n \"linux-arm-kernel@lists.infradead.org\"\n ,\n \"linux-realtek-soc@lists.infradead.org\"\n , =?utf-8?b?Q1lfSHVhbmdb6buD6Ymm5pmP?=\n\t=?utf-8?b?XQ==?= , =?utf-8?b?U3RhbmxleSBDaGFuZ1vmmIw=?=\n\t=?utf-8?b?6IKy5b63XQ==?= , =?utf-8?b?SmFtZXMg?=\n\t=?utf-8?b?VGFpIFvmiLTlv5fls7Bd?= ,\n \"robh@kernel.org\" ,\n \"krzk+dt@kernel.org\" ,\n \"conor+dt@kernel.org\" ,\n \"afaerber@suse.com\" , =?utf-8?b?VFlfQ2hhbmdb5by15a2Q6YC4?=\n\t=?utf-8?b?XQ==?= ","From":"\"Michael Walle\" ","To":"\"Linus Walleij\" , =?utf-8?b?WXUtQ2h1biBMaW4gW+aelw==?=\n\t=?utf-8?b?56WQ5ZCbXQ==?= ","X-Mailer":"aerc 0.20.0","References":"<20260408025243.1155482-1-eleanor.lin@realtek.com>\n <20260408025243.1155482-4-eleanor.lin@realtek.com>\n \n <52bf9ce2b7754af8af69b0afee0d07b2@realtek.com>\n ","In-Reply-To":"\n "}}]