[{"id":3674885,"web_url":"http://patchwork.ozlabs.org/comment/3674885/","msgid":"<7ccbc31f-b3ce-49a4-80e7-e052f517f0e1@linaro.org>","list_archive_url":null,"date":"2026-04-07T22:27:14","subject":"Re: [PATCH v10 15/21] target/arm/tcg/translate.c: replace TCGv with\n TCGv_va","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/8/26 08:20, Pierrick Bouvier wrote:\n> On 4/7/26 2:02 PM, Philippe Mathieu-Daudé wrote:\n>> On 7/4/26 21:59, Pierrick Bouvier wrote:\n>>> We know this file is for 32-bit runtime target, so we can set\n>>> TCG_ADDRESS_BITS. TCG_TYPE_VA is derived accordingly and is already\n>>> passed to translator_loop.\n>>>\n>>> Reviewed-by: Richard Henderson \n>>> Signed-off-by: Pierrick Bouvier \n>>> ---\n>>>    target/arm/tcg/translate.c | 29 +++++++++++++++--------------\n>>>    1 file changed, 15 insertions(+), 14 deletions(-)\n>>>\n>>> diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\n>>> index fa4c7907dcd..0b3b4ab86be 100644\n>>> --- a/target/arm/tcg/translate.c\n>>> +++ b/target/arm/tcg/translate.c\n>>> @@ -22,7 +22,8 @@\n>>>    #include \"translate.h\"\n>>>    #include \"translate-a32.h\"\n>>> -#include \"tcg/tcg-op.h\"\n>>> +#define TCG_ADDRESS_BITS 32\n>>> +#include \"tcg/tcg-op-mem.h\"\n>>>    #include \"qemu/log.h\"\n>>>    #include \"arm_ldst.h\"\n>>>    #include \"semihosting/semihost.h\"\n>>> @@ -910,14 +911,14 @@ MemOp pow2_align(unsigned i)\n>>>     * that the address argument is TCGv_i32 rather than TCGv.\n>>>     */\n>>> -static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)\n>>> +static TCGv_va gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)\n>>>    {\n>>> -    TCGv addr = tcg_temp_new();\n>>> -    tcg_gen_extu_i32_tl(addr, a32);\n>>> +    TCGv_va addr = tcgv_va_temp_new();\n>>> +    tcg_gen_mov_i32(addr, a32);\n>>\n>> The implicit TCGv_va -> TCGv_i32 bugs me here, but the overall change\n>> will make my sleep better :) So:\n>>\n> \n> We could use TCGv_i32 directly, TCGv_va is just useful here to document the intention. I \n> can update this if Richard and you prefer this.\n\nI think this is fine, as I'm not keen on introducing a complete set of tcg_gen_foo_va \nmacros. As is, any mismatch will be caught at compile-time.\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=aETcWrLl;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (unknown [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frWss6P0Gz1xy1\n\tfor ; Thu, 09 Apr 2026 04:33:37 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wAXhf-0001PI-Eu; Wed, 08 Apr 2026 14:32:39 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wAXhc-0000z9-B0\n for qemu-devel@nongnu.org; Wed, 08 Apr 2026 14:32:36 -0400","from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wAEtI-0002EC-Cx\n for qemu-devel@nongnu.org; Tue, 07 Apr 2026 18:27:26 -0400","by mail-pj1-x102d.google.com with SMTP id\n 98e67ed59e1d1-35d94f4ee36so3196787a91.3\n for ; Tue, 07 Apr 2026 15:27:22 -0700 (PDT)","from [192.168.1.105] (124-150-69-109.tpgi.com.au. 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TCG_TYPE_VA is derived accordingly and is already\n>> passed to translator_loop.\n>>\n>> Reviewed-by: Richard Henderson \n>> Signed-off-by: Pierrick Bouvier \n>> ---\n>> target/arm/tcg/translate.c | 29 +++++++++++++++--------------\n>> 1 file changed, 15 insertions(+), 14 deletions(-)\n>>\n>> diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\n>> index fa4c7907dcd..0b3b4ab86be 100644\n>> --- a/target/arm/tcg/translate.c\n>> +++ b/target/arm/tcg/translate.c\n>> @@ -22,7 +22,8 @@\n>> \n>> #include \"translate.h\"\n>> #include \"translate-a32.h\"\n>> -#include \"tcg/tcg-op.h\"\n>> +#define TCG_ADDRESS_BITS 32\n>> +#include \"tcg/tcg-op-mem.h\"\n>> #include \"qemu/log.h\"\n>> #include \"arm_ldst.h\"\n>> #include \"semihosting/semihost.h\"\n>> @@ -910,14 +911,14 @@ MemOp pow2_align(unsigned i)\n>> * that the address argument is TCGv_i32 rather than TCGv.\n>> */\n>> \n>> -static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)\n>> +static TCGv_va gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)\n>> {\n>> - TCGv addr = tcg_temp_new();\n>> - tcg_gen_extu_i32_tl(addr, a32);\n>> + TCGv_va addr = tcgv_va_temp_new();\n>> + tcg_gen_mov_i32(addr, a32);\n> \n> The implicit TCGv_va -> TCGv_i32 bugs me here, but the overall change\n> will make my sleep better :) So:\n>\n\nWe could use TCGv_i32 directly, TCGv_va is just useful here to document \nthe intention. I can update this if Richard and you prefer this.\n\n> Reviewed-by: Philippe Mathieu-Daudé \n> \n>> \n>> /* Not needed for user-mode BE32, where we use MO_BE instead. */\n>> if (!IS_USER_ONLY && s->sctlr_b && (op & MO_SIZE) < MO_32) {\n>> - tcg_gen_xori_tl(addr, addr, 4 - (1 << (op & MO_SIZE)));\n>> + tcg_gen_xori_i32(addr, addr, 4 - (1 << (op & MO_SIZE)));\n>> }\n>> return addr;\n>> }\n>> @@ -929,21 +930,21 @@ static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)\n>> void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val,\n>> TCGv_i32 a32, int index, MemOp opc)\n>> {\n>> - TCGv addr = gen_aa32_addr(s, a32, opc);\n>> + TCGv_va addr = gen_aa32_addr(s, a32, opc);\n>> tcg_gen_qemu_ld_i32(val, addr, index, opc);\n>> }\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=hWkXDlEG;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::1029;\n envelope-from=pierrick.bouvier@linaro.org; helo=mail-pj1-x1029.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3674897,"web_url":"http://patchwork.ozlabs.org/comment/3674897/","msgid":"","list_archive_url":null,"date":"2026-04-07T21:02:17","subject":"Re: [PATCH v10 15/21] target/arm/tcg/translate.c: replace TCGv with\n TCGv_va","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"content":"On 7/4/26 21:59, Pierrick Bouvier wrote:\n> We know this file is for 32-bit runtime target, so we can set\n> TCG_ADDRESS_BITS. TCG_TYPE_VA is derived accordingly and is already\n> passed to translator_loop.\n> \n> Reviewed-by: Richard Henderson \n> Signed-off-by: Pierrick Bouvier \n> ---\n> target/arm/tcg/translate.c | 29 +++++++++++++++--------------\n> 1 file changed, 15 insertions(+), 14 deletions(-)\n> \n> diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\n> index fa4c7907dcd..0b3b4ab86be 100644\n> --- a/target/arm/tcg/translate.c\n> +++ b/target/arm/tcg/translate.c\n> @@ -22,7 +22,8 @@\n> \n> #include \"translate.h\"\n> #include \"translate-a32.h\"\n> -#include \"tcg/tcg-op.h\"\n> +#define TCG_ADDRESS_BITS 32\n> +#include \"tcg/tcg-op-mem.h\"\n> #include \"qemu/log.h\"\n> #include \"arm_ldst.h\"\n> #include \"semihosting/semihost.h\"\n> @@ -910,14 +911,14 @@ MemOp pow2_align(unsigned i)\n> * that the address argument is TCGv_i32 rather than TCGv.\n> */\n> \n> -static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)\n> +static TCGv_va gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)\n> {\n> - TCGv addr = tcg_temp_new();\n> - tcg_gen_extu_i32_tl(addr, a32);\n> + TCGv_va addr = tcgv_va_temp_new();\n> + tcg_gen_mov_i32(addr, a32);\n\nThe implicit TCGv_va -> TCGv_i32 bugs me here, but the overall change\nwill make my sleep better :) So:\n\nReviewed-by: Philippe Mathieu-Daudé \n\n> \n> /* Not needed for user-mode BE32, where we use MO_BE instead. */\n> if (!IS_USER_ONLY && s->sctlr_b && (op & MO_SIZE) < MO_32) {\n> - tcg_gen_xori_tl(addr, addr, 4 - (1 << (op & MO_SIZE)));\n> + tcg_gen_xori_i32(addr, addr, 4 - (1 << (op & MO_SIZE)));\n> }\n> return addr;\n> }\n> @@ -929,21 +930,21 @@ static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)\n> void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val,\n> TCGv_i32 a32, int index, MemOp opc)\n> {\n> - TCGv addr = gen_aa32_addr(s, a32, opc);\n> + TCGv_va addr = gen_aa32_addr(s, a32, opc);\n> tcg_gen_qemu_ld_i32(val, addr, index, opc);\n> }","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=KAL9F4C1;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::32e;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3674966,"web_url":"http://patchwork.ozlabs.org/comment/3674966/","msgid":"<6ff0ba9a-fa63-45e1-bd98-61f53125037d@linaro.org>","list_archive_url":null,"date":"2026-04-07T22:34:23","subject":"Re: [PATCH v10 15/21] target/arm/tcg/translate.c: replace TCGv with\n TCGv_va","submitter":{"id":85798,"url":"http://patchwork.ozlabs.org/api/people/85798/","name":"Pierrick Bouvier","email":"pierrick.bouvier@linaro.org"},"content":"On 4/7/26 3:27 PM, Richard Henderson wrote:\n> On 4/8/26 08:20, Pierrick Bouvier wrote:\n>> On 4/7/26 2:02 PM, Philippe Mathieu-Daudé wrote:\n>>> On 7/4/26 21:59, Pierrick Bouvier wrote:\n>>>> We know this file is for 32-bit runtime target, so we can set\n>>>> TCG_ADDRESS_BITS. TCG_TYPE_VA is derived accordingly and is already\n>>>> passed to translator_loop.\n>>>>\n>>>> Reviewed-by: Richard Henderson \n>>>> Signed-off-by: Pierrick Bouvier \n>>>> ---\n>>>>    target/arm/tcg/translate.c | 29 +++++++++++++++--------------\n>>>>    1 file changed, 15 insertions(+), 14 deletions(-)\n>>>>\n>>>> diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\n>>>> index fa4c7907dcd..0b3b4ab86be 100644\n>>>> --- a/target/arm/tcg/translate.c\n>>>> +++ b/target/arm/tcg/translate.c\n>>>> @@ -22,7 +22,8 @@\n>>>>    #include \"translate.h\"\n>>>>    #include \"translate-a32.h\"\n>>>> -#include \"tcg/tcg-op.h\"\n>>>> +#define TCG_ADDRESS_BITS 32\n>>>> +#include \"tcg/tcg-op-mem.h\"\n>>>>    #include \"qemu/log.h\"\n>>>>    #include \"arm_ldst.h\"\n>>>>    #include \"semihosting/semihost.h\"\n>>>> @@ -910,14 +911,14 @@ MemOp pow2_align(unsigned i)\n>>>>     * that the address argument is TCGv_i32 rather than TCGv.\n>>>>     */\n>>>> -static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)\n>>>> +static TCGv_va gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)\n>>>>    {\n>>>> -    TCGv addr = tcg_temp_new();\n>>>> -    tcg_gen_extu_i32_tl(addr, a32);\n>>>> +    TCGv_va addr = tcgv_va_temp_new();\n>>>> +    tcg_gen_mov_i32(addr, a32);\n>>>\n>>> The implicit TCGv_va -> TCGv_i32 bugs me here, but the overall change\n>>> will make my sleep better :) So:\n>>>\n>>\n>> We could use TCGv_i32 directly, TCGv_va is just useful here to document the intention. I\n>> can update this if Richard and you prefer this.\n> \n> I think this is fine, as I'm not keen on introducing a complete set of tcg_gen_foo_va\n> macros. As is, any mismatch will be caught at compile-time.\n>\n\nAgreed. Usage should be reduced to address related functions.\n\n> \n> r~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=JOg+/e3B;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frYd932Fwz1yD3\n\tfor ; Thu, 09 Apr 2026 05:52:44 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wAYcI-0005uz-Gc; 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