[{"id":3674886,"web_url":"http://patchwork.ozlabs.org/comment/3674886/","msgid":"","list_archive_url":null,"date":"2026-04-08T02:51:06","subject":"Re: [PATCH 5/5] target/riscv: Use ELEN for Fractional LMUL check","submitter":{"id":92265,"url":"http://patchwork.ozlabs.org/api/people/92265/","name":"Chao Liu","email":"chao.liu.zevorn@gmail.com"},"content":"On Tue, Apr 07, 2026 at 02:36:14PM +1000, alistair23@gmail.com wrote:\n> From: Alistair Francis \n> \n> The RISC-V spec states that\n> \n> \"\"\"\n> For a given supported fractional LMUL setting, implementations\n> must support SEW settings between SEWMIN and LMUL * ELEN, inclusive.\n> \"\"\"\n> \n> We were previously checking VLEN, instead of ELEN, so let's update to\n> check ELEN instead of VLEN for fractional scaling.\n> \n> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3196\n> Signed-off-by: Alistair Francis \nReviewed-by: Chao Liu \n\nThanks,\nChao\n> ---\n> target/riscv/vector_helper.c | 9 ++++-----\n> 1 file changed, 4 insertions(+), 5 deletions(-)\n> \n> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c\n> index 83dd26314d..b4fc791eb7 100644\n> --- a/target/riscv/vector_helper.c\n> +++ b/target/riscv/vector_helper.c\n> @@ -47,18 +47,17 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,\n> target_ulong reserved = s2 &\n> MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,\n> xlen - 1 - R_VTYPE_RESERVED_SHIFT);\n> - uint16_t vlen = cpu->cfg.vlenb << 3;\n> int8_t lmul;\n> \n> if (vlmul & 4) {\n> /*\n> * Fractional LMUL, check:\n> *\n> - * VLEN * LMUL >= SEW\n> - * VLEN >> (8 - lmul) >= sew\n> - * (vlenb << 3) >> (8 - lmul) >= sew\n> + * ELEN * LMUL >= SEW\n> + * ELEN >> (8 - vlmul) >= sew\n> */\n> - if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {\n> + if (vlmul == 4 ||\n> + (cpu->cfg.elen >> (8 - vlmul)) < sew) {\n> vill = true;\n> }\n> }\n> -- \n> 2.53.0\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=IjQSpnic;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20260407043614.372871-6-alistair.francis@wdc.com>","Received-SPF":"pass client-ip=2607:f8b0:4864:20::f43;\n envelope-from=chao.liu.zevorn@gmail.com; helo=mail-qv1-xf43.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3675082,"web_url":"http://patchwork.ozlabs.org/comment/3675082/","msgid":"","list_archive_url":null,"date":"2026-04-09T05:32:44","subject":"Re: [PATCH 5/5] target/riscv: Use ELEN for Fractional LMUL check","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Tue, Apr 7, 2026 at 10:13 PM LIU Zhiwei wrote:\n>\n> Hi Alistair,\n>\n> On 4/7/26 12:36 PM, alistair23@gmail.com wrote:\n>\n> From: Alistair Francis \n>\n> The RISC-V spec states that\n>\n> \"\"\"\n> For a given supported fractional LMUL setting, implementations\n> must support SEW settings between SEWMIN and LMUL * ELEN, inclusive.\n> \"\"\"\n>\n> I think the meaning of \"must support\" in specification is \"must at least support\" instead of \"must only support\".\n\nGood point, I didn't really think about that.\n\n>\n> Sail or Spike have the same check as this patch to prevent user program can run on them, but\n> can't run on RTLs, as RTLs implementation may support SEW besides the SEWMIN and LMUL * ELEN range.\n>\n> We can refer to discussion here: https://github.com/riscv-software-src/riscv-isa-sim/pull/620\n\nI think this is still the right fix, as it seems like it's unlikely\nthere will be implementations that expect outside that minimum support\nto work, see https://github.com/riscv/riscv-isa-manual/issues/2359#issuecomment-3458627615\nfor example.\n\n>\n> In my opinion, we had better add a option such as \"frac_sew_check\" to make user set right value for their RTL implementation.\n\nIn future if there are implementations that want extra support that we\ncan add a property. Right now I suspect there isn't any software that\nexpects it to work, so it probably isn't an issue and will help catch\nfaulty implementations.\n\nAlistair\n\n>\n> Otherwise,\n> Reviewed-by: LIU Zhiwei \n>\n> Thanks,\n> Zhiwei\n>\n> We were previously checking VLEN, instead of ELEN, so let's update to\n> check ELEN instead of VLEN for fractional scaling.\n>\n> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3196\n> Signed-off-by: Alistair Francis \n> ---\n> target/riscv/vector_helper.c | 9 ++++-----\n> 1 file changed, 4 insertions(+), 5 deletions(-)\n>\n> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c\n> index 83dd26314d..b4fc791eb7 100644\n> --- a/target/riscv/vector_helper.c\n> +++ b/target/riscv/vector_helper.c\n> @@ -47,18 +47,17 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,\n> target_ulong reserved = s2 &\n> MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,\n> xlen - 1 - R_VTYPE_RESERVED_SHIFT);\n> - uint16_t vlen = cpu->cfg.vlenb << 3;\n> int8_t lmul;\n>\n> if (vlmul & 4) {\n> /*\n> * Fractional LMUL, check:\n> *\n> - * VLEN * LMUL >= SEW\n> - * VLEN >> (8 - lmul) >= sew\n> - * (vlenb << 3) >> (8 - lmul) >= sew\n> + * ELEN * LMUL >= SEW\n> + * ELEN >> (8 - vlmul) >= sew\n> */\n> - if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {\n> + if (vlmul == 4 ||\n> + (cpu->cfg.elen >> (8 - vlmul)) < sew) {\n> vill = true;\n> }\n> }","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=da80+o7N;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Wed, 08 Apr 2026\n 22:33:10 -0700 (PDT)","MIME-Version":"1.0","References":"<20260407043614.372871-1-alistair.francis@wdc.com>\n <20260407043614.372871-6-alistair.francis@wdc.com>\n ","In-Reply-To":"","From":"Alistair Francis ","Date":"Thu, 9 Apr 2026 15:32:44 +1000","X-Gm-Features":"AQROBzA4ld6oI-3VJgKwhPQdeKKqUMkyO45kO2U3Vfm8inbv8J-vwxdXmuMKgoI","Message-ID":"\n ","Subject":"Re: [PATCH 5/5] target/riscv: Use ELEN for Fractional LMUL check","To":"LIU Zhiwei ","Cc":"palmer@dabbelt.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com,\n chao.liu.zevorn@gmail.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org,\n Alistair Francis ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Received-SPF":"pass client-ip=2a00:1450:4864:20::632;\n envelope-from=alistair23@gmail.com; helo=mail-ej1-x632.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3675089,"web_url":"http://patchwork.ozlabs.org/comment/3675089/","msgid":"<0fc9dde4-16a3-425f-9e51-38e892c34008@linux.alibaba.com>","list_archive_url":null,"date":"2026-04-09T06:05:36","subject":"Re: [PATCH 5/5] target/riscv: Use ELEN for Fractional LMUL check","submitter":{"id":84720,"url":"http://patchwork.ozlabs.org/api/people/84720/","name":"LIU Zhiwei","email":"zhiwei_liu@linux.alibaba.com"},"content":"On 4/9/26 1:32 PM, Alistair Francis wrote:\n> On Tue, Apr 7, 2026 at 10:13 PM LIU Zhiwei wrote:\n>> Hi Alistair,\n>>\n>> On 4/7/26 12:36 PM, alistair23@gmail.com wrote:\n>>\n>> From: Alistair Francis \n>>\n>> The RISC-V spec states that\n>>\n>> \"\"\"\n>> For a given supported fractional LMUL setting, implementations\n>> must support SEW settings between SEWMIN and LMUL * ELEN, inclusive.\n>> \"\"\"\n>>\n>> I think the meaning of \"must support\" in specification is \"must at least support\" instead of \"must only support\".\n> Good point, I didn't really think about that.\n>\n>> Sail or Spike have the same check as this patch to prevent user program can run on them, but\n>> can't run on RTLs, as RTLs implementation may support SEW besides the SEWMIN and LMUL * ELEN range.\n>>\n>> We can refer to discussion here: https://github.com/riscv-software-src/riscv-isa-sim/pull/620\n> I think this is still the right fix, as it seems like it's unlikely\n> there will be implementations that expect outside that minimum support\n> to work, see https://github.com/riscv/riscv-isa-manual/issues/2359#issuecomment-3458627615\n> for example.\nMake sense.\n>\n>> In my opinion, we had better add a option such as \"frac_sew_check\" to make user set right value for their RTL implementation.\n> In future if there are implementations that want extra support that we\n> can add a property.\nAgree.\n> Right now I suspect there isn't any software that\n> expects it to work, so it probably isn't an issue and will help catch\n> faulty implementations.\n\nSome RTLs can issue more vector instructions one cycle when lmul = 1/2 \nthan lmul = 1. It is useful for some workloads, such as H264, which \ntypical calculation unit is 128 bit.\nIf vlen is 256bit, software can set lmul to 1/2 (64bit sew is allowed by \nspecification, but forbidden by this patch) to issue more vector \ninstructions one cycle for this type workload.\n\nStandard software should use this feature by vsetvl and vill detection.  \nSo it should also work with this patch.\n\nThanks,\nZhiwei\n\n>\n> Alistair\n>\n>> Otherwise,\n>> Reviewed-by: LIU Zhiwei \n>>\n>> Thanks,\n>> Zhiwei\n>>\n>> We were previously checking VLEN, instead of ELEN, so let's update to\n>> check ELEN instead of VLEN for fractional scaling.\n>>\n>> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3196\n>> Signed-off-by: Alistair Francis \n>> ---\n>> target/riscv/vector_helper.c | 9 ++++-----\n>> 1 file changed, 4 insertions(+), 5 deletions(-)\n>>\n>> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c\n>> index 83dd26314d..b4fc791eb7 100644\n>> --- a/target/riscv/vector_helper.c\n>> +++ b/target/riscv/vector_helper.c\n>> @@ -47,18 +47,17 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,\n>> target_ulong reserved = s2 &\n>> MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,\n>> xlen - 1 - R_VTYPE_RESERVED_SHIFT);\n>> - uint16_t vlen = cpu->cfg.vlenb << 3;\n>> int8_t lmul;\n>>\n>> if (vlmul & 4) {\n>> /*\n>> * Fractional LMUL, check:\n>> *\n>> - * VLEN * LMUL >= SEW\n>> - * VLEN >> (8 - lmul) >= sew\n>> - * (vlenb << 3) >> (8 - lmul) >= sew\n>> + * ELEN * LMUL >= SEW\n>> + * ELEN >> (8 - vlmul) >= sew\n>> */\n>> - if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {\n>> + if (vlmul == 4 ||\n>> + (cpu->cfg.elen >> (8 - vlmul)) < sew) {\n>> vill = true;\n>> }\n>> }","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.alibaba.com header.i=@linux.alibaba.com\n header.a=rsa-sha256 header.s=default header.b=n9NaPVp1;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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