[{"id":3674408,"web_url":"http://patchwork.ozlabs.org/comment/3674408/","msgid":"","list_archive_url":null,"date":"2026-04-07T16:23:10","subject":"Re: [PATCH 1/5] target/riscv: Generate access fault if sc comparison\n fails","submitter":{"id":92265,"url":"http://patchwork.ozlabs.org/api/people/92265/","name":"Chao Liu","email":"chao.liu.zevorn@gmail.com"},"content":"On Tue, Apr 07, 2026 at 02:36:10PM +1000, alistair23@gmail.com wrote:\n> From: Alistair Francis \n> \n> The RISC-V spec states:\n> \n> \"For the purposes of memory protection, a failed SC.W may be treated\n> like a store.\"\n> \n> So if the comparison in sc.w fails we should still check for alignment\n> and do a probe access to check permissions.\n> \n> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3323\n> Resoves: https://gitlab.com/qemu-project/qemu/-/work_items/3136\n> Signed-off-by: Alistair Francis \n> ---\n> target/riscv/helper.h | 3 +++\n> target/riscv/op_helper.c | 14 ++++++++++++++\n> target/riscv/insn_trans/trans_rva.c.inc | 6 ++++++\n> 3 files changed, 23 insertions(+)\n> \n> diff --git a/target/riscv/helper.h b/target/riscv/helper.h\n> index b785456ee0..af6cfcfc27 100644\n> --- a/target/riscv/helper.h\n> +++ b/target/riscv/helper.h\n> @@ -1289,3 +1289,6 @@ DEF_HELPER_4(vsm4r_vs, void, ptr, ptr, env, i32)\n> #ifndef CONFIG_USER_ONLY\n> DEF_HELPER_1(ssamoswap_disabled, void, env)\n> #endif\n> +\n> +/* Zalrsc\" SC write probe */\nstray `\"` after Zalrsc.\n\nother LGTM :)\n\nReviewed-by: Chao Liu \n\nThanks,\nChao\n> +DEF_HELPER_FLAGS_3(sc_probe_write, TCG_CALL_NO_WG, void, env, tl, tl)\n> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c\n> index 6ccc127c30..b569366369 100644\n> --- a/target/riscv/op_helper.c\n> +++ b/target/riscv/op_helper.c\n> @@ -281,6 +281,20 @@ void helper_cbo_inval(CPURISCVState *env, target_ulong address)\n> /* We don't emulate the cache-hierarchy, so we're done. */\n> }\n> \n> +void helper_sc_probe_write(CPURISCVState *env, target_ulong addr,\n> + target_ulong size)\n> +{\n> + uintptr_t ra = GETPC();\n> + int mmu_idx = riscv_env_mmu_index(env, false);\n> +\n> + if (addr & (size - 1)) {\n> + env->badaddr = addr;\n> + riscv_raise_exception(env, RISCV_EXCP_STORE_AMO_ADDR_MIS, ra);\n> + }\n> +\n> + probe_write(env, addr, size, mmu_idx, ra);\n> +}\n> +\n> #ifndef CONFIG_USER_ONLY\n> \n> target_ulong helper_sret(CPURISCVState *env)\n> diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc\n> index a7a3278d24..62c0fe673d 100644\n> --- a/target/riscv/insn_trans/trans_rva.c.inc\n> +++ b/target/riscv/insn_trans/trans_rva.c.inc\n> @@ -90,6 +90,12 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)\n> */\n> TCGBar bar_strl = (ctx->ztso || a->rl) ? TCG_BAR_STRL : 0;\n> tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + bar_strl);\n> + /*\n> + * \"For the purposes of memory protection, a failed SC.W may be treated\n> + * like a store.\" so let's check the write access permissions\n> + */\n> + gen_helper_sc_probe_write(tcg_env, src1,\n> + tcg_constant_tl(memop_size(mop)));\n> gen_set_gpr(ctx, a->rd, tcg_constant_tl(1));\n> \n> gen_set_label(l2);\n> -- \n> 2.53.0\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=RYFo+iD9;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fqxCD6MXnz1xtJ\n\tfor ; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20260407043614.372871-2-alistair.francis@wdc.com>","Received-SPF":"pass client-ip=2607:f8b0:4864:20::744;\n envelope-from=chao.liu.zevorn@gmail.com; helo=mail-qk1-x744.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3674410,"web_url":"http://patchwork.ozlabs.org/comment/3674410/","msgid":"","list_archive_url":null,"date":"2026-04-07T09:38:11","subject":"Re: [PATCH 1/5] target/riscv: Generate access fault if sc comparison\n fails","submitter":{"id":92288,"url":"http://patchwork.ozlabs.org/api/people/92288/","name":"Daniel Henrique Barboza","email":"daniel.barboza@oss.qualcomm.com"},"content":"On 4/7/2026 1:36 AM, alistair23@gmail.com wrote:\n> From: Alistair Francis \n> \n> The RISC-V spec states:\n> \n> \"For the purposes of memory protection, a failed SC.W may be treated\n> like a store.\"\n> \n> So if the comparison in sc.w fails we should still check for alignment\n> and do a probe access to check permissions.\n> \n> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3323\n> Resoves: https://gitlab.com/qemu-project/qemu/-/work_items/3136\n\nTypo: \"Resoves\"\n\n\nAlso, IIRC the bug URL that automatically closes Gitlab issues when\nmerging the patch is on the format:\n\n\"Resolves: https://gitlab.com/qemu-project/qemu/-/issues/(number)\"\n\n\nMaybe this URL with \"work_items\" also works, but even with the regular\nURL Gitlab fails to autoclose the bug sometimes. I suggest changing the\n\"work_items\" to \"issues\" in all those URLs to be safe.\n\n\nThat said,\n\n\nReviewed-by: Daniel Henrique Barboza \n\n> Signed-off-by: Alistair Francis \n> ---\n> target/riscv/helper.h | 3 +++\n> target/riscv/op_helper.c | 14 ++++++++++++++\n> target/riscv/insn_trans/trans_rva.c.inc | 6 ++++++\n> 3 files changed, 23 insertions(+)\n> \n> diff --git a/target/riscv/helper.h b/target/riscv/helper.h\n> index b785456ee0..af6cfcfc27 100644\n> --- a/target/riscv/helper.h\n> +++ b/target/riscv/helper.h\n> @@ -1289,3 +1289,6 @@ DEF_HELPER_4(vsm4r_vs, void, ptr, ptr, env, i32)\n> #ifndef CONFIG_USER_ONLY\n> DEF_HELPER_1(ssamoswap_disabled, void, env)\n> #endif\n> +\n> +/* Zalrsc\" SC write probe */\n> +DEF_HELPER_FLAGS_3(sc_probe_write, TCG_CALL_NO_WG, void, env, tl, tl)\n> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c\n> index 6ccc127c30..b569366369 100644\n> --- a/target/riscv/op_helper.c\n> +++ b/target/riscv/op_helper.c\n> @@ -281,6 +281,20 @@ void helper_cbo_inval(CPURISCVState *env, target_ulong address)\n> /* We don't emulate the cache-hierarchy, so we're done. */\n> }\n> \n> +void helper_sc_probe_write(CPURISCVState *env, target_ulong addr,\n> + target_ulong size)\n> +{\n> + uintptr_t ra = GETPC();\n> + int mmu_idx = riscv_env_mmu_index(env, false);\n> +\n> + if (addr & (size - 1)) {\n> + env->badaddr = addr;\n> + riscv_raise_exception(env, RISCV_EXCP_STORE_AMO_ADDR_MIS, ra);\n> + }\n> +\n> + probe_write(env, addr, size, mmu_idx, ra);\n> +}\n> +\n> #ifndef CONFIG_USER_ONLY\n> \n> target_ulong helper_sret(CPURISCVState *env)\n> diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc\n> index a7a3278d24..62c0fe673d 100644\n> --- a/target/riscv/insn_trans/trans_rva.c.inc\n> +++ b/target/riscv/insn_trans/trans_rva.c.inc\n> @@ -90,6 +90,12 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)\n> */\n> TCGBar bar_strl = (ctx->ztso || a->rl) ? TCG_BAR_STRL : 0;\n> tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + bar_strl);\n> + /*\n> + * \"For the purposes of memory protection, a failed SC.W may be treated\n> + * like a store.\" so let's check the write access permissions\n> + */\n> + gen_helper_sc_probe_write(tcg_env, src1,\n> + tcg_constant_tl(memop_size(mop)));\n> gen_set_gpr(ctx, a->rd, tcg_constant_tl(1));\n> \n> gen_set_label(l2);","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=YsoDgAs3;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=GTUuDbBk;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n 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BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3674937,"web_url":"http://patchwork.ozlabs.org/comment/3674937/","msgid":"<09cf72c9-7333-4f1f-bb2a-bc88b668b294@linaro.org>","list_archive_url":null,"date":"2026-04-08T08:48:14","subject":"Re: [PATCH 1/5] target/riscv: Generate access fault if sc comparison\n fails","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"content":"On 7/4/26 11:38, Daniel Henrique Barboza wrote:\n> \n> \n> On 4/7/2026 1:36 AM, alistair23@gmail.com wrote:\n>> From: Alistair Francis \n>>\n>> The RISC-V spec states:\n>>\n>> \"For the purposes of memory protection, a failed SC.W may be treated\n>> like a store.\"\n>>\n>> So if the comparison in sc.w fails we should still check for alignment\n>> and do a probe access to check permissions.\n>>\n>> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3323\n>> Resoves: https://gitlab.com/qemu-project/qemu/-/work_items/3136\n> \n> Typo: \"Resoves\"\n> \n> \n> Also, IIRC the bug URL that automatically closes Gitlab issues when\n> merging the patch is on the format:\n> \n> \"Resolves: https://gitlab.com/qemu-project/qemu/-/issues/(number)\"\n> \n> \n> Maybe this URL with \"work_items\" also works, but even with the regular\n> URL Gitlab fails to autoclose the bug sometimes.  I suggest changing the\n> \"work_items\" to \"issues\" in all those URLs to be safe.\n\nFWIW I concur :)\n\n> \n> \n> That said,\n> \n> \n> Reviewed-by: Daniel Henrique Barboza \n> \n>> Signed-off-by: Alistair Francis \n>> ---\n>>   target/riscv/helper.h                   |  3 +++\n>>   target/riscv/op_helper.c                | 14 ++++++++++++++\n>>   target/riscv/insn_trans/trans_rva.c.inc |  6 ++++++\n>>   3 files changed, 23 insertions(+)\n>>\n>> diff --git a/target/riscv/helper.h b/target/riscv/helper.h\n>> index b785456ee0..af6cfcfc27 100644\n>> --- a/target/riscv/helper.h\n>> +++ b/target/riscv/helper.h\n>> @@ -1289,3 +1289,6 @@ DEF_HELPER_4(vsm4r_vs, void, ptr, ptr, env, i32)\n>>   #ifndef CONFIG_USER_ONLY\n>>   DEF_HELPER_1(ssamoswap_disabled, void, env)\n>>   #endif\n>> +\n>> +/* Zalrsc\" SC write probe */\n>> +DEF_HELPER_FLAGS_3(sc_probe_write, TCG_CALL_NO_WG, void, env, tl, tl)\n>> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c\n>> index 6ccc127c30..b569366369 100644\n>> --- a/target/riscv/op_helper.c\n>> +++ b/target/riscv/op_helper.c\n>> @@ -281,6 +281,20 @@ void helper_cbo_inval(CPURISCVState *env, \n>> target_ulong address)\n>>       /* We don't emulate the cache-hierarchy, so we're done. */\n>>   }\n>> +void helper_sc_probe_write(CPURISCVState *env, target_ulong addr,\n>> +                           target_ulong size)\n\nWe could directly use uint64_t for @size. Then after the release the\n@addr argument will be converted to vaddr type [*]. We could do that\ndirectly now:\n\n\nDEF_HELPER_FLAGS_3(sc_probe_write, TCG_CALL_NO_WG, void, env, vaddr, i64)\n\nvoid helper_sc_probe_write(CPURISCVState *env, vaddr addr,\n uint64_t size)\n\n\n[*] \nhttps://lore.kernel.org/qemu-devel/20260401143456.79843-1-philmd@linaro.org/\n\n>> +{\n>> +    uintptr_t ra = GETPC();\n>> +    int mmu_idx = riscv_env_mmu_index(env, false);\n>> +\n>> +    if (addr & (size - 1)) {\n>> +        env->badaddr = addr;\n>> +        riscv_raise_exception(env, RISCV_EXCP_STORE_AMO_ADDR_MIS, ra);\n>> +    }\n>> +\n>> +    probe_write(env, addr, size, mmu_idx, ra);\n>> +}","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=eFvAesbw;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::332;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3675083,"web_url":"http://patchwork.ozlabs.org/comment/3675083/","msgid":"","list_archive_url":null,"date":"2026-04-09T05:38:04","subject":"Re: [PATCH 1/5] target/riscv: Generate access fault if sc comparison\n fails","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Tue, Apr 7, 2026 at 7:38 PM Daniel Henrique Barboza\n wrote:\n>\n>\n>\n> On 4/7/2026 1:36 AM, alistair23@gmail.com wrote:\n> > From: Alistair Francis \n> >\n> > The RISC-V spec states:\n> >\n> > \"For the purposes of memory protection, a failed SC.W may be treated\n> > like a store.\"\n> >\n> > So if the comparison in sc.w fails we should still check for alignment\n> > and do a probe access to check permissions.\n> >\n> > Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3323\n> > Resoves: https://gitlab.com/qemu-project/qemu/-/work_items/3136\n>\n> Typo: \"Resoves\"\n>\n>\n> Also, IIRC the bug URL that automatically closes Gitlab issues when\n> merging the patch is on the format:\n>\n> \"Resolves: https://gitlab.com/qemu-project/qemu/-/issues/(number)\"\n\nInterestingly trying to access\n\nhttps://gitlab.com/qemu-project/qemu/-/issues/3196\n\ntakes me to\n\nhttps://gitlab.com/qemu-project/qemu/-/work_items/3196\n\nSo I think Gitlab is changing from issues to work_items\n\n>\n>\n> Maybe this URL with \"work_items\" also works, but even with the regular\n> URL Gitlab fails to autoclose the bug sometimes. I suggest changing the\n> \"work_items\" to \"issues\" in all those URLs to be safe.\n\nMaybe using \"issues\" is the problem?\n\nI'm thinking of leaving these as-is, as issues seem to be replaced now.\n\nI even see https://docs.gitlab.com/development/work_items/#migration-strategy\nand https://gitlab.com/groups/gitlab-org/-/work_items/6033 with more\ndetails on this\n\nAlistair\n\n>\n>\n> That said,\n>\n>\n> Reviewed-by: Daniel Henrique Barboza \n>\n> > Signed-off-by: Alistair Francis \n> > ---\n> > target/riscv/helper.h | 3 +++\n> > target/riscv/op_helper.c | 14 ++++++++++++++\n> > target/riscv/insn_trans/trans_rva.c.inc | 6 ++++++\n> > 3 files changed, 23 insertions(+)\n> >\n> > diff --git a/target/riscv/helper.h b/target/riscv/helper.h\n> > index b785456ee0..af6cfcfc27 100644\n> > --- a/target/riscv/helper.h\n> > +++ b/target/riscv/helper.h\n> > @@ -1289,3 +1289,6 @@ DEF_HELPER_4(vsm4r_vs, void, ptr, ptr, env, i32)\n> > #ifndef CONFIG_USER_ONLY\n> > DEF_HELPER_1(ssamoswap_disabled, void, env)\n> > #endif\n> > +\n> > +/* Zalrsc\" SC write probe */\n> > +DEF_HELPER_FLAGS_3(sc_probe_write, TCG_CALL_NO_WG, void, env, tl, tl)\n> > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c\n> > index 6ccc127c30..b569366369 100644\n> > --- a/target/riscv/op_helper.c\n> > +++ b/target/riscv/op_helper.c\n> > @@ -281,6 +281,20 @@ void helper_cbo_inval(CPURISCVState *env, target_ulong address)\n> > /* We don't emulate the cache-hierarchy, so we're done. */\n> > }\n> >\n> > +void helper_sc_probe_write(CPURISCVState *env, target_ulong addr,\n> > + target_ulong size)\n> > +{\n> > + uintptr_t ra = GETPC();\n> > + int mmu_idx = riscv_env_mmu_index(env, false);\n> > +\n> > + if (addr & (size - 1)) {\n> > + env->badaddr = addr;\n> > + riscv_raise_exception(env, RISCV_EXCP_STORE_AMO_ADDR_MIS, ra);\n> > + }\n> > +\n> > + probe_write(env, addr, size, mmu_idx, ra);\n> > +}\n> > +\n> > #ifndef CONFIG_USER_ONLY\n> >\n> > target_ulong helper_sret(CPURISCVState *env)\n> > diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc\n> > index a7a3278d24..62c0fe673d 100644\n> > --- a/target/riscv/insn_trans/trans_rva.c.inc\n> > +++ b/target/riscv/insn_trans/trans_rva.c.inc\n> > @@ -90,6 +90,12 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)\n> > */\n> > TCGBar bar_strl = (ctx->ztso || a->rl) ? TCG_BAR_STRL : 0;\n> > tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + bar_strl);\n> > + /*\n> > + * \"For the purposes of memory protection, a failed SC.W may be treated\n> > + * like a store.\" so let's check the write access permissions\n> > + */\n> > + gen_helper_sc_probe_write(tcg_env, src1,\n> > + tcg_constant_tl(memop_size(mop)));\n> > gen_set_gpr(ctx, a->rd, tcg_constant_tl(1));\n> >\n> > gen_set_label(l2);\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=WNRCllf/;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frpfn16Ynz1yCv\n\tfor ; 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Wed, 08 Apr 2026\n 22:38:30 -0700 (PDT)","MIME-Version":"1.0","References":"<20260407043614.372871-1-alistair.francis@wdc.com>\n <20260407043614.372871-2-alistair.francis@wdc.com>\n ","In-Reply-To":"","From":"Alistair Francis ","Date":"Thu, 9 Apr 2026 15:38:04 +1000","X-Gm-Features":"AQROBzCsgrh6cwXnWWPGB8MOE00sfMkIKiBn1V43DbufBsVt28uHbObK2IFtcp0","Message-ID":"\n ","Subject":"Re: [PATCH 1/5] target/riscv: Generate access fault if sc comparison\n fails","To":"Daniel Henrique Barboza ","Cc":"palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com,\n chao.liu.zevorn@gmail.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org,\n Alistair Francis ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Received-SPF":"pass client-ip=2a00:1450:4864:20::633;\n envelope-from=alistair23@gmail.com; helo=mail-ej1-x633.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3675093,"web_url":"http://patchwork.ozlabs.org/comment/3675093/","msgid":"","list_archive_url":null,"date":"2026-04-09T06:21:45","subject":"Re: [PATCH 1/5] target/riscv: Generate access fault if sc comparison\n fails","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Wed, Apr 8, 2026 at 6:48 PM Philippe Mathieu-Daudé wrote:\n>\n> On 7/4/26 11:38, Daniel Henrique Barboza wrote:\n> >\n> >\n> > On 4/7/2026 1:36 AM, alistair23@gmail.com wrote:\n> >> From: Alistair Francis \n> >>\n> >> The RISC-V spec states:\n> >>\n> >> \"For the purposes of memory protection, a failed SC.W may be treated\n> >> like a store.\"\n> >>\n> >> So if the comparison in sc.w fails we should still check for alignment\n> >> and do a probe access to check permissions.\n> >>\n> >> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3323\n> >> Resoves: https://gitlab.com/qemu-project/qemu/-/work_items/3136\n> >\n> > Typo: \"Resoves\"\n> >\n> >\n> > Also, IIRC the bug URL that automatically closes Gitlab issues when\n> > merging the patch is on the format:\n> >\n> > \"Resolves: https://gitlab.com/qemu-project/qemu/-/issues/(number)\"\n> >\n> >\n> > Maybe this URL with \"work_items\" also works, but even with the regular\n> > URL Gitlab fails to autoclose the bug sometimes. I suggest changing the\n> > \"work_items\" to \"issues\" in all those URLs to be safe.\n>\n> FWIW I concur :)\n>\n> >\n> >\n> > That said,\n> >\n> >\n> > Reviewed-by: Daniel Henrique Barboza \n> >\n> >> Signed-off-by: Alistair Francis \n> >> ---\n> >> target/riscv/helper.h | 3 +++\n> >> target/riscv/op_helper.c | 14 ++++++++++++++\n> >> target/riscv/insn_trans/trans_rva.c.inc | 6 ++++++\n> >> 3 files changed, 23 insertions(+)\n> >>\n> >> diff --git a/target/riscv/helper.h b/target/riscv/helper.h\n> >> index b785456ee0..af6cfcfc27 100644\n> >> --- a/target/riscv/helper.h\n> >> +++ b/target/riscv/helper.h\n> >> @@ -1289,3 +1289,6 @@ DEF_HELPER_4(vsm4r_vs, void, ptr, ptr, env, i32)\n> >> #ifndef CONFIG_USER_ONLY\n> >> DEF_HELPER_1(ssamoswap_disabled, void, env)\n> >> #endif\n> >> +\n> >> +/* Zalrsc\" SC write probe */\n> >> +DEF_HELPER_FLAGS_3(sc_probe_write, TCG_CALL_NO_WG, void, env, tl, tl)\n> >> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c\n> >> index 6ccc127c30..b569366369 100644\n> >> --- a/target/riscv/op_helper.c\n> >> +++ b/target/riscv/op_helper.c\n> >> @@ -281,6 +281,20 @@ void helper_cbo_inval(CPURISCVState *env,\n> >> target_ulong address)\n> >> /* We don't emulate the cache-hierarchy, so we're done. */\n> >> }\n> >> +void helper_sc_probe_write(CPURISCVState *env, target_ulong addr,\n> >> + target_ulong size)\n>\n> We could directly use uint64_t for @size. Then after the release the\n> @addr argument will be converted to vaddr type [*]. We could do that\n> directly now:\n>\n>\n> DEF_HELPER_FLAGS_3(sc_probe_write, TCG_CALL_NO_WG, void, env, vaddr, i64)\n>\n> void helper_sc_probe_write(CPURISCVState *env, vaddr addr,\n> uint64_t size)\n\nThat fails for RV32 linux-user\n\n../target/riscv/insn_trans/trans_rva.c.inc:97:40: error: passing\nargument 2 of ‘gen_helper_sc_probe_write’ from incompatible pointer\ntype [-Wincompatible-po\ninter-types]\n 97 | gen_helper_sc_probe_write(tcg_env, src1,\n | ^~~~\n | |\n | TCGv {aka struct TCGv_i32_d *}\nIn file included from\n/var/mnt/scratch/alistair/software/qemu/include/qemu/osdep.h:53,\n from ../target/riscv/translate.c:19:\n/var/mnt/scratch/alistair/software/qemu/include/exec/helper-head.h.inc:128:57:\nnote: expected ‘TCGv_i64’ {aka ‘struct TCGv_i64_d *’} but argument is\nof type\n‘TCGv’ {aka ‘struct TCGv_i32_d *’}\n 128 | #define dh_arg_decl(t, n) glue(TCGv_, dh_alias(t)) glue(arg, n)\n | ^\n/var/mnt/scratch/alistair/software/qemu/include/qemu/compiler.h:29:21:\nnote: in definition of macro ‘xglue’\n 29 | #define xglue(x, y) x ## y\n | ^\n/var/mnt/scratch/alistair/software/qemu/include/exec/helper-head.h.inc:128:52:\nnote: in expansion of macro ‘glue’\n 128 | #define dh_arg_decl(t, n) glue(TCGv_, dh_alias(t)) glue(arg, n)\n | ^~~~\n/var/mnt/scratch/alistair/software/qemu/include/exec/helper-gen.h.inc:44:25:\nnote: in expansion of macro ‘dh_arg_decl’\n 44 | dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3)) \\\n | ^~~~~~~~~~~\n../target/riscv/helper.h:1294:1: note: in expansion of macro\n‘DEF_HELPER_FLAGS_3’\n1294 | DEF_HELPER_FLAGS_3(sc_probe_write, TCG_CALL_NO_WG, void, env, vaddr, i64)\n | ^~~~~~~~~~~~~~~~~~\nIn file included from\n/var/mnt/scratch/alistair/software/qemu/include/tcg/tcg-op-common.h:11,\n from\n/var/mnt/scratch/alistair/software/qemu/include/tcg/tcg-op.h:11,\n from ../target/riscv/translate.c:22:\n/var/mnt/scratch/alistair/software/qemu/include/tcg/tcg.h:202:28:\nnote: ‘TCGv_i64’ declared here\n 202 | typedef struct TCGv_i64_d *TCGv_i64;\n | ^~~~~~~~\n/var/mnt/scratch/alistair/software/qemu/include/tcg/tcg-op.h:32:18:\nnote: ‘TCGv’ declared here\n 32 | typedef TCGv_i32 TCGv;\n | ^~~~\n\nAm I missing something?\n\nAlistair\n\n>\n>\n> [*]\n> https://lore.kernel.org/qemu-devel/20260401143456.79843-1-philmd@linaro.org/\n>\n> >> +{\n> >> + uintptr_t ra = GETPC();\n> >> + int mmu_idx = riscv_env_mmu_index(env, false);\n> >> +\n> >> + if (addr & (size - 1)) {\n> >> + env->badaddr = addr;\n> >> + riscv_raise_exception(env, RISCV_EXCP_STORE_AMO_ADDR_MIS, ra);\n> >> + }\n> >> +\n> >> + probe_write(env, addr, size, mmu_idx, ra);\n> >> +}","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=gKXx4AT5;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Wed, 08 Apr 2026\n 23:22:11 -0700 (PDT)","MIME-Version":"1.0","References":"<20260407043614.372871-1-alistair.francis@wdc.com>\n <20260407043614.372871-2-alistair.francis@wdc.com>\n \n <09cf72c9-7333-4f1f-bb2a-bc88b668b294@linaro.org>","In-Reply-To":"<09cf72c9-7333-4f1f-bb2a-bc88b668b294@linaro.org>","From":"Alistair Francis ","Date":"Thu, 9 Apr 2026 16:21:45 +1000","X-Gm-Features":"AQROBzCgW61uRy9XGxf1N5vGO5BALdj_f-tUsU_LqVhudpm7gEKjJM6n6PoYOOM","Message-ID":"\n ","Subject":"Re: [PATCH 1/5] target/riscv: Generate access fault if sc comparison\n fails","To":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","Cc":"Daniel Henrique Barboza ,\n palmer@dabbelt.com,\n liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com,\n qemu-riscv@nongnu.org, qemu-devel@nongnu.org,\n Alistair Francis ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Received-SPF":"pass client-ip=2a00:1450:4864:20::629;\n envelope-from=alistair23@gmail.com; helo=mail-ej1-x629.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3675222,"web_url":"http://patchwork.ozlabs.org/comment/3675222/","msgid":"","list_archive_url":null,"date":"2026-04-09T10:00:04","subject":"Re: [PATCH 1/5] target/riscv: Generate access fault if sc comparison\n fails","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"content":"On 9/4/26 08:21, Alistair Francis wrote:\n> On Wed, Apr 8, 2026 at 6:48 PM Philippe Mathieu-Daudé wrote:\n>>\n>> On 7/4/26 11:38, Daniel Henrique Barboza wrote:\n>>>\n>>>\n>>> On 4/7/2026 1:36 AM, alistair23@gmail.com wrote:\n>>>> From: Alistair Francis \n>>>>\n>>>> The RISC-V spec states:\n>>>>\n>>>> \"For the purposes of memory protection, a failed SC.W may be treated\n>>>> like a store.\"\n>>>>\n>>>> So if the comparison in sc.w fails we should still check for alignment\n>>>> and do a probe access to check permissions.\n>>>>\n>>>> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3323\n>>>> Resoves: https://gitlab.com/qemu-project/qemu/-/work_items/3136\n>>>\n>>> Typo: \"Resoves\"\n>>>\n>>>\n>>> Also, IIRC the bug URL that automatically closes Gitlab issues when\n>>> merging the patch is on the format:\n>>>\n>>> \"Resolves: https://gitlab.com/qemu-project/qemu/-/issues/(number)\"\n>>>\n>>>\n>>> Maybe this URL with \"work_items\" also works, but even with the regular\n>>> URL Gitlab fails to autoclose the bug sometimes. I suggest changing the\n>>> \"work_items\" to \"issues\" in all those URLs to be safe.\n>>\n>> FWIW I concur :)\n>>\n>>>\n>>>\n>>> That said,\n>>>\n>>>\n>>> Reviewed-by: Daniel Henrique Barboza \n>>>\n>>>> Signed-off-by: Alistair Francis \n>>>> ---\n>>>> target/riscv/helper.h | 3 +++\n>>>> target/riscv/op_helper.c | 14 ++++++++++++++\n>>>> target/riscv/insn_trans/trans_rva.c.inc | 6 ++++++\n>>>> 3 files changed, 23 insertions(+)\n>>>>\n>>>> diff --git a/target/riscv/helper.h b/target/riscv/helper.h\n>>>> index b785456ee0..af6cfcfc27 100644\n>>>> --- a/target/riscv/helper.h\n>>>> +++ b/target/riscv/helper.h\n>>>> @@ -1289,3 +1289,6 @@ DEF_HELPER_4(vsm4r_vs, void, ptr, ptr, env, i32)\n>>>> #ifndef CONFIG_USER_ONLY\n>>>> DEF_HELPER_1(ssamoswap_disabled, void, env)\n>>>> #endif\n>>>> +\n>>>> +/* Zalrsc\" SC write probe */\n>>>> +DEF_HELPER_FLAGS_3(sc_probe_write, TCG_CALL_NO_WG, void, env, tl, tl)\n>>>> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c\n>>>> index 6ccc127c30..b569366369 100644\n>>>> --- a/target/riscv/op_helper.c\n>>>> +++ b/target/riscv/op_helper.c\n>>>> @@ -281,6 +281,20 @@ void helper_cbo_inval(CPURISCVState *env,\n>>>> target_ulong address)\n>>>> /* We don't emulate the cache-hierarchy, so we're done. */\n>>>> }\n>>>> +void helper_sc_probe_write(CPURISCVState *env, target_ulong addr,\n>>>> + target_ulong size)\n>>\n>> We could directly use uint64_t for @size. Then after the release the\n>> @addr argument will be converted to vaddr type [*]. We could do that\n>> directly now:\n>>\n>>\n>> DEF_HELPER_FLAGS_3(sc_probe_write, TCG_CALL_NO_WG, void, env, vaddr, i64)\n>>\n>> void helper_sc_probe_write(CPURISCVState *env, vaddr addr,\n>> uint64_t size)\n> \n> That fails for RV32 linux-user\n> \n> ../target/riscv/insn_trans/trans_rva.c.inc:97:40: error: passing\n> argument 2 of ‘gen_helper_sc_probe_write’ from incompatible pointer\n> type [-Wincompatible-po\n> inter-types]\n> 97 | gen_helper_sc_probe_write(tcg_env, src1,\n> | ^~~~\n> | |\n> | TCGv {aka struct TCGv_i32_d *}\n> In file included from\n> /var/mnt/scratch/alistair/software/qemu/include/qemu/osdep.h:53,\n> from ../target/riscv/translate.c:19:\n> /var/mnt/scratch/alistair/software/qemu/include/exec/helper-head.h.inc:128:57:\n> note: expected ‘TCGv_i64’ {aka ‘struct TCGv_i64_d *’} but argument is\n> of type\n> ‘TCGv’ {aka ‘struct TCGv_i32_d *’}\n> 128 | #define dh_arg_decl(t, n) glue(TCGv_, dh_alias(t)) glue(arg, n)\n> | ^\n> /var/mnt/scratch/alistair/software/qemu/include/qemu/compiler.h:29:21:\n> note: in definition of macro ‘xglue’\n> 29 | #define xglue(x, y) x ## y\n> | ^\n> /var/mnt/scratch/alistair/software/qemu/include/exec/helper-head.h.inc:128:52:\n> note: in expansion of macro ‘glue’\n> 128 | #define dh_arg_decl(t, n) glue(TCGv_, dh_alias(t)) glue(arg, n)\n> | ^~~~\n> /var/mnt/scratch/alistair/software/qemu/include/exec/helper-gen.h.inc:44:25:\n> note: in expansion of macro ‘dh_arg_decl’\n> 44 | dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3)) \\\n> | ^~~~~~~~~~~\n> ../target/riscv/helper.h:1294:1: note: in expansion of macro\n> ‘DEF_HELPER_FLAGS_3’\n> 1294 | DEF_HELPER_FLAGS_3(sc_probe_write, TCG_CALL_NO_WG, void, env, vaddr, i64)\n> | ^~~~~~~~~~~~~~~~~~\n> In file included from\n> /var/mnt/scratch/alistair/software/qemu/include/tcg/tcg-op-common.h:11,\n> from\n> /var/mnt/scratch/alistair/software/qemu/include/tcg/tcg-op.h:11,\n> from ../target/riscv/translate.c:22:\n> /var/mnt/scratch/alistair/software/qemu/include/tcg/tcg.h:202:28:\n> note: ‘TCGv_i64’ declared here\n> 202 | typedef struct TCGv_i64_d *TCGv_i64;\n> | ^~~~~~~~\n> /var/mnt/scratch/alistair/software/qemu/include/tcg/tcg-op.h:32:18:\n> note: ‘TCGv’ declared here\n> 32 | typedef TCGv_i32 TCGv;\n> | ^~~~\n> \n> Am I missing something?\n\nOh, RISCV needs more work than :( Discard my suggestion then,\nthanks for trying it and sorry for the delay.\n\nRegards,\n\nPhil.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=zNZU07dJ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::330;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3675224,"web_url":"http://patchwork.ozlabs.org/comment/3675224/","msgid":"","list_archive_url":null,"date":"2026-04-09T10:02:02","subject":"Re: [PATCH 1/5] target/riscv: Generate access fault if sc comparison\n fails","submitter":{"id":92288,"url":"http://patchwork.ozlabs.org/api/people/92288/","name":"Daniel Henrique Barboza","email":"daniel.barboza@oss.qualcomm.com"},"content":"On 4/9/2026 2:38 AM, Alistair Francis wrote:\n> On Tue, Apr 7, 2026 at 7:38 PM Daniel Henrique Barboza\n> wrote:\n>>\n>>\n>>\n>> On 4/7/2026 1:36 AM, alistair23@gmail.com wrote:\n>>> From: Alistair Francis \n>>>\n>>> The RISC-V spec states:\n>>>\n>>> \"For the purposes of memory protection, a failed SC.W may be treated\n>>> like a store.\"\n>>>\n>>> So if the comparison in sc.w fails we should still check for alignment\n>>> and do a probe access to check permissions.\n>>>\n>>> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3323\n>>> Resoves: https://gitlab.com/qemu-project/qemu/-/work_items/3136\n>>\n>> Typo: \"Resoves\"\n>>\n>>\n>> Also, IIRC the bug URL that automatically closes Gitlab issues when\n>> merging the patch is on the format:\n>>\n>> \"Resolves: https://gitlab.com/qemu-project/qemu/-/issues/(number)\"\n> \n> Interestingly trying to access\n> \n> https://gitlab.com/qemu-project/qemu/-/issues/3196\n> \n> takes me to\n> \n> https://gitlab.com/qemu-project/qemu/-/work_items/3196\n> \n> So I think Gitlab is changing from issues to work_items\n> \n>>\n>>\n>> Maybe this URL with \"work_items\" also works, but even with the regular\n>> URL Gitlab fails to autoclose the bug sometimes. I suggest changing the\n>> \"work_items\" to \"issues\" in all those URLs to be safe.\n> \n> Maybe using \"issues\" is the problem?\n> \n> I'm thinking of leaving these as-is, as issues seem to be replaced now.\n> \n> I even see https://docs.gitlab.com/development/work_items/#migration-strategy\n> and https://gitlab.com/groups/gitlab-org/-/work_items/6033 with more\n> details on this\n\nSeems like you're ahead of the curve then :D let's leave it as is and\nsee if the bug autocloses when the patches are merged.\n\n\nThanks,\nDaniel\n\n> \n> Alistair\n> \n>>\n>>\n>> That said,\n>>\n>>\n>> Reviewed-by: Daniel Henrique Barboza \n>>\n>>> Signed-off-by: Alistair Francis \n>>> ---\n>>> target/riscv/helper.h | 3 +++\n>>> target/riscv/op_helper.c | 14 ++++++++++++++\n>>> target/riscv/insn_trans/trans_rva.c.inc | 6 ++++++\n>>> 3 files changed, 23 insertions(+)\n>>>\n>>> diff --git a/target/riscv/helper.h b/target/riscv/helper.h\n>>> index b785456ee0..af6cfcfc27 100644\n>>> --- a/target/riscv/helper.h\n>>> +++ b/target/riscv/helper.h\n>>> @@ -1289,3 +1289,6 @@ DEF_HELPER_4(vsm4r_vs, void, ptr, ptr, env, i32)\n>>> #ifndef CONFIG_USER_ONLY\n>>> DEF_HELPER_1(ssamoswap_disabled, void, env)\n>>> #endif\n>>> +\n>>> +/* Zalrsc\" SC write probe */\n>>> +DEF_HELPER_FLAGS_3(sc_probe_write, TCG_CALL_NO_WG, void, env, tl, tl)\n>>> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c\n>>> index 6ccc127c30..b569366369 100644\n>>> --- a/target/riscv/op_helper.c\n>>> +++ b/target/riscv/op_helper.c\n>>> @@ -281,6 +281,20 @@ void helper_cbo_inval(CPURISCVState *env, target_ulong address)\n>>> /* We don't emulate the cache-hierarchy, so we're done. */\n>>> }\n>>>\n>>> +void helper_sc_probe_write(CPURISCVState *env, target_ulong addr,\n>>> + target_ulong size)\n>>> +{\n>>> + uintptr_t ra = GETPC();\n>>> + int mmu_idx = riscv_env_mmu_index(env, false);\n>>> +\n>>> + if (addr & (size - 1)) {\n>>> + env->badaddr = addr;\n>>> + riscv_raise_exception(env, RISCV_EXCP_STORE_AMO_ADDR_MIS, ra);\n>>> + }\n>>> +\n>>> + probe_write(env, addr, size, mmu_idx, ra);\n>>> +}\n>>> +\n>>> #ifndef CONFIG_USER_ONLY\n>>>\n>>> target_ulong helper_sret(CPURISCVState *env)\n>>> diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc\n>>> index a7a3278d24..62c0fe673d 100644\n>>> --- a/target/riscv/insn_trans/trans_rva.c.inc\n>>> +++ b/target/riscv/insn_trans/trans_rva.c.inc\n>>> @@ -90,6 +90,12 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)\n>>> */\n>>> TCGBar bar_strl = (ctx->ztso || a->rl) ? TCG_BAR_STRL : 0;\n>>> tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + bar_strl);\n>>> + /*\n>>> + * \"For the purposes of memory protection, a failed SC.W may be treated\n>>> + * like a store.\" so let's check the write access permissions\n>>> + */\n>>> + gen_helper_sc_probe_write(tcg_env, src1,\n>>> + tcg_constant_tl(memop_size(mop)));\n>>> gen_set_gpr(ctx, a->rd, tcg_constant_tl(1));\n>>>\n>>> gen_set_label(l2);\n>>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=PuelqURh;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=VJpXCJdR;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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I suggest changing the\n> >> \"work_items\" to \"issues\" in all those URLs to be safe.\n> >\n> > Maybe using \"issues\" is the problem?\n> >\n> > I'm thinking of leaving these as-is, as issues seem to be replaced now.\n> >\n> > I even see https://docs.gitlab.com/development/work_items/#migration-strategy\n> > and https://gitlab.com/groups/gitlab-org/-/work_items/6033 with more\n> > details on this\n>\n> Seems like you're ahead of the curve then :D let's leave it as is and\n> see if the bug autocloses when the patches are merged.\n\nI didn't know that when I started, I just tried to open the issue link\nand it went to work_items :)\n\nSeems like it does work though:\nhttps://gitlab.com/qemu-project/qemu/-/work_items/2796\n\nAlistair","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=AOFont5m;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Thu, 09 Apr 2026\n 16:30:00 -0700 (PDT)","MIME-Version":"1.0","References":"<20260407043614.372871-1-alistair.francis@wdc.com>\n <20260407043614.372871-2-alistair.francis@wdc.com>\n \n \n ","In-Reply-To":"","From":"Alistair Francis ","Date":"Fri, 10 Apr 2026 09:29:34 +1000","X-Gm-Features":"AQROBzCeSsKXhQopGjUlA3xcGjtF0usIIEJ_ap8Hg5J-qybOI2ZpAY7ohf3CjaA","Message-ID":"\n ","Subject":"Re: [PATCH 1/5] target/riscv: Generate access fault if sc comparison\n fails","To":"Daniel Henrique Barboza ","Cc":"palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com,\n chao.liu.zevorn@gmail.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org,\n Alistair Francis ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Received-SPF":"pass client-ip=2a00:1450:4864:20::633;\n envelope-from=alistair23@gmail.com; helo=mail-ej1-x633.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}}]