[{"id":3674404,"web_url":"http://patchwork.ozlabs.org/comment/3674404/","msgid":"","list_archive_url":null,"date":"2026-04-07T09:41:50","subject":"Re: [PATCH 3/5] target/riscv: Don't OR mip.SEIP when mvien is one","submitter":{"id":92288,"url":"http://patchwork.ozlabs.org/api/people/92288/","name":"Daniel Henrique Barboza","email":"daniel.barboza@oss.qualcomm.com"},"content":"On 4/7/2026 1:36 AM, alistair23@gmail.com wrote:\n> From: Alistair Francis \n> \n> The RISC-V spec states that\n> \n> \"\"\"\n> But when bit 9 of mvien is one, bit SEIP in mip is read-only and does\n> not include the value of bit 9 of mvip. Rather, the value of mip.SEIP\n> is simply the supervisor external interrupt signal from the hart’s\n> external interrupt controller (APLIC or IMSIC).\n> \"\"\"\n> \n> From my understanding this means we should remove MIP_SEIP from the\n> alias mask.\n> \n> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/2828\n> Signed-off-by: Alistair Francis \n> ---\n\n\nReviewed-by: Daniel Henrique Barboza \n\n> target/riscv/csr.c | 8 ++++++++\n> 1 file changed, 8 insertions(+)\n> \n> diff --git a/target/riscv/csr.c b/target/riscv/csr.c\n> index a75281539b..2a2f9497db 100644\n> --- a/target/riscv/csr.c\n> +++ b/target/riscv/csr.c\n> @@ -3796,6 +3796,14 @@ static RISCVException rmw_mvip64(CPURISCVState *env, int csrno,\n> /* Remove bits that are zero in both mideleg and mvien. */\n> alias_mask &= (env->mideleg | env->mvien);\n> nalias_mask &= (env->mideleg | env->mvien);\n> + } else {\n> + if (env->mvien & MIP_SEIP) {\n> + /*\n> + * Bit SEIP in mip is read-only and does not\n> + * include the value of bit 9 of mvip\n> + */\n> + alias_mask &= ~MIP_SEIP;\n> + }\n> }\n> \n> /*","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=Akd3NRI0;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=acmjfl1i;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Rather, the value of mip.SEIP\n> is simply the supervisor external interrupt signal from the hart’s\n> external interrupt controller (APLIC or IMSIC).\n> \"\"\"\n> \n> From my understanding this means we should remove MIP_SEIP from the\n> alias mask.\n> \n> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/2828\n> Signed-off-by: Alistair Francis \n> ---\n> target/riscv/csr.c | 8 ++++++++\n> 1 file changed, 8 insertions(+)\n> \n> diff --git a/target/riscv/csr.c b/target/riscv/csr.c\n> index a75281539b..2a2f9497db 100644\n> --- a/target/riscv/csr.c\n> +++ b/target/riscv/csr.c\n> @@ -3796,6 +3796,14 @@ static RISCVException rmw_mvip64(CPURISCVState *env, int csrno,\n> /* Remove bits that are zero in both mideleg and mvien. */\n> alias_mask &= (env->mideleg | env->mvien);\n> nalias_mask &= (env->mideleg | env->mvien);\n> + } else {\n> + if (env->mvien & MIP_SEIP) {\n> + /*\n> + * Bit SEIP in mip is read-only and does not\n> + * include the value of bit 9 of mvip\n> + */\n> + alias_mask &= ~MIP_SEIP;\nThis needs some discussion. I did a simple derivation of the\nalias_mask initial value for bit 9 across all four combinations:\n\n alias_mask = ((S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) &\n (env->mideleg | ~env->mvien)) | MIP_STIP;\n\n mideleg[9] mvien[9] | ~mvien[9] mideleg|~mvien | alias[9] nalias[9]\n ---------- -------- + --------- -------------- + -------- ---------\n 0 0 | 1 1 | 1 0\n 0 1 | 0 0 | 0 1\n 1 0 | 1 1 | 1 0\n 1 1 | 0 1 | 1 0\n\nChecking only mvien[9]=1 actually includes two cases:\n - combo 2: mideleg=0, mvien=1\n - combo 4: mideleg=1, mvien=1\n\nCombo 2 already has alias_mask[9]=0, so the else branch is a\nno-op there. The only effective case is combo 4, where\nalias_mask[9] goes from 1 to 0. But nalias_mask[9] is also 0\nfor combo 4, so SEIP disappears from MVIP entirely.\n\nPer the truth table in the function header:\n\n mideleg[i]=1, mvien[i]=X -> mvip[i] aliases mip[i]\n\nIs there a special intent to break this alias for SEIP? Could\nyou clarify?\n\nPer the AIA spec, I think the fix should be in rmw_mip64()\ninstead — make mip.SEIP read-only when mvien[9]=1, similar\nto how sstc makes STIP read-only:\n\n static RISCVException rmw_mip64(CPURISCVState *env, int csrno,\n uint64_t *ret_val,\n uint64_t new_val, uint64_t wr_mask)\n {\n uint64_t old_mip, mask = wr_mask & delegable_ints;\n uint32_t gin;\n\n + /*\n + * When mvien[9]=1, mip.SEIP is read-only and reflects only\n + * the external interrupt signal from the interrupt controller.\n + */\n + if (env->mvien & MIP_SEIP) {\n + mask &= ~MIP_SEIP;\n + }\n +\n if (mask & MIP_SEIP) {\n env->software_seip = new_val & MIP_SEIP;\n new_val |= env->external_seip * MIP_SEIP;\n }\n ...\n\nReviewed-by: Chao Liu \n\nThanks,\nChao\n> + }\n> }\n> \n> /*\n> -- \n> 2.53.0\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=WKoBW+Ip;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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