[{"id":3674200,"web_url":"http://patchwork.ozlabs.org/comment/3674200/","msgid":"<7ewnbwdo5qtasbxj4uel6a6uthczq2l6udbvoqqkwm776lvseb@v54ri2gknwxn>","list_archive_url":null,"date":"2026-04-07T13:57:25","subject":"Re: [PATCH V11 04/12] PCI: imx6: Add support for parsing the reset\n property in new Root Port binding","submitter":{"id":78905,"url":"http://patchwork.ozlabs.org/api/people/78905/","name":"Manivannan Sadhasivam","email":"mani@kernel.org"},"content":"On Tue, Apr 07, 2026 at 06:41:46PM +0800, Sherry Sun wrote:\n> The current DT binding for pci-imx6 specifies the 'reset-gpios' property\n> in the host bridge node. However, the PERST# signal logically belongs to\n> individual Root Ports rather than the host bridge itself. This becomes\n> important when supporting PCIe KeyE connector and PCI power control\n> framework for pci-imx6 driver, which requires properties to be specified\n> in Root Port nodes.\n> \n> Add support for parsing 'reset-gpios' from Root Port child nodes using\n> the common helper pci_host_common_parse_ports(), and update the reset\n> GPIO handling to use the parsed port list from bridge->ports. To\n> maintain DT backwards compatibility, fallback to the legacy method of\n> parsing the host bridge node if the reset property is not present in the\n> Root Port node.\n> \n> Since now the reset GPIO is obtained with GPIOD_ASIS flag, it may be in\n> input mode, using gpiod_direction_output() instead of\n> gpiod_set_value_cansleep() to ensure the reset GPIO is properly\n> configured as output before setting its value.\n> \n> Signed-off-by: Sherry Sun \n> ---\n> drivers/pci/controller/dwc/pci-imx6.c | 75 +++++++++++++++++++++------\n> 1 file changed, 60 insertions(+), 15 deletions(-)\n> \n> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c\n> index d99da7e42590..dd8f9c0fcec4 100644\n> --- a/drivers/pci/controller/dwc/pci-imx6.c\n> +++ b/drivers/pci/controller/dwc/pci-imx6.c\n> @@ -34,6 +34,7 @@\n> #include \n> \n> #include \"../../pci.h\"\n> +#include \"../pci-host-common.h\"\n> #include \"pcie-designware.h\"\n> \n> #define IMX8MQ_GPR_PCIE_REF_USE_PAD\t\tBIT(9)\n> @@ -152,7 +153,6 @@ struct imx_lut_data {\n> \n> struct imx_pcie {\n> \tstruct dw_pcie\t\t*pci;\n> -\tstruct gpio_desc\t*reset_gpiod;\n> \tstruct clk_bulk_data\t*clks;\n> \tint\t\t\tnum_clks;\n> \tbool\t\t\tsupports_clkreq;\n> @@ -1224,6 +1224,32 @@ static void imx_pcie_disable_device(struct pci_host_bridge *bridge,\n> \timx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev));\n> }\n> \n> +static int imx_pcie_parse_legacy_binding(struct imx_pcie *pcie)\n> +{\n> +\tstruct device *dev = pcie->pci->dev;\n> +\tstruct pci_host_bridge *bridge = pcie->pci->pp.bridge;\n> +\tstruct pci_host_port *port;\n> +\tstruct gpio_desc *reset;\n> +\n> +\treset = devm_gpiod_get_optional(dev, \"reset\", GPIOD_ASIS);\n> +\tif (IS_ERR(reset))\n> +\t\treturn PTR_ERR(reset);\n> +\n> +\tif (!reset)\n> +\t\treturn 0;\n> +\n> +\tport = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);\n> +\tif (!port)\n> +\t\treturn -ENOMEM;\n> +\n> +\tport->reset = reset;\n> +\tINIT_LIST_HEAD(&port->list);\n> +\tlist_add_tail(&port->list, &bridge->ports);\n> +\n> +\treturn devm_add_action_or_reset(dev, pci_host_common_delete_ports,\n> +\t\t\t\t\t&bridge->ports);\n> +}\n> +\n> static void imx_pcie_vpcie_aux_disable(void *data)\n> {\n> \tstruct regulator *vpcie_aux = data;\n> @@ -1233,13 +1259,22 @@ static void imx_pcie_vpcie_aux_disable(void *data)\n> \n> static void imx_pcie_assert_perst(struct imx_pcie *imx_pcie, bool assert)\n> {\n> -\tif (assert) {\n> -\t\tgpiod_set_value_cansleep(imx_pcie->reset_gpiod, 1);\n> -\t} else {\n> -\t\tif (imx_pcie->reset_gpiod) {\n> -\t\t\tmsleep(PCIE_T_PVPERL_MS);\n> -\t\t\tgpiod_set_value_cansleep(imx_pcie->reset_gpiod, 0);\n> -\t\t\tmsleep(PCIE_RESET_CONFIG_WAIT_MS);\n> +\tstruct dw_pcie *pci = imx_pcie->pci;\n> +\tstruct pci_host_bridge *bridge = pci->pp.bridge;\n> +\tstruct pci_host_port *port;\n> +\n> +\tif (!bridge)\n> +\t\treturn;\n> +\n> +\tlist_for_each_entry(port, &bridge->ports, list) {\n> +\t\tif (assert) {\n> +\t\t\tgpiod_direction_output(port->reset, 1);\n> +\t\t} else {\n> +\t\t\tif (port->reset) {\n> +\t\t\t\tmsleep(PCIE_T_PVPERL_MS);\n> +\t\t\t\tgpiod_direction_output(port->reset, 0);\n> +\t\t\t\tmsleep(PCIE_RESET_CONFIG_WAIT_MS);\n> +\t\t\t}\n\nSashiko flagged this loop:\n\n```\nDoes this loop multiply the initialization delays?\nIf a controller has multiple Root Ports, the msleep calls will run\nsequentially for each port, linearly increasing the delay. Could we optimize\nthis by asserting all reset GPIOs, waiting the pre-delay once, de-asserting\nall GPIOs, and waiting the post-delay once for the entire bus?\n```\n\nMaybe you should do:\n\n\tif (!list_empty(&bridge->ports) && !assert)\n\t\tmsleep(PCIE_T_PVPERL_MS);\n\n\tlist_for_each_entry(port, &bridge->ports, list) {\n\t\t...\n\t\tgpiod_direction_output(port->reset, 0);\n\t\t...\n\t}\n\n\tif (!list_empty(&bridge->ports) && !assert)\n\t\tmsleep(PCIE_RESET_CONFIG_WAIT_MS);\n\nAnd then this:\n\n```\nAlso, since this function is called from imx_pcie_resume_noirq, which\nexecutes with hardware interrupts disabled, does the use of msleep here\ntrigger a 'sleeping while atomic' bug?\n```\n\nThis is a valid concern. You should use mdelay(). But I'd recommend\nswitching to IRQ enabled callback, resume() instead. There is no complelling\nreason to use resume_noirq() in this driver and adding delays in noirq()\ncallbacks is not recommended as it may increase the overall system resume time.\n\nI will submit a separate series to convert dw_pcie_resume_noirq() and its\ncallers to IRQ enabled callbacks since this dw_pcie_resume_noirq() could\npotentially cause delay up to 1sec.\n\n> \t\t}\n> \t}\n> }\n> @@ -1249,8 +1284,25 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)\n> \tstruct dw_pcie *pci = to_dw_pcie_from_pp(pp);\n> \tstruct device *dev = pci->dev;\n> \tstruct imx_pcie *imx_pcie = to_imx_pcie(pci);\n> +\tstruct pci_host_bridge *bridge = pp->bridge;\n> \tint ret;\n> \n> +\tif (bridge && list_empty(&bridge->ports)) {\n> +\t\t/* Parse Root Port nodes if present */\n> +\t\tret = pci_host_common_parse_ports(dev, bridge);\n> +\t\tif (ret) {\n> +\t\t\tif (ret != -ENOENT) {\n> +\t\t\t\tdev_err(dev, \"Failed to parse Root Port nodes: %d\\n\", ret);\n> +\t\t\t\treturn ret;\n> +\t\t\t}\n> +\n> +\t\t\t/* Fallback to legacy binding for DT backwards compatibility */\n> +\t\t\tret = imx_pcie_parse_legacy_binding(imx_pcie);\n\nThis is also flagged by Sashiko:\n\n```\nCould this error handling corrupt the port state and trigger an invalid legacy\nfallback?\n\nIf a device tree defines multiple Root Ports and one lacks the optional\nreset GPIO, pci_host_common_parse_ports returns -ENOENT. This causes\nthe code to fall back to imx_pcie_parse_legacy_binding.\n\nSince the already-parsed child ports remain in bridge->ports without\nrollback, the legacy host bridge GPIO will be appended alongside them.\nValid child nodes are skipped, and both child and legacy GPIOs will be\ntoggled simultaneously.\n```\n\nYou should try to cleanup Root Port resources if pci_host_common_parse_ports()\nfails with -ENOENT.\n\n- Mani","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=n1VP5kih;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-52073-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"n1VP5kih\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fqnwZ5YLSz1xy1\n\tfor ; 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charset=utf-8","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":"<20260407104154.2842132-5-sherry.sun@nxp.com>"}},{"id":3674657,"web_url":"http://patchwork.ozlabs.org/comment/3674657/","msgid":"","list_archive_url":null,"date":"2026-04-08T08:34:03","subject":"RE: [PATCH V11 04/12] PCI: imx6: Add support for parsing the reset\n property in new Root Port binding","submitter":{"id":77063,"url":"http://patchwork.ozlabs.org/api/people/77063/","name":"Sherry Sun","email":"sherry.sun@nxp.com"},"content":"> On Tue, Apr 07, 2026 at 06:41:46PM +0800, Sherry Sun wrote:\n> > The current DT binding for pci-imx6 specifies the 'reset-gpios'\n> > property in the host bridge node. However, the PERST# signal logically\n> > belongs to individual Root Ports rather than the host bridge itself.\n> > This becomes important when supporting PCIe KeyE connector and PCI\n> > power control framework for pci-imx6 driver, which requires properties\n> > to be specified in Root Port nodes.\n> >\n> > Add support for parsing 'reset-gpios' from Root Port child nodes using\n> > the common helper pci_host_common_parse_ports(), and update the reset\n> > GPIO handling to use the parsed port list from bridge->ports. To\n> > maintain DT backwards compatibility, fallback to the legacy method of\n> > parsing the host bridge node if the reset property is not present in\n> > the Root Port node.\n> >\n> > Since now the reset GPIO is obtained with GPIOD_ASIS flag, it may be\n> > in input mode, using gpiod_direction_output() instead of\n> > gpiod_set_value_cansleep() to ensure the reset GPIO is properly\n> > configured as output before setting its value.\n> >\n> > Signed-off-by: Sherry Sun \n> > ---\n> > drivers/pci/controller/dwc/pci-imx6.c | 75\n> > +++++++++++++++++++++------\n> > 1 file changed, 60 insertions(+), 15 deletions(-)\n> >\n> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c\n> > b/drivers/pci/controller/dwc/pci-imx6.c\n> > index d99da7e42590..dd8f9c0fcec4 100644\n> > --- a/drivers/pci/controller/dwc/pci-imx6.c\n> > +++ b/drivers/pci/controller/dwc/pci-imx6.c\n> > @@ -34,6 +34,7 @@\n> > #include \n> >\n> > #include \"../../pci.h\"\n> > +#include \"../pci-host-common.h\"\n> > #include \"pcie-designware.h\"\n> >\n> > #define IMX8MQ_GPR_PCIE_REF_USE_PAD\t\tBIT(9)\n> > @@ -152,7 +153,6 @@ struct imx_lut_data {\n> >\n> > struct imx_pcie {\n> > \tstruct dw_pcie\t\t*pci;\n> > -\tstruct gpio_desc\t*reset_gpiod;\n> > \tstruct clk_bulk_data\t*clks;\n> > \tint\t\t\tnum_clks;\n> > \tbool\t\t\tsupports_clkreq;\n> > @@ -1224,6 +1224,32 @@ static void imx_pcie_disable_device(struct\n> pci_host_bridge *bridge,\n> > \timx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev)); }\n> >\n> > +static int imx_pcie_parse_legacy_binding(struct imx_pcie *pcie) {\n> > +\tstruct device *dev = pcie->pci->dev;\n> > +\tstruct pci_host_bridge *bridge = pcie->pci->pp.bridge;\n> > +\tstruct pci_host_port *port;\n> > +\tstruct gpio_desc *reset;\n> > +\n> > +\treset = devm_gpiod_get_optional(dev, \"reset\", GPIOD_ASIS);\n> > +\tif (IS_ERR(reset))\n> > +\t\treturn PTR_ERR(reset);\n> > +\n> > +\tif (!reset)\n> > +\t\treturn 0;\n> > +\n> > +\tport = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);\n> > +\tif (!port)\n> > +\t\treturn -ENOMEM;\n> > +\n> > +\tport->reset = reset;\n> > +\tINIT_LIST_HEAD(&port->list);\n> > +\tlist_add_tail(&port->list, &bridge->ports);\n> > +\n> > +\treturn devm_add_action_or_reset(dev,\n> pci_host_common_delete_ports,\n> > +\t\t\t\t\t&bridge->ports);\n> > +}\n> > +\n> > static void imx_pcie_vpcie_aux_disable(void *data) {\n> > \tstruct regulator *vpcie_aux = data;\n> > @@ -1233,13 +1259,22 @@ static void imx_pcie_vpcie_aux_disable(void\n> > *data)\n> >\n> > static void imx_pcie_assert_perst(struct imx_pcie *imx_pcie, bool\n> > assert) {\n> > -\tif (assert) {\n> > -\t\tgpiod_set_value_cansleep(imx_pcie->reset_gpiod, 1);\n> > -\t} else {\n> > -\t\tif (imx_pcie->reset_gpiod) {\n> > -\t\t\tmsleep(PCIE_T_PVPERL_MS);\n> > -\t\t\tgpiod_set_value_cansleep(imx_pcie->reset_gpiod, 0);\n> > -\t\t\tmsleep(PCIE_RESET_CONFIG_WAIT_MS);\n> > +\tstruct dw_pcie *pci = imx_pcie->pci;\n> > +\tstruct pci_host_bridge *bridge = pci->pp.bridge;\n> > +\tstruct pci_host_port *port;\n> > +\n> > +\tif (!bridge)\n> > +\t\treturn;\n> > +\n> > +\tlist_for_each_entry(port, &bridge->ports, list) {\n> > +\t\tif (assert) {\n> > +\t\t\tgpiod_direction_output(port->reset, 1);\n> > +\t\t} else {\n> > +\t\t\tif (port->reset) {\n> > +\t\t\t\tmsleep(PCIE_T_PVPERL_MS);\n> > +\t\t\t\tgpiod_direction_output(port->reset, 0);\n> > +\t\t\t\tmsleep(PCIE_RESET_CONFIG_WAIT_MS);\n> > +\t\t\t}\n> \n> Sashiko flagged this loop:\n> \n> ```\n> Does this loop multiply the initialization delays?\n> If a controller has multiple Root Ports, the msleep calls will run sequentially\n> for each port, linearly increasing the delay. Could we optimize this by\n> asserting all reset GPIOs, waiting the pre-delay once, de-asserting all GPIOs,\n> and waiting the post-delay once for the entire bus?\n> ```\n> \n> Maybe you should do:\n> \n> \tif (!list_empty(&bridge->ports) && !assert)\n> \t\tmsleep(PCIE_T_PVPERL_MS);\n> \n> \tlist_for_each_entry(port, &bridge->ports, list) {\n> \t\t...\n> \t\tgpiod_direction_output(port->reset, 0);\n> \t\t...\n> \t}\n> \n> \tif (!list_empty(&bridge->ports) && !assert)\n> \t\tmsleep(PCIE_RESET_CONFIG_WAIT_MS);\n> \n\nHi Mani, I think the code below looks clearer, is that ok for you?\n\n if (assert) {\n list_for_each_entry(port, &bridge->ports, list)\n gpiod_direction_output(port->reset, 1);\n } else {\n if (list_empty(&bridge->ports))\n return;\n\n msleep(PCIE_T_PVPERL_MS);\n list_for_each_entry(port, &bridge->ports, list)\n gpiod_direction_output(port->reset, 0);\n msleep(PCIE_RESET_CONFIG_WAIT_MS);\n }\n\n> And then this:\n> \n> ```\n> Also, since this function is called from imx_pcie_resume_noirq, which\n> executes with hardware interrupts disabled, does the use of msleep here\n> trigger a 'sleeping while atomic' bug?\n> ```\n> \n> This is a valid concern. You should use mdelay(). But I'd recommend switching\n> to IRQ enabled callback, resume() instead. There is no complelling reason to\n> use resume_noirq() in this driver and adding delays in noirq() callbacks is not\n> recommended as it may increase the overall system resume time.\n> \n> I will submit a separate series to convert dw_pcie_resume_noirq() and its\n> callers to IRQ enabled callbacks since this dw_pcie_resume_noirq() could\n> potentially cause delay up to 1sec.\n\nYes, this is not a new bug introduced by this patch. I agree we should covert the\nconvert dw_pcie_resume_noirq() and the caller to IRQ enabled callbacks to fix\nthis in a separate patch series.\nFor now, should I leave it as is, or switch to mdelay in this patch?\n\n> \n> > \t\t}\n> > \t}\n> > }\n> > @@ -1249,8 +1284,25 @@ static int imx_pcie_host_init(struct dw_pcie_rp\n> *pp)\n> > \tstruct dw_pcie *pci = to_dw_pcie_from_pp(pp);\n> > \tstruct device *dev = pci->dev;\n> > \tstruct imx_pcie *imx_pcie = to_imx_pcie(pci);\n> > +\tstruct pci_host_bridge *bridge = pp->bridge;\n> > \tint ret;\n> >\n> > +\tif (bridge && list_empty(&bridge->ports)) {\n> > +\t\t/* Parse Root Port nodes if present */\n> > +\t\tret = pci_host_common_parse_ports(dev, bridge);\n> > +\t\tif (ret) {\n> > +\t\t\tif (ret != -ENOENT) {\n> > +\t\t\t\tdev_err(dev, \"Failed to parse Root Port\n> nodes: %d\\n\", ret);\n> > +\t\t\t\treturn ret;\n> > +\t\t\t}\n> > +\n> > +\t\t\t/* Fallback to legacy binding for DT backwards\n> compatibility */\n> > +\t\t\tret = imx_pcie_parse_legacy_binding(imx_pcie);\n> \n> This is also flagged by Sashiko:\n> \n> ```\n> Could this error handling corrupt the port state and trigger an invalid legacy\n> fallback?\n> \n> If a device tree defines multiple Root Ports and one lacks the optional reset\n> GPIO, pci_host_common_parse_ports returns -ENOENT. This causes the code\n> to fall back to imx_pcie_parse_legacy_binding.\n> \n> Since the already-parsed child ports remain in bridge->ports without rollback,\n> the legacy host bridge GPIO will be appended alongside them.\n> Valid child nodes are skipped, and both child and legacy GPIOs will be toggled\n> simultaneously.\n> ```\n> \n> You should try to cleanup Root Port resources if\n> pci_host_common_parse_ports() fails with -ENOENT.\n\nSure, I will call pci_host_common_delete_ports() to clean up any partially parsed\nRoot Port resources before falling back to legacy binding.\n\nBest Regards\nSherry","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nxp.com header.i=@nxp.com header.a=rsa-sha256\n header.s=selector1 header.b=baRv+C85;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","X-OriginatorOrg":"nxp.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-AuthSource":"VI0PR04MB12114.eurprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n f81724b4-d89e-4f55-9a20-08de95499710","X-MS-Exchange-CrossTenant-originalarrivaltime":"08 Apr 2026 08:34:03.2687\n (UTC)","X-MS-Exchange-CrossTenant-fromentityheader":"Hosted","X-MS-Exchange-CrossTenant-id":"686ea1d3-bc2b-4c6f-a92c-d99c5c301635","X-MS-Exchange-CrossTenant-mailboxtype":"HOSTED","X-MS-Exchange-CrossTenant-userprincipalname":"\n EAD6ywCXfHDbO++P6QHyAm9w0YaF3WqyQW35aO2l9KHEwr1endMj2reKlRzMl3HCCQNKkFpuZCOFZEAEQdWbig==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"PA2PR04MB10375"}},{"id":3674791,"web_url":"http://patchwork.ozlabs.org/comment/3674791/","msgid":"","list_archive_url":null,"date":"2026-04-08T13:55:19","subject":"Re: [PATCH V11 04/12] PCI: imx6: Add support for parsing the reset\n property in new Root Port binding","submitter":{"id":78905,"url":"http://patchwork.ozlabs.org/api/people/78905/","name":"Manivannan Sadhasivam","email":"mani@kernel.org"},"content":"On Wed, Apr 08, 2026 at 08:34:03AM +0000, Sherry Sun wrote:\n> > On Tue, Apr 07, 2026 at 06:41:46PM +0800, Sherry Sun wrote:\n> > > The current DT binding for pci-imx6 specifies the 'reset-gpios'\n> > > property in the host bridge node. However, the PERST# signal logically\n> > > belongs to individual Root Ports rather than the host bridge itself.\n> > > This becomes important when supporting PCIe KeyE connector and PCI\n> > > power control framework for pci-imx6 driver, which requires properties\n> > > to be specified in Root Port nodes.\n> > >\n> > > Add support for parsing 'reset-gpios' from Root Port child nodes using\n> > > the common helper pci_host_common_parse_ports(), and update the reset\n> > > GPIO handling to use the parsed port list from bridge->ports. To\n> > > maintain DT backwards compatibility, fallback to the legacy method of\n> > > parsing the host bridge node if the reset property is not present in\n> > > the Root Port node.\n> > >\n> > > Since now the reset GPIO is obtained with GPIOD_ASIS flag, it may be\n> > > in input mode, using gpiod_direction_output() instead of\n> > > gpiod_set_value_cansleep() to ensure the reset GPIO is properly\n> > > configured as output before setting its value.\n> > >\n> > > Signed-off-by: Sherry Sun \n> > > ---\n> > > drivers/pci/controller/dwc/pci-imx6.c | 75\n> > > +++++++++++++++++++++------\n> > > 1 file changed, 60 insertions(+), 15 deletions(-)\n> > >\n> > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c\n> > > b/drivers/pci/controller/dwc/pci-imx6.c\n> > > index d99da7e42590..dd8f9c0fcec4 100644\n> > > --- a/drivers/pci/controller/dwc/pci-imx6.c\n> > > +++ b/drivers/pci/controller/dwc/pci-imx6.c\n> > > @@ -34,6 +34,7 @@\n> > > #include \n> > >\n> > > #include \"../../pci.h\"\n> > > +#include \"../pci-host-common.h\"\n> > > #include \"pcie-designware.h\"\n> > >\n> > > #define IMX8MQ_GPR_PCIE_REF_USE_PAD\t\tBIT(9)\n> > > @@ -152,7 +153,6 @@ struct imx_lut_data {\n> > >\n> > > struct imx_pcie {\n> > > \tstruct dw_pcie\t\t*pci;\n> > > -\tstruct gpio_desc\t*reset_gpiod;\n> > > \tstruct clk_bulk_data\t*clks;\n> > > \tint\t\t\tnum_clks;\n> > > \tbool\t\t\tsupports_clkreq;\n> > > @@ -1224,6 +1224,32 @@ static void imx_pcie_disable_device(struct\n> > pci_host_bridge *bridge,\n> > > \timx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev)); }\n> > >\n> > > +static int imx_pcie_parse_legacy_binding(struct imx_pcie *pcie) {\n> > > +\tstruct device *dev = pcie->pci->dev;\n> > > +\tstruct pci_host_bridge *bridge = pcie->pci->pp.bridge;\n> > > +\tstruct pci_host_port *port;\n> > > +\tstruct gpio_desc *reset;\n> > > +\n> > > +\treset = devm_gpiod_get_optional(dev, \"reset\", GPIOD_ASIS);\n> > > +\tif (IS_ERR(reset))\n> > > +\t\treturn PTR_ERR(reset);\n> > > +\n> > > +\tif (!reset)\n> > > +\t\treturn 0;\n> > > +\n> > > +\tport = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);\n> > > +\tif (!port)\n> > > +\t\treturn -ENOMEM;\n> > > +\n> > > +\tport->reset = reset;\n> > > +\tINIT_LIST_HEAD(&port->list);\n> > > +\tlist_add_tail(&port->list, &bridge->ports);\n> > > +\n> > > +\treturn devm_add_action_or_reset(dev,\n> > pci_host_common_delete_ports,\n> > > +\t\t\t\t\t&bridge->ports);\n> > > +}\n> > > +\n> > > static void imx_pcie_vpcie_aux_disable(void *data) {\n> > > \tstruct regulator *vpcie_aux = data;\n> > > @@ -1233,13 +1259,22 @@ static void imx_pcie_vpcie_aux_disable(void\n> > > *data)\n> > >\n> > > static void imx_pcie_assert_perst(struct imx_pcie *imx_pcie, bool\n> > > assert) {\n> > > -\tif (assert) {\n> > > -\t\tgpiod_set_value_cansleep(imx_pcie->reset_gpiod, 1);\n> > > -\t} else {\n> > > -\t\tif (imx_pcie->reset_gpiod) {\n> > > -\t\t\tmsleep(PCIE_T_PVPERL_MS);\n> > > -\t\t\tgpiod_set_value_cansleep(imx_pcie->reset_gpiod, 0);\n> > > -\t\t\tmsleep(PCIE_RESET_CONFIG_WAIT_MS);\n> > > +\tstruct dw_pcie *pci = imx_pcie->pci;\n> > > +\tstruct pci_host_bridge *bridge = pci->pp.bridge;\n> > > +\tstruct pci_host_port *port;\n> > > +\n> > > +\tif (!bridge)\n> > > +\t\treturn;\n> > > +\n> > > +\tlist_for_each_entry(port, &bridge->ports, list) {\n> > > +\t\tif (assert) {\n> > > +\t\t\tgpiod_direction_output(port->reset, 1);\n> > > +\t\t} else {\n> > > +\t\t\tif (port->reset) {\n> > > +\t\t\t\tmsleep(PCIE_T_PVPERL_MS);\n> > > +\t\t\t\tgpiod_direction_output(port->reset, 0);\n> > > +\t\t\t\tmsleep(PCIE_RESET_CONFIG_WAIT_MS);\n> > > +\t\t\t}\n> > \n> > Sashiko flagged this loop:\n> > \n> > ```\n> > Does this loop multiply the initialization delays?\n> > If a controller has multiple Root Ports, the msleep calls will run sequentially\n> > for each port, linearly increasing the delay. Could we optimize this by\n> > asserting all reset GPIOs, waiting the pre-delay once, de-asserting all GPIOs,\n> > and waiting the post-delay once for the entire bus?\n> > ```\n> > \n> > Maybe you should do:\n> > \n> > \tif (!list_empty(&bridge->ports) && !assert)\n> > \t\tmsleep(PCIE_T_PVPERL_MS);\n> > \n> > \tlist_for_each_entry(port, &bridge->ports, list) {\n> > \t\t...\n> > \t\tgpiod_direction_output(port->reset, 0);\n> > \t\t...\n> > \t}\n> > \n> > \tif (!list_empty(&bridge->ports) && !assert)\n> > \t\tmsleep(PCIE_RESET_CONFIG_WAIT_MS);\n> > \n> \n> Hi Mani, I think the code below looks clearer, is that ok for you?\n> \n> if (assert) {\n> list_for_each_entry(port, &bridge->ports, list)\n> gpiod_direction_output(port->reset, 1);\n> } else {\n> if (list_empty(&bridge->ports))\n> return;\n> \n\nThis check should be moved out of the if() condition. Other than this, the\nchange looks good.\n\n> msleep(PCIE_T_PVPERL_MS);\n> list_for_each_entry(port, &bridge->ports, list)\n> gpiod_direction_output(port->reset, 0);\n> msleep(PCIE_RESET_CONFIG_WAIT_MS);\n> }\n>\n> > And then this:\n> > \n> > ```\n> > Also, since this function is called from imx_pcie_resume_noirq, which\n> > executes with hardware interrupts disabled, does the use of msleep here\n> > trigger a 'sleeping while atomic' bug?\n> > ```\n> > \n> > This is a valid concern. You should use mdelay(). But I'd recommend switching\n> > to IRQ enabled callback, resume() instead. There is no complelling reason to\n> > use resume_noirq() in this driver and adding delays in noirq() callbacks is not\n> > recommended as it may increase the overall system resume time.\n> > \n> > I will submit a separate series to convert dw_pcie_resume_noirq() and its\n> > callers to IRQ enabled callbacks since this dw_pcie_resume_noirq() could\n> > potentially cause delay up to 1sec.\n> \n> Yes, this is not a new bug introduced by this patch. I agree we should covert the\n> convert dw_pcie_resume_noirq() and the caller to IRQ enabled callbacks to fix\n> this in a separate patch series.\n> For now, should I leave it as is, or switch to mdelay in this patch?\n> \n\nJust use mdelay() in your patch for now.\n\n- Mani","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=Xyh+eGOS;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-52157-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"Xyh+eGOS\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frPrb67w9z1xv0\n\tfor ; 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charset=utf-8","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":"\n "}},{"id":3675049,"web_url":"http://patchwork.ozlabs.org/comment/3675049/","msgid":"","list_archive_url":null,"date":"2026-04-09T02:40:26","subject":"RE: [PATCH V11 04/12] PCI: imx6: Add support for parsing the reset\n property in new Root Port binding","submitter":{"id":77063,"url":"http://patchwork.ozlabs.org/api/people/77063/","name":"Sherry Sun","email":"sherry.sun@nxp.com"},"content":"> Subject: Re: [PATCH V11 04/12] PCI: imx6: Add support for parsing the reset\n> property in new Root Port binding\n> \n> On Wed, Apr 08, 2026 at 08:34:03AM +0000, Sherry Sun wrote:\n> > > On Tue, Apr 07, 2026 at 06:41:46PM +0800, Sherry Sun wrote:\n> > > > The current DT binding for pci-imx6 specifies the 'reset-gpios'\n> > > > property in the host bridge node. However, the PERST# signal\n> > > > logically belongs to individual Root Ports rather than the host bridge\n> itself.\n> > > > This becomes important when supporting PCIe KeyE connector and PCI\n> > > > power control framework for pci-imx6 driver, which requires\n> > > > properties to be specified in Root Port nodes.\n> > > >\n> > > > Add support for parsing 'reset-gpios' from Root Port child nodes\n> > > > using the common helper pci_host_common_parse_ports(), and update\n> > > > the reset GPIO handling to use the parsed port list from\n> > > > bridge->ports. To maintain DT backwards compatibility, fallback to\n> > > > the legacy method of parsing the host bridge node if the reset\n> > > > property is not present in the Root Port node.\n> > > >\n> > > > Since now the reset GPIO is obtained with GPIOD_ASIS flag, it may\n> > > > be in input mode, using gpiod_direction_output() instead of\n> > > > gpiod_set_value_cansleep() to ensure the reset GPIO is properly\n> > > > configured as output before setting its value.\n> > > >\n> > > > Signed-off-by: Sherry Sun \n> > > > ---\n> > > > drivers/pci/controller/dwc/pci-imx6.c | 75\n> > > > +++++++++++++++++++++------\n> > > > 1 file changed, 60 insertions(+), 15 deletions(-)\n> > > >\n> > > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c\n> > > > b/drivers/pci/controller/dwc/pci-imx6.c\n> > > > index d99da7e42590..dd8f9c0fcec4 100644\n> > > > --- a/drivers/pci/controller/dwc/pci-imx6.c\n> > > > +++ b/drivers/pci/controller/dwc/pci-imx6.c\n> > > > @@ -34,6 +34,7 @@\n> > > > #include \n> > > >\n> > > > #include \"../../pci.h\"\n> > > > +#include \"../pci-host-common.h\"\n> > > > #include \"pcie-designware.h\"\n> > > >\n> > > > #define IMX8MQ_GPR_PCIE_REF_USE_PAD\t\tBIT(9)\n> > > > @@ -152,7 +153,6 @@ struct imx_lut_data {\n> > > >\n> > > > struct imx_pcie {\n> > > > \tstruct dw_pcie\t\t*pci;\n> > > > -\tstruct gpio_desc\t*reset_gpiod;\n> > > > \tstruct clk_bulk_data\t*clks;\n> > > > \tint\t\t\tnum_clks;\n> > > > \tbool\t\t\tsupports_clkreq;\n> > > > @@ -1224,6 +1224,32 @@ static void imx_pcie_disable_device(struct\n> > > pci_host_bridge *bridge,\n> > > > \timx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev)); }\n> > > >\n> > > > +static int imx_pcie_parse_legacy_binding(struct imx_pcie *pcie) {\n> > > > +\tstruct device *dev = pcie->pci->dev;\n> > > > +\tstruct pci_host_bridge *bridge = pcie->pci->pp.bridge;\n> > > > +\tstruct pci_host_port *port;\n> > > > +\tstruct gpio_desc *reset;\n> > > > +\n> > > > +\treset = devm_gpiod_get_optional(dev, \"reset\", GPIOD_ASIS);\n> > > > +\tif (IS_ERR(reset))\n> > > > +\t\treturn PTR_ERR(reset);\n> > > > +\n> > > > +\tif (!reset)\n> > > > +\t\treturn 0;\n> > > > +\n> > > > +\tport = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);\n> > > > +\tif (!port)\n> > > > +\t\treturn -ENOMEM;\n> > > > +\n> > > > +\tport->reset = reset;\n> > > > +\tINIT_LIST_HEAD(&port->list);\n> > > > +\tlist_add_tail(&port->list, &bridge->ports);\n> > > > +\n> > > > +\treturn devm_add_action_or_reset(dev,\n> > > pci_host_common_delete_ports,\n> > > > +\t\t\t\t\t&bridge->ports);\n> > > > +}\n> > > > +\n> > > > static void imx_pcie_vpcie_aux_disable(void *data) {\n> > > > \tstruct regulator *vpcie_aux = data; @@ -1233,13 +1259,22 @@\n> > > > static void imx_pcie_vpcie_aux_disable(void\n> > > > *data)\n> > > >\n> > > > static void imx_pcie_assert_perst(struct imx_pcie *imx_pcie, bool\n> > > > assert) {\n> > > > -\tif (assert) {\n> > > > -\t\tgpiod_set_value_cansleep(imx_pcie->reset_gpiod, 1);\n> > > > -\t} else {\n> > > > -\t\tif (imx_pcie->reset_gpiod) {\n> > > > -\t\t\tmsleep(PCIE_T_PVPERL_MS);\n> > > > -\t\t\tgpiod_set_value_cansleep(imx_pcie->reset_gpiod, 0);\n> > > > -\t\t\tmsleep(PCIE_RESET_CONFIG_WAIT_MS);\n> > > > +\tstruct dw_pcie *pci = imx_pcie->pci;\n> > > > +\tstruct pci_host_bridge *bridge = pci->pp.bridge;\n> > > > +\tstruct pci_host_port *port;\n> > > > +\n> > > > +\tif (!bridge)\n> > > > +\t\treturn;\n> > > > +\n> > > > +\tlist_for_each_entry(port, &bridge->ports, list) {\n> > > > +\t\tif (assert) {\n> > > > +\t\t\tgpiod_direction_output(port->reset, 1);\n> > > > +\t\t} else {\n> > > > +\t\t\tif (port->reset) {\n> > > > +\t\t\t\tmsleep(PCIE_T_PVPERL_MS);\n> > > > +\t\t\t\tgpiod_direction_output(port->reset, 0);\n> > > > +\t\t\t\tmsleep(PCIE_RESET_CONFIG_WAIT_MS);\n> > > > +\t\t\t}\n> > >\n> > > Sashiko flagged this loop:\n> > >\n> > > ```\n> > > Does this loop multiply the initialization delays?\n> > > If a controller has multiple Root Ports, the msleep calls will run\n> > > sequentially for each port, linearly increasing the delay. Could we\n> > > optimize this by asserting all reset GPIOs, waiting the pre-delay\n> > > once, de-asserting all GPIOs, and waiting the post-delay once for the entire\n> bus?\n> > > ```\n> > >\n> > > Maybe you should do:\n> > >\n> > > \tif (!list_empty(&bridge->ports) && !assert)\n> > > \t\tmsleep(PCIE_T_PVPERL_MS);\n> > >\n> > > \tlist_for_each_entry(port, &bridge->ports, list) {\n> > > \t\t...\n> > > \t\tgpiod_direction_output(port->reset, 0);\n> > > \t\t...\n> > > \t}\n> > >\n> > > \tif (!list_empty(&bridge->ports) && !assert)\n> > > \t\tmsleep(PCIE_RESET_CONFIG_WAIT_MS);\n> > >\n> >\n> > Hi Mani, I think the code below looks clearer, is that ok for you?\n> >\n> > if (assert) {\n> > list_for_each_entry(port, &bridge->ports, list)\n> > gpiod_direction_output(port->reset, 1);\n> > } else {\n> > if (list_empty(&bridge->ports))\n> > return;\n> >\n> \n> This check should be moved out of the if() condition. Other than this, the\n> change looks good.\n\nOk, will do.\n\n> \n> > msleep(PCIE_T_PVPERL_MS);\n> > list_for_each_entry(port, &bridge->ports, list)\n> > gpiod_direction_output(port->reset, 0);\n> > msleep(PCIE_RESET_CONFIG_WAIT_MS);\n> > }\n> >\n> > > And then this:\n> > >\n> > > ```\n> > > Also, since this function is called from imx_pcie_resume_noirq,\n> > > which executes with hardware interrupts disabled, does the use of\n> > > msleep here trigger a 'sleeping while atomic' bug?\n> > > ```\n> > >\n> > > This is a valid concern. You should use mdelay(). But I'd recommend\n> > > switching to IRQ enabled callback, resume() instead. There is no\n> > > complelling reason to use resume_noirq() in this driver and adding\n> > > delays in noirq() callbacks is not recommended as it may increase the\n> overall system resume time.\n> > >\n> > > I will submit a separate series to convert dw_pcie_resume_noirq()\n> > > and its callers to IRQ enabled callbacks since this\n> > > dw_pcie_resume_noirq() could potentially cause delay up to 1sec.\n> >\n> > Yes, this is not a new bug introduced by this patch. I agree we should\n> > covert the convert dw_pcie_resume_noirq() and the caller to IRQ\n> > enabled callbacks to fix this in a separate patch series.\n> > For now, should I leave it as is, or switch to mdelay in this patch?\n> >\n> \n> Just use mdelay() in your patch for now.\n\nOk, thanks!\n\nBest Regards\nSherry","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nxp.com header.i=@nxp.com header.a=rsa-sha256\n header.s=selector1 header.b=IdmABsWN;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-52186-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com\n header.b=\"IdmABsWN\"","smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=40.107.159.44","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=nxp.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=nxp.com","dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=nxp.com;"],"Received":["from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frkgn1p0mz1yCv\n\tfor ; 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