[{"id":3674301,"web_url":"http://patchwork.ozlabs.org/comment/3674301/","msgid":"<20260407-shown-guileless-5c8b8d94f5e5@spud>","list_archive_url":null,"date":"2026-04-07T16:29:51","subject":"Re: [PATCH v2 1/4] riscv: add UltraRISC SoC family Kconfig support","submitter":{"id":84372,"url":"http://patchwork.ozlabs.org/api/people/84372/","name":"Conor Dooley","email":"conor@kernel.org"},"content":"On Tue, Apr 07, 2026 at 10:40:52AM +0800, Jia Wang wrote:\n> The first SoC in the UltraRISC series is UR-DP1000, containing octa\n> UltraRISC C100 cores.\n\nNot gonna lie, I find it odd that pcie is where this platform starts\noff, but sure. What's the plan for adding the rest of the platform?\n\n> \n> Signed-off-by: Jia Wang \n> ---\n> arch/riscv/Kconfig.socs | 9 +++++++++\n> 1 file changed, 9 insertions(+)\n> \n> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs\n> index d621b85dd63b..98708569ec6a 100644\n> --- a/arch/riscv/Kconfig.socs\n> +++ b/arch/riscv/Kconfig.socs\n> @@ -84,6 +84,15 @@ config ARCH_THEAD\n> \thelp\n> \t This enables support for the RISC-V based T-HEAD SoCs.\n> \n> +config ARCH_ULTRARISC\n> +\tbool \"UltraRISC RISC-V SoCs\"\n> +\thelp\n> +\t This enables support for UltraRISC SoC platform hardware,\n> +\t including boards based on the UR-DP1000.\n\n> +\t UR-DP1000 is an 8-core 64-bit RISC-V SoC that supports\n> +\t the RV64GCBHX ISA. It supports Hardware Virtualization\n> +\t and RISC-V RV64 ISA H(v1.0) Extension.\n\nDelete this section IMO, doesn't provide any real value. Don't need nor\nwant the marketing brochure in the help text. The first sentence is\nsufficient.\n\n> +\n> config ARCH_VIRT\n> \tbool \"QEMU Virt Machine\"\n> \tselect POWER_RESET\n> \n> -- \n> 2.34.1\n>","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=OVjJ6aLB;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-52091-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"OVjJ6aLB\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fqsF40hqzz1xy1\n\tfor ; Wed, 08 Apr 2026 02:32:56 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 446773004C5E\n\tfor ; Tue, 7 Apr 2026 16:29:59 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 7D5A53BC676;\n\tTue, 7 Apr 2026 16:29:57 +0000 (UTC)","from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A8E43A4F3B;\n\tTue, 7 Apr 2026 16:29:57 +0000 (UTC)","by smtp.kernel.org (Postfix) with ESMTPSA id 8963AC116C6;\n\tTue, 7 Apr 2026 16:29:53 +0000 (UTC)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1775579397; cv=none;\n b=uQspyAKAkrAbzmyklVuTtU9a8Jrc6EJAHfZSHJ3M11hySZwRb8yWUpBFIhI16nGIy3ziLh3JWfAtNAY9d8DxOlqfB8ydUX6eBo9zsw9wQFHcm2WT9PzfisQdg9jiIcvZB5fVyhG/0AzMhTqzReUP4cQ8VOQjjKx0NrrwbtWmvxc=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1775579397; c=relaxed/simple;\n\tbh=Dm2vtAxO4d+eJhE657w6ZbaNu/kszM+d1xpoMi3ShtM=;\n\th=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:\n\t Content-Type:Content-Disposition:In-Reply-To;\n b=ok26ZYqEPRrHwOdC8VwP57ypnvhybRj6FSwdJYB1AAvjhByXXMWB3vF7oKw2+Zqp2rVaQ+xn095oMEaRC2hUmNjQSnLkjwgDl//mwmkTKppIQ+KJJkGBgXmcNJO7UNdyIBYO03Ntgpkai1aojmOqXs4HIbQ2v+sArxDvGcb7elk=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=OVjJ6aLB; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1775579396;\n\tbh=Dm2vtAxO4d+eJhE657w6ZbaNu/kszM+d1xpoMi3ShtM=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=OVjJ6aLB8LWYHohyrDKlzVQD9KCJ8rXEAt0/xlPLCMEFr0NSJwDW9Luabd1etR6q2\n\t d6fD5EBGRqvq9rvimcSVgvBVyMpqp8z2q6Ylnj5Cygaa70FjcvSyGluD9z2qvYRwtY\n\t zH1z4RbFgL4sQazZgIjqm4wV0Hr2g/EQvnnqX120lSL0X7k8yhWNVIukt86j72ME0M\n\t bpN3+UpPLGhZD/C+gmSIG/KVER1r1a7bThyw3q2uTXMM1h53x5uSqKesiNtFYyoUKK\n\t Lu5rzc+UT6pz75/aXHxkXGPQ+I8pPJ7ZF6jDxCqXOLNVUYBOJLUv/ag6guWSjEgyTc\n\t wJwiw9UfouBjQ==","Date":"Tue, 7 Apr 2026 17:29:51 +0100","From":"Conor Dooley ","To":"Jia Wang ","Cc":"Paul Walmsley , Palmer Dabbelt ,\n Albert Ou , Alexandre Ghiti ,\n Lorenzo Pieralisi , Krzysztof =?utf-8?q?Wilczy=C5=84?=\n\t=?utf-8?q?ski?= ,\n Manivannan Sadhasivam , Rob Herring ,\n Bjorn Helgaas , Jingoo Han ,\n Xincheng Zhang ,\n Krzysztof Kozlowski , Conor Dooley ,\n linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,\n linux-pci@vger.kernel.org, devicetree@vger.kernel.org","Subject":"Re: [PATCH v2 1/4] riscv: add UltraRISC SoC family Kconfig support","Message-ID":"<20260407-shown-guileless-5c8b8d94f5e5@spud>","References":"<20260407-ultrarisc-pcie-v2-0-2aa2a19a7fb3@ultrarisc.com>\n <20260407-ultrarisc-pcie-v2-1-2aa2a19a7fb3@ultrarisc.com>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha512;\n\tprotocol=\"application/pgp-signature\"; boundary=\"ipgBr6m3SknQlqBO\"","Content-Disposition":"inline","In-Reply-To":"<20260407-ultrarisc-pcie-v2-1-2aa2a19a7fb3@ultrarisc.com>"}},{"id":3674520,"web_url":"http://patchwork.ozlabs.org/comment/3674520/","msgid":"<177561282495.2731393.9548650582911498336.b4-reply@b4>","list_archive_url":null,"date":"2026-04-08T01:47:04","subject":"Re: [PATCH v2 1/4] riscv: add UltraRISC SoC family Kconfig support","submitter":{"id":92886,"url":"http://patchwork.ozlabs.org/api/people/92886/","name":"Jia Wang","email":"wangjia@ultrarisc.com"},"content":"On 2026-04-07 17:29 +0100, Conor Dooley wrote:\n> On Tue, Apr 07, 2026 at 10:40:52AM +0800, Jia Wang wrote:\n> > The first SoC in the UltraRISC series is UR-DP1000, containing octa\n> > UltraRISC C100 cores.\n> \n> Not gonna lie, I find it odd that pcie is where this platform starts\n> off, but sure. What's the plan for adding the rest of the platform?\n>\n\nHi Conor,\n\nThanks for the question.\n\nOur next step is to upstream the pinctrl driver together with the related\nDTS updates. The pinctrl series only affects the SoC’s low-speed peripheral\ninterfaces. For GMAC, SPI, I2C, and GPIO, we plan to use the existing\nkernel drivers, so no new controller drivers are needed \n> > \n> > Signed-off-by: Jia Wang \n> > ---\n> > arch/riscv/Kconfig.socs | 9 +++++++++\n> > 1 file changed, 9 insertions(+)\n> > \n> > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs\n> > index d621b85dd63b..98708569ec6a 100644\n> > --- a/arch/riscv/Kconfig.socs\n> > +++ b/arch/riscv/Kconfig.socs\n> > @@ -84,6 +84,15 @@ config ARCH_THEAD\n> > \thelp\n> > \t This enables support for the RISC-V based T-HEAD SoCs.\n> > \n> > +config ARCH_ULTRARISC\n> > +\tbool \"UltraRISC RISC-V SoCs\"\n> > +\thelp\n> > +\t This enables support for UltraRISC SoC platform hardware,\n> > +\t including boards based on the UR-DP1000.\n> \n> > +\t UR-DP1000 is an 8-core 64-bit RISC-V SoC that supports\n> > +\t the RV64GCBHX ISA. It supports Hardware Virtualization\n> > +\t and RISC-V RV64 ISA H(v1.0) Extension.\n> \n> Delete this section IMO, doesn't provide any real value. Don't need nor\n> want the marketing brochure in the help text. The first sentence is\n> sufficient.\n>\n\nI’ll drop the SoC description part from the Kconfig help text as you\nsuggested.\n \n> > +\n> > config ARCH_VIRT\n> > \tbool \"QEMU Virt Machine\"\n> > \tselect POWER_RESET\n> > \n> > -- \n> > 2.34.1\n> > \n\nBest regards,\nJia Wang","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ultrarisc.com header.i=@ultrarisc.com\n header.a=rsa-sha256 header.s=dkim header.b=gnxAX7Uu;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-52111-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=ultrarisc.com header.i=@ultrarisc.com\n header.b=\"gnxAX7Uu\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=218.76.62.146","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=ultrarisc.com","smtp.subspace.kernel.org;\n spf=none smtp.mailfrom=ultrarisc.com"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fr5bb6MLXz1xv0\n\tfor ; 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charset=\"utf-8\"","Content-Transfer-Encoding":"8bit","Subject":"Re: [PATCH v2 1/4] riscv: add UltraRISC SoC family Kconfig support","From":"Jia Wang ","To":"Conor Dooley ","Cc":"Jia Wang , Paul Walmsley ,\n Palmer Dabbelt , Albert Ou ,\n Alexandre Ghiti , Lorenzo Pieralisi ,\n\t=?utf-8?q?Krzysztof_Wilczy=C5=84ski?= ,\n Manivannan Sadhasivam , Rob Herring ,\n Bjorn Helgaas , Jingoo Han ,\n Xincheng Zhang ,\n Krzysztof Kozlowski ,\n Conor Dooley , linux-riscv@lists.infradead.org,\n linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,\n devicetree@vger.kernel.org","In-Reply-To":"<20260407-shown-guileless-5c8b8d94f5e5@spud>","References":"<20260407-ultrarisc-pcie-v2-0-2aa2a19a7fb3@ultrarisc.com>\n <20260407-ultrarisc-pcie-v2-1-2aa2a19a7fb3@ultrarisc.com>\n <20260407-shown-guileless-5c8b8d94f5e5@spud>","Date":"Wed, 08 Apr 2026 09:47:04 +0800","Message-Id":"<177561282495.2731393.9548650582911498336.b4-reply@b4>","X-Mailer":"b4 0.15-dev","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1775612825; 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What's the plan for adding the rest of the platform?\n> >\n> \n> Hi Conor,\n> \n> Thanks for the question.\n> \n> Our next step is to upstream the pinctrl driver together with the related\n> DTS updates. The pinctrl series only affects the SoC’s low-speed peripheral\n> interfaces. For GMAC, SPI, I2C, and GPIO, we plan to use the existing\n> kernel drivers, so no new controller drivers are needed \n\nAnd clocks? pinctrl and clocks would be the bare minimum level of\nsupport required before a platform should be merged. Obviously, you can\nget device drivers for PCI etc etc merged without clock drivers, but the\ninitial dts should contain the clocks too.\n\n> > > \n> > > Signed-off-by: Jia Wang \n> > > ---\n> > > arch/riscv/Kconfig.socs | 9 +++++++++\n> > > 1 file changed, 9 insertions(+)\n> > > \n> > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs\n> > > index d621b85dd63b..98708569ec6a 100644\n> > > --- a/arch/riscv/Kconfig.socs\n> > > +++ b/arch/riscv/Kconfig.socs\n> > > @@ -84,6 +84,15 @@ config ARCH_THEAD\n> > > \thelp\n> > > \t This enables support for the RISC-V based T-HEAD SoCs.\n> > > \n> > > +config ARCH_ULTRARISC\n> > > +\tbool \"UltraRISC RISC-V SoCs\"\n> > > +\thelp\n> > > +\t This enables support for UltraRISC SoC platform hardware,\n> > > +\t including boards based on the UR-DP1000.\n> > \n> > > +\t UR-DP1000 is an 8-core 64-bit RISC-V SoC that supports\n> > > +\t the RV64GCBHX ISA. It supports Hardware Virtualization\n> > > +\t and RISC-V RV64 ISA H(v1.0) Extension.\n> > \n> > Delete this section IMO, doesn't provide any real value. Don't need nor\n> > want the marketing brochure in the help text. The first sentence is\n> > sufficient.\n> >\n> \n> I’ll drop the SoC description part from the Kconfig help text as you\n> suggested.\n> \n> > > +\n> > > config ARCH_VIRT\n> > > \tbool \"QEMU Virt Machine\"\n> > > \tselect POWER_RESET\n> > > \n> > > -- \n> > > 2.34.1\n> > > \n> \n> Best regards,\n> Jia Wang\n>","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=dQyxn6a3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-52166-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"dQyxn6a3\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frV5n6hTxz1yD3\n\tfor ; Thu, 09 Apr 2026 03:13:49 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id CECC83016EF0\n\tfor ; Wed, 8 Apr 2026 17:10:34 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 0FFD635B658;\n\tWed, 8 Apr 2026 17:10:34 +0000 (UTC)","from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id E00A4346795;\n\tWed, 8 Apr 2026 17:10:33 +0000 (UTC)","by smtp.kernel.org (Postfix) with ESMTPSA id 721F8C19421;\n\tWed, 8 Apr 2026 17:10:30 +0000 (UTC)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1775668234; cv=none;\n b=URhBHLWbS7gcam3SL2wn3Eu9KPnhVXqnpt1pzde9qEJDlb+/M9tn+XRfv9RAo9ZUq6iSuqtEZuNsmWPl3Gglxa/5N1Sn/xF2w3sGCsrppHH6MJIS8YxTP+Tzms01Ysp1sBk1teURfw/b+dHgM/ExEkj+q4pMfu76ySGEW1rhNXU=","ARC-Message-Signature":"i=1; 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micalg=pgp-sha512;\n\tprotocol=\"application/pgp-signature\"; boundary=\"PAOwAJ1VswMSS1Ix\"","Content-Disposition":"inline","In-Reply-To":"<177561282495.2731393.9548650582911498336.b4-reply@b4>"}},{"id":3677015,"web_url":"http://patchwork.ozlabs.org/comment/3677015/","msgid":"<177613724276.4104287.2231755690464498119.b4-reply@b4>","list_archive_url":null,"date":"2026-04-14T03:27:22","subject":"Re: [PATCH v2 1/4] riscv: add UltraRISC SoC family Kconfig support","submitter":{"id":92886,"url":"http://patchwork.ozlabs.org/api/people/92886/","name":"Jia Wang","email":"wangjia@ultrarisc.com"},"content":"On 2026-04-08 18:10 +0100, Conor Dooley wrote:\n> On Wed, Apr 08, 2026 at 09:47:04AM +0800, Jia Wang wrote:\n> > On 2026-04-07 17:29 +0100, Conor Dooley wrote:\n> > > On Tue, Apr 07, 2026 at 10:40:52AM +0800, Jia Wang wrote:\n> > > > The first SoC in the UltraRISC series is UR-DP1000, containing octa\n> > > > UltraRISC C100 cores.\n> > > \n> > > Not gonna lie, I find it odd that pcie is where this platform starts\n> > > off, but sure. What's the plan for adding the rest of the platform?\n> > >\n> > \n> > Hi Conor,\n> > \n> > Thanks for the question.\n> > \n> > Our next step is to upstream the pinctrl driver together with the related\n> > DTS updates. The pinctrl series only affects the SoC’s low-speed peripheral\n> > interfaces. For GMAC, SPI, I2C, and GPIO, we plan to use the existing\n> > kernel drivers, so no new controller drivers are needed \n> \n> And clocks? pinctrl and clocks would be the bare minimum level of\n> support required before a platform should be merged. Obviously, you can\n> get device drivers for PCI etc etc merged without clock drivers, but the\n> initial dts should contain the clocks too.\n>\n\nOn our platform, all functional clocks are fully configured and enabled by\nthe firmware before Linux boots. The kernel is not expected to adjust clock\nrates or gate/ungate clocks at runtime. \nTherefore, in the initial device tree we only describe the fixed clocks\nrequired by the standard subsystem drivers, using `fixed-clock` where needed.\n\nSince there is no clock controller accessible to the OS, we do not plan to\nadd a clock driver at this stage. If future hardware versions expose a\nprogrammable clock controller to Linux, we will upstream the corresponding\ndriver and update the DT accordingly.\n \n> > > > \n> > > > Signed-off-by: Jia Wang \n> > > > ---\n> > > > arch/riscv/Kconfig.socs | 9 +++++++++\n> > > > 1 file changed, 9 insertions(+)\n> > > > \n> > > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs\n> > > > index d621b85dd63b..98708569ec6a 100644\n> > > > --- a/arch/riscv/Kconfig.socs\n> > > > +++ b/arch/riscv/Kconfig.socs\n> > > > @@ -84,6 +84,15 @@ config ARCH_THEAD\n> > > > \thelp\n> > > > \t This enables support for the RISC-V based T-HEAD SoCs.\n> > > > \n> > > > +config ARCH_ULTRARISC\n> > > > +\tbool \"UltraRISC RISC-V SoCs\"\n> > > > +\thelp\n> > > > +\t This enables support for UltraRISC SoC platform hardware,\n> > > > +\t including boards based on the UR-DP1000.\n> > > \n> > > > +\t UR-DP1000 is an 8-core 64-bit RISC-V SoC that supports\n> > > > +\t the RV64GCBHX ISA. It supports Hardware Virtualization\n> > > > +\t and RISC-V RV64 ISA H(v1.0) Extension.\n> > > \n> > > Delete this section IMO, doesn't provide any real value. Don't need nor\n> > > want the marketing brochure in the help text. The first sentence is\n> > > sufficient.\n> > >\n> > \n> > I’ll drop the SoC description part from the Kconfig help text as you\n> > suggested.\n> > \n> > > > +\n> > > > config ARCH_VIRT\n> > > > \tbool \"QEMU Virt Machine\"\n> > > > \tselect POWER_RESET\n> > > > \n> > > > -- \n> > > > 2.34.1\n> > > > \n> > \n> > Best regards,\n> > Jia Wang\n> >","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ultrarisc.com header.i=@ultrarisc.com\n header.a=rsa-sha256 header.s=dkim header.b=cqk0bxpZ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-52471-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=ultrarisc.com header.i=@ultrarisc.com\n header.b=\"cqk0bxpZ\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=218.76.62.146","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=ultrarisc.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=ultrarisc.com"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fvqX60Hk7z1xtJ\n\tfor ; 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charset=\"utf-8\"","Content-Transfer-Encoding":"8bit","Subject":"Re: [PATCH v2 1/4] riscv: add UltraRISC SoC family Kconfig support","From":"Jia Wang ","To":"Conor Dooley ","Cc":"Jia Wang , Paul Walmsley ,\n Palmer Dabbelt , Albert Ou ,\n Alexandre Ghiti , Lorenzo Pieralisi ,\n\t=?utf-8?q?Krzysztof_Wilczy=C5=84ski?= ,\n Manivannan Sadhasivam , Rob Herring ,\n Bjorn Helgaas , Jingoo Han ,\n Xincheng Zhang ,\n Krzysztof Kozlowski ,\n Conor Dooley , linux-riscv@lists.infradead.org,\n linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,\n devicetree@vger.kernel.org","In-Reply-To":"<20260408-wise-dividers-ec8a057d4bd2@spud>","References":"<20260407-ultrarisc-pcie-v2-0-2aa2a19a7fb3@ultrarisc.com>\n <20260407-ultrarisc-pcie-v2-1-2aa2a19a7fb3@ultrarisc.com>\n <20260407-shown-guileless-5c8b8d94f5e5@spud>\n <177561282495.2731393.9548650582911498336.b4-reply@b4>\n <20260408-wise-dividers-ec8a057d4bd2@spud>","Date":"Tue, 14 Apr 2026 11:27:22 +0800","Message-Id":"<177613724276.4104287.2231755690464498119.b4-reply@b4>","X-Mailer":"b4 0.15-dev","X-Developer-Signature":"v=1; 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