[{"id":3674384,"web_url":"http://patchwork.ozlabs.org/comment/3674384/","msgid":"<7166f802-fe21-4672-895a-3bb946c41a55@linaro.org>","list_archive_url":null,"date":"2026-04-07T19:23:25","subject":"Re: [PATCH v9 13/20] target/arm/tcg/translate.c: extract\n aarch64_translate_code()","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"content":"On 7/4/26 04:27, Pierrick Bouvier wrote:\n> This allows to get rid of TARGET_AARCH64, and helps with next patch\n> which will define at runtime tcg address type, by adding a second entry\n> point in a different source file.\n> \n> Suggested-by: Richard Henderson \n> Reviewed-by: Richard Henderson \n> Signed-off-by: Pierrick Bouvier \n> ---\n> target/arm/internals.h | 2 ++\n> target/arm/tcg/stubs32.c | 7 +++++++\n> target/arm/tcg/translate-a64.c | 8 ++++++++\n> target/arm/tcg/translate.c | 18 ++++++++----------\n> 4 files changed, 25 insertions(+), 10 deletions(-)\n\n\n> diff --git a/target/arm/tcg/stubs32.c b/target/arm/tcg/stubs32.c\n> index c5a0bc61f47..3945dc49e5e 100644\n> --- a/target/arm/tcg/stubs32.c\n> +++ b/target/arm/tcg/stubs32.c\n> @@ -3,6 +3,7 @@\n> */\n> \n> #include \"qemu/osdep.h\"\n> +#include \"target/arm/internals.h\"\n> #include \"target/arm/tcg/translate.h\"\n> \n> \n> @@ -15,3 +16,9 @@ void a64_translate_init(void)\n> {\n> /* Don't initialize for 32 bits. Call site will be fixed later. */\n> }\n> +\n> +void aarch64_translate_code(CPUState *cs, TranslationBlock *tb,\n> + int *max_insns, vaddr pc, void *host_pc)\n> +{\n> + g_assert_not_reached();\n> +}\n> diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\n> index 35ad7530c4b..c5af26e2b7e 100644\n> --- a/target/arm/tcg/translate-a64.c\n> +++ b/target/arm/tcg/translate-a64.c\n> @@ -10949,3 +10949,11 @@ const TranslatorOps aarch64_translator_ops = {\n> .translate_insn = aarch64_tr_translate_insn,\n> .tb_stop = aarch64_tr_tb_stop,\n> };\n> +\n\nPlease get translator_loop() declaration with explicit:\n\n#include \"exec/translator.h\"\n\n> +void aarch64_translate_code(CPUState *cpu, TranslationBlock *tb,\n> + int *max_insns, vaddr pc, void *host_pc)\n> +{\n> + DisasContext dc = {};\n\n> + translator_loop(cpu, tb, max_insns, pc, host_pc,\n> + &aarch64_translator_ops, &dc.base);\n> +}\n> diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\n> index 204f9657993..0597c9d4bed 100644\n> --- a/target/arm/tcg/translate.c\n> +++ b/target/arm/tcg/translate.c\n> @@ -6878,18 +6878,16 @@ static const TranslatorOps thumb_translator_ops = {\n\nDitto (pre-existing):\n\n#include \"exec/translator.h\"\n\n> void arm_translate_code(CPUState *cpu, TranslationBlock *tb,\n> int *max_insns, vaddr pc, void *host_pc)\n> {\n> - DisasContext dc = { };\n> - const TranslatorOps *ops = &arm_translator_ops;\n> CPUARMTBFlags tb_flags = arm_tbflags_from_tb(tb);\n> \n> - if (EX_TBFLAG_AM32(tb_flags, THUMB)) {\n> - ops = &thumb_translator_ops;\n> - }\n> -#ifdef TARGET_AARCH64\n> if (EX_TBFLAG_ANY(tb_flags, AARCH64_STATE)) {\n> - ops = &aarch64_translator_ops;\n> + aarch64_translate_code(cpu, tb, max_insns, pc, host_pc);\n> + } else {\n> + DisasContext dc = { };\n> + translator_loop(cpu, tb, max_insns, pc, host_pc,\n> + (EX_TBFLAG_AM32(tb_flags, THUMB)\n> + ? &thumb_translator_ops\n> + : &arm_translator_ops),\n> + &dc.base);\n> }\n> -#endif\n> -\n> - translator_loop(cpu, tb, max_insns, pc, host_pc, ops, &dc.base);\n> }","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=mCF/s2y6;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::332;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3674454,"web_url":"http://patchwork.ozlabs.org/comment/3674454/","msgid":"<4beca66b-a3e1-4480-8830-d548c2b06670@linaro.org>","list_archive_url":null,"date":"2026-04-07T19:53:11","subject":"Re: [PATCH v9 13/20] target/arm/tcg/translate.c: extract\n aarch64_translate_code()","submitter":{"id":85798,"url":"http://patchwork.ozlabs.org/api/people/85798/","name":"Pierrick Bouvier","email":"pierrick.bouvier@linaro.org"},"content":"On 4/7/26 12:23 PM, Philippe Mathieu-Daudé wrote:\n> On 7/4/26 04:27, Pierrick Bouvier wrote:\n>> This allows to get rid of TARGET_AARCH64, and helps with next patch\n>> which will define at runtime tcg address type, by adding a second entry\n>> point in a different source file.\n>>\n>> Suggested-by: Richard Henderson \n>> Reviewed-by: Richard Henderson \n>> Signed-off-by: Pierrick Bouvier \n>> ---\n>> target/arm/internals.h | 2 ++\n>> target/arm/tcg/stubs32.c | 7 +++++++\n>> target/arm/tcg/translate-a64.c | 8 ++++++++\n>> target/arm/tcg/translate.c | 18 ++++++++----------\n>> 4 files changed, 25 insertions(+), 10 deletions(-)\n> \n> \n>> diff --git a/target/arm/tcg/stubs32.c b/target/arm/tcg/stubs32.c\n>> index c5a0bc61f47..3945dc49e5e 100644\n>> --- a/target/arm/tcg/stubs32.c\n>> +++ b/target/arm/tcg/stubs32.c\n>> @@ -3,6 +3,7 @@\n>> */\n>> \n>> #include \"qemu/osdep.h\"\n>> +#include \"target/arm/internals.h\"\n>> #include \"target/arm/tcg/translate.h\"\n>> \n>> \n>> @@ -15,3 +16,9 @@ void a64_translate_init(void)\n>> {\n>> /* Don't initialize for 32 bits. Call site will be fixed later. */\n>> }\n>> +\n>> +void aarch64_translate_code(CPUState *cs, TranslationBlock *tb,\n>> + int *max_insns, vaddr pc, void *host_pc)\n>> +{\n>> + g_assert_not_reached();\n>> +}\n>> diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\n>> index 35ad7530c4b..c5af26e2b7e 100644\n>> --- a/target/arm/tcg/translate-a64.c\n>> +++ b/target/arm/tcg/translate-a64.c\n>> @@ -10949,3 +10949,11 @@ const TranslatorOps aarch64_translator_ops = {\n>> .translate_insn = aarch64_tr_translate_insn,\n>> .tb_stop = aarch64_tr_tb_stop,\n>> };\n>> +\n> \n> Please get translator_loop() declaration with explicit:\n> \n> #include \"exec/translator.h\"\n>\n\nDone.\n\n>> +void aarch64_translate_code(CPUState *cpu, TranslationBlock *tb,\n>> + int *max_insns, vaddr pc, void *host_pc)\n>> +{\n>> + DisasContext dc = {};\n> \n>> + translator_loop(cpu, tb, max_insns, pc, host_pc,\n>> + &aarch64_translator_ops, &dc.base);\n>> +}\n>> diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\n>> index 204f9657993..0597c9d4bed 100644\n>> --- a/target/arm/tcg/translate.c\n>> +++ b/target/arm/tcg/translate.c\n>> @@ -6878,18 +6878,16 @@ static const TranslatorOps thumb_translator_ops = {\n> \n> Ditto (pre-existing):\n> \n> #include \"exec/translator.h\"\n>\n\nDone.\n\n>> void arm_translate_code(CPUState *cpu, TranslationBlock *tb,\n>> int *max_insns, vaddr pc, void *host_pc)\n>> {\n>> - DisasContext dc = { };\n>> - const TranslatorOps *ops = &arm_translator_ops;\n>> CPUARMTBFlags tb_flags = arm_tbflags_from_tb(tb);\n>> \n>> - if (EX_TBFLAG_AM32(tb_flags, THUMB)) {\n>> - ops = &thumb_translator_ops;\n>> - }\n>> -#ifdef TARGET_AARCH64\n>> if (EX_TBFLAG_ANY(tb_flags, AARCH64_STATE)) {\n>> - ops = &aarch64_translator_ops;\n>> + aarch64_translate_code(cpu, tb, max_insns, pc, host_pc);\n>> + } else {\n>> + DisasContext dc = { };\n>> + translator_loop(cpu, tb, max_insns, pc, host_pc,\n>> + (EX_TBFLAG_AM32(tb_flags, THUMB)\n>> + ? &thumb_translator_ops\n>> + : &arm_translator_ops),\n>> + &dc.base);\n>> }\n>> -#endif\n>> -\n>> - translator_loop(cpu, tb, max_insns, pc, host_pc, ops, &dc.base);\n>> }\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Tt1WaHsw;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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