[{"id":3676602,"web_url":"http://patchwork.ozlabs.org/comment/3676602/","msgid":"","list_archive_url":null,"date":"2026-04-13T09:35:47","subject":"Re: [PATCH v21 2/6] pwm: driver for qualcomm ipq6018 pwm block","submitter":{"id":88416,"url":"http://patchwork.ozlabs.org/api/people/88416/","name":"Uwe Kleine-König","email":"ukleinek@kernel.org"},"content":"Hello,\n\nOn Mon, Apr 06, 2026 at 10:24:39PM +0200, George Moussalem via B4 Relay wrote:\n> From: Devi Priya \n> \n> Driver for the PWM block in Qualcomm IPQ6018 line of SoCs. Based on\n> driver from downstream Codeaurora kernel tree. Removed support for older\n> (V1) variants because I have no access to that hardware.\n> \n> Tested on IPQ5018 and IPQ6010 based hardware.\n> \n> Co-developed-by: Baruch Siach \n> Signed-off-by: Baruch Siach \n> Signed-off-by: Devi Priya \n> Reviewed-by: Bjorn Andersson \n> Signed-off-by: George Moussalem \n\nI have a few remaining nitpicks. If you're ok I'll squash the following\ndiff into this patch and apply it:\n\ndiff --git a/drivers/pwm/pwm-ipq.c b/drivers/pwm/pwm-ipq.c\nindex b79e5e457d1a..65af19ded72c 100644\n--- a/drivers/pwm/pwm-ipq.c\n+++ b/drivers/pwm/pwm-ipq.c\n@@ -2,7 +2,7 @@\n /*\n * Copyright (c) 2016-2017, 2020 The Linux Foundation. All rights reserved.\n *\n- * Hardware notes / Limitations:\n+ * Limitations:\n * - The PWM controller has no publicly available datasheet.\n * - Each of the four channels is programmed via two 32-bit registers\n * (REG0 and REG1 at 8-byte stride).\n\nThis is to make\n\n\tsed -rn '/Limitations:/,/\\*\\/?$/p' drivers/pwm/*.c\n\ndo the right thing. I know \"Limitations\" isn't a good subject for this,\nbut until I come around to pick a better marker, doing the same in all\ndrivers is good.\n\n@@ -44,13 +44,6 @@\n \n #define IPQ_PWM_REG1\t\t\t4\n #define IPQ_PWM_REG1_PRE_DIV\t\tGENMASK(15, 0)\n-\n-/*\n- * The max value specified for each field is based on the number of bits\n- * in the pwm control register for that field (16-bit)\n- */\n-#define IPQ_PWM_MAX_DIV\t\t\tFIELD_MAX(IPQ_PWM_REG0_PWM_DIV)\n-\n /*\n * Enable bit is set to enable output toggling in pwm device.\n * Update bit is set to trigger the change and is unset automatically\n@@ -59,6 +52,12 @@\n #define IPQ_PWM_REG1_UPDATE\t\tBIT(30)\n #define IPQ_PWM_REG1_ENABLE\t\tBIT(31)\n \n+/*\n+ * The max value specified for each field is based on the number of bits\n+ * in the pwm control register for that field (16-bit)\n+ */\n+#define IPQ_PWM_MAX_DIV\t\t\tFIELD_MAX(IPQ_PWM_REG0_PWM_DIV)\n+\n struct ipq_pwm_chip {\n \tvoid __iomem *mem;\n \tunsigned long clk_rate;\n\nThis is just about ordering definitions taken 1:1 from the manual before\ndriver specific stuff.\n\n@@ -95,6 +94,12 @@ static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,\n \tunsigned long val = 0;\n \tunsigned long hi_dur;\n \n+\tif (!state->enabled) {\n+\t\t/* clear IPQ_PWM_REG1_ENABLE */\n+\t\tipq_pwm_reg_write(pwm, IPQ_PWM_REG1, IPQ_PWM_REG1_UPDATE);\n+\t\treturn 0;\n+\t}\n+\n \tif (state->polarity != PWM_POLARITY_NORMAL)\n \t\treturn -EINVAL;\n \nThis ensures that the PWM can be disabled even if state->polarity is\nbogus or period and duty_cycle are out of range.\n\n@@ -102,7 +107,8 @@ static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,\n \t * Check the upper and lower bounds for the period as per\n \t * hardware limits\n \t */\n-\tperiod_ns = max(state->period, IPQ_PWM_MIN_PERIOD_NS);\n+\tif (state->period < IPQ_PWM_MIN_PERIOD_NS)\n+\t\treturn -ERANGE;\n \tperiod_ns = min(state->period, IPQ_PWM_MAX_PERIOD_NS);\n \tduty_ns = min(state->duty_cycle, period_ns);\n \nThis is about correctness. A driver is expected to never configure a\nhigher value than requested. (And otherwise I would have converted that\nto clamp().)\n\n@@ -134,7 +140,7 @@ static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,\n \n \t/* pwm duty = HI_DUR * (PRE_DIV + 1) / clk_rate */\n \thi_dur = mul_u64_u64_div_u64(duty_ns, ipq_chip->clk_rate,\n-\t\t\t\t (u64)(pre_div + 1) * NSEC_PER_SEC);\n+\t\t\t\t (u64)NSEC_PER_SEC * (pre_div + 1));\n \n \tval = FIELD_PREP(IPQ_PWM_REG0_HI_DURATION, hi_dur) |\n \t\tFIELD_PREP(IPQ_PWM_REG0_PWM_DIV, pwm_div);\n\nJust consistency with the period calculation\n\n@@ -144,9 +150,7 @@ static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,\n \tipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val);\n \n \t/* PWM enable toggle needs a separate write to REG1 */\n-\tval |= IPQ_PWM_REG1_UPDATE;\n-\tif (state->enabled)\n-\t\tval |= IPQ_PWM_REG1_ENABLE;\n+\tval |= IPQ_PWM_REG1_UPDATE | IPQ_PWM_REG1_ENABLE;\n \tipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val);\n \n \treturn 0;\n\nSimplification that is possible after checking for state->enabled early.\n\n@@ -174,7 +178,7 @@ static int ipq_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,\n \thi_dur = FIELD_GET(IPQ_PWM_REG0_HI_DURATION, reg0);\n \tpre_div = FIELD_GET(IPQ_PWM_REG1_PRE_DIV, reg1);\n \n-\teffective_div = (u64)(pre_div + 1) * (pwm_div + 1);\n+\teffective_div = (u64)(pwm_div + 1) * (pre_div + 1)\n \n \t/*\n \t * effective_div <= 0x100000000, so the multiplication doesn't overflow.\n\nAgain consistency.\n\nA nice followup for this patch would be the conversion to the waveform\nAPI; just in case you're still motivated to work on this driver :-)\n\nBest regards\nUwe","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=bx+8O1xs;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pwm+bounces-8567-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"bx+8O1xs\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fvMlD5sYkz1yDF\n\tfor ; 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micalg=pgp-sha512;\n\tprotocol=\"application/pgp-signature\"; boundary=\"5u5li7rew6iszz66\"","Content-Disposition":"inline","In-Reply-To":"<20260406-ipq-pwm-v21-2-6ed1e868e4c2@outlook.com>"}},{"id":3676887,"web_url":"http://patchwork.ozlabs.org/comment/3676887/","msgid":"","list_archive_url":null,"date":"2026-04-13T19:17:18","subject":"Re: [PATCH v21 2/6] pwm: driver for qualcomm ipq6018 pwm block","submitter":{"id":90319,"url":"http://patchwork.ozlabs.org/api/people/90319/","name":"George Moussalem","email":"george.moussalem@outlook.com"},"content":"Hello\n\nOn 4/13/2026 1:35 PM, Uwe Kleine-König wrote:\n> Hello,\n> \n> On Mon, Apr 06, 2026 at 10:24:39PM +0200, George Moussalem via B4 Relay wrote:\n>> From: Devi Priya \n>>\n>> Driver for the PWM block in Qualcomm IPQ6018 line of SoCs. Based on\n>> driver from downstream Codeaurora kernel tree. Removed support for older\n>> (V1) variants because I have no access to that hardware.\n>>\n>> Tested on IPQ5018 and IPQ6010 based hardware.\n>>\n>> Co-developed-by: Baruch Siach \n>> Signed-off-by: Baruch Siach \n>> Signed-off-by: Devi Priya \n>> Reviewed-by: Bjorn Andersson \n>> Signed-off-by: George Moussalem \n> \n> I have a few remaining nitpicks. If you're ok I'll squash the following\n> diff into this patch and apply it:\n\nJust applied it to my own branch, all okay from my side. Thanks for your\nguidance and support!\n\n> \n> diff --git a/drivers/pwm/pwm-ipq.c b/drivers/pwm/pwm-ipq.c\n> index b79e5e457d1a..65af19ded72c 100644\n> --- a/drivers/pwm/pwm-ipq.c\n> +++ b/drivers/pwm/pwm-ipq.c\n> @@ -2,7 +2,7 @@\n> /*\n> * Copyright (c) 2016-2017, 2020 The Linux Foundation. All rights reserved.\n> *\n> - * Hardware notes / Limitations:\n> + * Limitations:\n> * - The PWM controller has no publicly available datasheet.\n> * - Each of the four channels is programmed via two 32-bit registers\n> * (REG0 and REG1 at 8-byte stride).\n> \n> This is to make\n> \n> \tsed -rn '/Limitations:/,/\\*\\/?$/p' drivers/pwm/*.c\n> \n> do the right thing. I know \"Limitations\" isn't a good subject for this,\n> but until I come around to pick a better marker, doing the same in all\n> drivers is good.\n> \n> @@ -44,13 +44,6 @@\n> \n> #define IPQ_PWM_REG1\t\t\t4\n> #define IPQ_PWM_REG1_PRE_DIV\t\tGENMASK(15, 0)\n> -\n> -/*\n> - * The max value specified for each field is based on the number of bits\n> - * in the pwm control register for that field (16-bit)\n> - */\n> -#define IPQ_PWM_MAX_DIV\t\t\tFIELD_MAX(IPQ_PWM_REG0_PWM_DIV)\n> -\n> /*\n> * Enable bit is set to enable output toggling in pwm device.\n> * Update bit is set to trigger the change and is unset automatically\n> @@ -59,6 +52,12 @@\n> #define IPQ_PWM_REG1_UPDATE\t\tBIT(30)\n> #define IPQ_PWM_REG1_ENABLE\t\tBIT(31)\n> \n> +/*\n> + * The max value specified for each field is based on the number of bits\n> + * in the pwm control register for that field (16-bit)\n> + */\n> +#define IPQ_PWM_MAX_DIV\t\t\tFIELD_MAX(IPQ_PWM_REG0_PWM_DIV)\n> +\n> struct ipq_pwm_chip {\n> \tvoid __iomem *mem;\n> \tunsigned long clk_rate;\n> \n> This is just about ordering definitions taken 1:1 from the manual before\n> driver specific stuff.\n> \n> @@ -95,6 +94,12 @@ static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,\n> \tunsigned long val = 0;\n> \tunsigned long hi_dur;\n> \n> +\tif (!state->enabled) {\n> +\t\t/* clear IPQ_PWM_REG1_ENABLE */\n> +\t\tipq_pwm_reg_write(pwm, IPQ_PWM_REG1, IPQ_PWM_REG1_UPDATE);\n> +\t\treturn 0;\n> +\t}\n> +\n> \tif (state->polarity != PWM_POLARITY_NORMAL)\n> \t\treturn -EINVAL;\n> \n> This ensures that the PWM can be disabled even if state->polarity is\n> bogus or period and duty_cycle are out of range.\n> \n> @@ -102,7 +107,8 @@ static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,\n> \t * Check the upper and lower bounds for the period as per\n> \t * hardware limits\n> \t */\n> -\tperiod_ns = max(state->period, IPQ_PWM_MIN_PERIOD_NS);\n> +\tif (state->period < IPQ_PWM_MIN_PERIOD_NS)\n> +\t\treturn -ERANGE;\n> \tperiod_ns = min(state->period, IPQ_PWM_MAX_PERIOD_NS);\n> \tduty_ns = min(state->duty_cycle, period_ns);\n> \n> This is about correctness. A driver is expected to never configure a\n> higher value than requested. (And otherwise I would have converted that\n> to clamp().)\n> \n> @@ -134,7 +140,7 @@ static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,\n> \n> \t/* pwm duty = HI_DUR * (PRE_DIV + 1) / clk_rate */\n> \thi_dur = mul_u64_u64_div_u64(duty_ns, ipq_chip->clk_rate,\n> -\t\t\t\t (u64)(pre_div + 1) * NSEC_PER_SEC);\n> +\t\t\t\t (u64)NSEC_PER_SEC * (pre_div + 1));\n> \n> \tval = FIELD_PREP(IPQ_PWM_REG0_HI_DURATION, hi_dur) |\n> \t\tFIELD_PREP(IPQ_PWM_REG0_PWM_DIV, pwm_div);\n> \n> Just consistency with the period calculation\n> \n> @@ -144,9 +150,7 @@ static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,\n> \tipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val);\n> \n> \t/* PWM enable toggle needs a separate write to REG1 */\n> -\tval |= IPQ_PWM_REG1_UPDATE;\n> -\tif (state->enabled)\n> -\t\tval |= IPQ_PWM_REG1_ENABLE;\n> +\tval |= IPQ_PWM_REG1_UPDATE | IPQ_PWM_REG1_ENABLE;\n> \tipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val);\n> \n> \treturn 0;\n> \n> Simplification that is possible after checking for state->enabled early.\n> \n> @@ -174,7 +178,7 @@ static int ipq_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,\n> \thi_dur = FIELD_GET(IPQ_PWM_REG0_HI_DURATION, reg0);\n> \tpre_div = FIELD_GET(IPQ_PWM_REG1_PRE_DIV, reg1);\n> \n> -\teffective_div = (u64)(pre_div + 1) * (pwm_div + 1);\n> +\teffective_div = (u64)(pwm_div + 1) * (pre_div + 1)\n> \n> \t/*\n> \t * effective_div <= 0x100000000, so the multiplication doesn't overflow.\n> \n> Again consistency.\n> \n> A nice followup for this patch would be the conversion to the waveform\n> API; just in case you're still motivated to work on this driver :-)\n> \n> Best regards\n> Uwe\n\nBest regards,\nGeorge","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=outlook.com header.i=@outlook.com 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PM, Uwe Kleine-König wrote:\n> > On Mon, Apr 06, 2026 at 10:24:39PM +0200, George Moussalem via B4 Relay wrote:\n> >> From: Devi Priya \n> >>\n> >> Driver for the PWM block in Qualcomm IPQ6018 line of SoCs. Based on\n> >> driver from downstream Codeaurora kernel tree. Removed support for older\n> >> (V1) variants because I have no access to that hardware.\n> >>\n> >> Tested on IPQ5018 and IPQ6010 based hardware.\n> >>\n> >> Co-developed-by: Baruch Siach \n> >> Signed-off-by: Baruch Siach \n> >> Signed-off-by: Devi Priya \n> >> Reviewed-by: Bjorn Andersson \n> >> Signed-off-by: George Moussalem \n> > \n> > I have a few remaining nitpicks. If you're ok I'll squash the following\n> > diff into this patch and apply it:\n> \n> Just applied it to my own branch, all okay from my side. Thanks for your\n> guidance and support!\n\nI did that and added a ; to make the compiler happy. It is now contained\nat\nhttps://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux.git pwm/for-nexxt\nas 7.2-rc1 material. I'll push it into next after the merge window\ncloses in ~ two weeks.\n\nBest regards and thanks for work\nUwe","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=mWzZNZY7;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pwm+bounces-8571-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"mWzZNZY7\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fvfBQ31Fhz1xtJ\n\tfor ; Tue, 14 Apr 2026 06:28:46 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id BD0E1301FA5B\n\tfor ; Mon, 13 Apr 2026 20:27:37 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id E17D339478E;\n\tMon, 13 Apr 2026 20:27:36 +0000 (UTC)","from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id BC054393DE0;\n\tMon, 13 Apr 2026 20:27:36 +0000 (UTC)","by smtp.kernel.org (Postfix) with ESMTPSA id 086CAC2BCAF;\n\tMon, 13 Apr 2026 20:27:35 +0000 (UTC)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776112056; cv=none;\n b=oiB6FzbfsfxXoVR6gJu1eU6dKMKyb8q/msrx2XoS+C2nbd7Qu3E4ZgqklanxFK4nK8gTh/xjE2SxsgWEx8f2HH8AvN8C2l4pekrLqI7I/82qqgujHwTxIX90lo0AY82Rbr7bMINBhVnEg0D+CmQrvM98Tj62/vZj3wL+djO3Flo=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776112056; c=relaxed/simple;\n\tbh=6yofSQLj+gW5ePwKJizrWlHOQntWXc7yHgiMuUR/QC4=;\n\th=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:\n\t Content-Type:Content-Disposition:In-Reply-To;\n b=DzEP73cQpUJpcBpXL8i2UR/GOGrP3EdjfIwM8hIjnG/uNBA5UkMHUjEpOhjlAUJZU8Xc6jNai3iB4bgG1hOUHzTDWJW1ApwS6f8K8vj8hEN7byzTHgGwzVXVSZUmI8nOlfLoI3O6rKuUnHskKeqk6JMJe7Bt8F410AEO2XQVagE=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=mWzZNZY7; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1776112056;\n\tbh=6yofSQLj+gW5ePwKJizrWlHOQntWXc7yHgiMuUR/QC4=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=mWzZNZY7tBqVHisz5/TAuMVz5TwYyVIrJsX2ylAlDYRVokTuIo5Bszo7eLA4Qynxp\n\t lxS1eKsHMcVwYP52rBrfR27Pa4yrhzLJHiESqYKIoA0fVWL+ro0SPvkTiRY9VM2+0p\n\t x/Aq7TOWJVGFwZINF46Bfu2mEIGDBpejfOpskTy8eAJHAir8Dj9VrX7VjW61Y7v6+W\n\t w8Y6P6VbTuBha74LE3s4zK+JdtTWCNzvamxsZz0OECIkT+Xbx/AQLHGyhM5FGv9yHS\n\t 9ASdk+UPEaN2ecqhnGIUwF2kgGaMvId6IRX7l3QxDM7ov93KyvFfoXhrv2csydSsmF\n\t p6huCDnuQQocA==","Date":"Mon, 13 Apr 2026 22:27:33 +0200","From":"Uwe =?utf-8?q?Kleine-K=C3=B6nig?= ","To":"George Moussalem ","Cc":"Rob Herring ,\n\tKrzysztof Kozlowski , Conor Dooley ,\n\tBjorn Andersson ,\n Konrad Dybcio ,\n\tlinux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org,\n devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, Devi Priya ","Subject":"Re: [PATCH v21 2/6] pwm: driver for qualcomm ipq6018 pwm block","Message-ID":"","References":"<20260406-ipq-pwm-v21-0-6ed1e868e4c2@outlook.com>\n <20260406-ipq-pwm-v21-2-6ed1e868e4c2@outlook.com>\n \n ","Precedence":"bulk","X-Mailing-List":"linux-pwm@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha512;\n\tprotocol=\"application/pgp-signature\"; boundary=\"bhhp4rpnsyfcrsua\"","Content-Disposition":"inline","In-Reply-To":"\n "}}]