[{"id":3673881,"web_url":"http://patchwork.ozlabs.org/comment/3673881/","msgid":"","list_archive_url":null,"date":"2026-04-06T22:39:58","subject":"Re: [PATCH v4 1/3] lib: sbi: Add RISC-V vector context save/restore\n support","submitter":{"id":86710,"url":"http://patchwork.ozlabs.org/api/people/86710/","name":"Samuel Holland","email":"samuel.holland@sifive.com"},"content":"Hi Dave,\n\nOn 2026-04-06 2:31 PM, dave.patel@riscstar.com wrote:\n> From: Dave Patel \n> \n> Eager context switch: Add support for saving and restoring RISC-V vector\n> extension state in OpenSBI. This introduces a per-hart vector context\n> structure and helper routines to perform full context save and restore.\n> \n> The vector context includes vcsr CSRs along with storage for all 32 vector\n> registers. The register state is saved and restored using byte-wise vector\n> load/store instructions (vs8r/vl8r).\n> \n> The implementation follows an eager context switching model where the entire\n> vector state is saved and restored on every context switch. This provides a\n> simple and deterministic mechanism without requiring lazy trap-based\n> management.\n> \n> Notes:\n> - The SBI_MAX_VLENB is configured using CONFIG_SBI_MAX_VLENB.\n> \n> Signed-off-by: Dave Patel \n> ---\n> include/sbi/sbi_vector.h | 29 ++++++++\n> lib/sbi/Kconfig | 4 +\n> lib/sbi/objects.mk | 1 +\n> lib/sbi/sbi_vector.c | 154 +++++++++++++++++++++++++++++++++++++++\n> 4 files changed, 188 insertions(+)\n> create mode 100644 include/sbi/sbi_vector.h\n> create mode 100644 lib/sbi/sbi_vector.c\n> \n> diff --git a/include/sbi/sbi_vector.h b/include/sbi/sbi_vector.h\n> new file mode 100644\n> index 00000000..13048716\n> --- /dev/null\n> +++ b/include/sbi/sbi_vector.h\n> @@ -0,0 +1,29 @@\n> +/* SPDX-License-Identifier: GPL-2.0\n\nThis license is not compatible with the OpenSBI project. You need to release\nthese changes under a compatible license (assuming you are able to do so, i.e.\nthey are not derived from GPL code, etc. I am not a lawyer).\n\n> + *\n> + * Copyright (c) 2026 RISCstar Solutions.\n> + *\n> + * Authors:\n> + * Dave Patel \n> + */\n> +\n> +#ifndef __SBI_VECTOR_H__\n> +#define __SBI_VECTOR_H__\n> +\n> +#include \n> +\n> +#define SBI_MAX_VLENB CONFIG_SBI_MAX_VLENB\n> +\n> +struct sbi_vector_context {\n> +\tunsigned long vcsr;\n> +\tunsigned long vstart;\n> +\n> +\t/* size depends on VLEN */\n> +\tuint8_t vregs[32 * SBI_MAX_VLENB];\n> +};\n> +\n> +void sbi_vector_save(struct sbi_vector_context *dst);\n> +void sbi_vector_restore(const struct sbi_vector_context *src);\n> +int sbi_vector_domain_init(void);\n> +\n> +#endif //__SBI_VECTOR_H__\n> +\n> diff --git a/lib/sbi/Kconfig b/lib/sbi/Kconfig\n> index 8479f861..b2432150 100644\n> --- a/lib/sbi/Kconfig\n> +++ b/lib/sbi/Kconfig\n> @@ -74,4 +74,8 @@ config SBI_ECALL_VIRQ\n> \tbool \"VIRQ extension\"\n> \tdefault y\n> \n> +config SBI_MAX_VLENB\n> +\tint \"Vector VLENB size\"\n> +\tdefault 256\n> +\n> endmenu\n> diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk\n> index 68fc2036..ecb2b54e 100644\n> --- a/lib/sbi/objects.mk\n> +++ b/lib/sbi/objects.mk\n> @@ -109,3 +109,4 @@ libsbi-objs-y += sbi_trap_v_ldst.o\n> libsbi-objs-y += sbi_unpriv.o\n> libsbi-objs-y += sbi_expected_trap.o\n> libsbi-objs-y += sbi_cppc.o\n> +libsbi-objs-y += sbi_vector.o\n> diff --git a/lib/sbi/sbi_vector.c b/lib/sbi/sbi_vector.c\n> new file mode 100644\n> index 00000000..85134f8b\n> --- /dev/null\n> +++ b/lib/sbi/sbi_vector.c\n> @@ -0,0 +1,154 @@\n> +/* SPDX-License-Identifier: GPL-2.0\n> + *\n> + * Copyright (c) 2026 RISCstar Solutions.\n> + *\n> + * Authors:\n> + *\t Dave Patel \n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#ifdef OPENSBI_CC_SUPPORT_VECTOR\n> +\n> +static inline unsigned long vector_vlenb(void)\n> +{\n> +\tunsigned long vlenb = 0;\n> +\n> +\tasm volatile (\n> +\t\t\".option push\\n\\t\"\n> +\t\t\".option arch, +v\\n\\t\"\n> +\t\t\"csrr %0, vlenb\\n\\t\"\n> +\t\t\".option pop\\n\\t\"\n> +\t\t: \"=r\"(vlenb)\n> +\t\t:\n> +\t\t: \"memory\");\n> +\n> +\treturn vlenb;\n> +}\n> +\n> +void sbi_vector_save(struct sbi_vector_context *dst)\n> +{\n> +\tif (!dst)\n> +\t\treturn;\n> +\n> +#define READ_CSR(dst, csr)\t\t\t\t\\\n> +\t({\t\t\t\t\t\t\\\n> +\t\tasm volatile (\t\t\t\t\\\n> +\t\t\t\"\t.option push\\n\\t\"\t\\\n> +\t\t\t\"\t.option arch, +v\\n\\t\"\t\\\n> +\t\t\t\"\tcsrr %0, \" #csr \"\\n\\t\"\t\\\n> +\t\t\t\"\t.option pop\\n\\t\"\t\\\n> +\t\t\t:\t\"=r\"(dst)\t\t\\\n> +\t\t\t:\t\t\t\t\\\n> +\t\t\t:\t\"memory\");\t\t\\\n> +\t})\t\t\t\t\t\t\\\n> +\n> +\t/* Step 1: Save CSRs */\n> +\tREAD_CSR(dst->vcsr, vcsr);\n> +\tREAD_CSR(dst->vstart, vstart);\n> +\n> +#undef READ_CSR\n> +\n> +\tulong vlenb = vector_vlenb();\n> +\tuint8_t *base = dst->vregs;\n> +\n> +\t/* Step 3: Save vector registers */\n> +#define SAVE_VREG(i)\t\t\t\t\t\t\\\n> +\t({\t\t\t\t\t\t\t\\\n> +\tasm volatile(\t\t\t\t\t\t\\\n> +\t\t\"\t.option push\\n\\t\"\t\t\t\\\n> +\t\t\"\t.option arch, +v\\n\\t\"\t\t\t\\\n> +\t\t\"\tvs8r.v v\" #i \", (%0)\\n\\t\"\t\t\\\n> +\t\t\"\t.option pop\\n\\t\"\t\t\t\\\n> +\t\t::\t\"r\"(base + (i) * vlenb)\t: \"memory\");\t\\\n> +\t})\t\t\t\t\t\t\t\\\n> +\n> +\tSAVE_VREG(0);\n> +\tSAVE_VREG(8);\n> +\tSAVE_VREG(16);\n> +\tSAVE_VREG(24);\n> +\n> +#undef SAVE_VREG\n> +}\n> +\n> +void sbi_vector_restore(const struct sbi_vector_context *src)\n> +{\n> +\tif (!src)\n> +\t\treturn;\n> +\n> +\tconst uint8_t *base = src->vregs;\n> +\tulong vlenb = vector_vlenb();\n> +\n> +\t/* Step 2: Restore vector registers */\n> +#define RESTORE_VREG(i)\t\t\t\t\t\\\n> +\t({\t\t\t\t\t\t\t\\\n> +\tasm volatile(\t\t\t\t\t\t\\\n> +\t\t\"\t.option push\\n\\t\"\t\t\t\\\n> +\t\t\"\t.option arch, +v\\n\\t\"\t\t\t\\\n> +\t\t\"\tvl8r.v v\" #i \", (%0)\\n\\t\"\t\t\\\n> +\t\t\"\t.option pop\\n\\t\"\t\t\t\\\n> +\t\t::\t\"r\"(base + (i) * vlenb) : \"memory\");\t\\\n> +\t })\t\t\t\t\t\t\t\\\n> +\n> +\tRESTORE_VREG(0);\n> +\tRESTORE_VREG(8);\n> +\tRESTORE_VREG(16);\n> +\tRESTORE_VREG(24);\n> +#undef RESTORE_VREG\n> +\n> +\t/* Step 3: Restore CSR's last */\n> +#define WRITE_CSR(csr, val)\t\t\t\\\n> +\t({\t\t\t\t\t\\\n> +\tasm volatile(\t\t\t\t\\\n> +\t\t\"\t.option push\\n\\t\"\t\\\n> +\t\t\"\t.option arch, +v\\n\\t\"\t\\\n> +\t\t\"\tcsrw \" #csr \", %0\\n\\t\"\t\\\n> +\t\t\"\t.option pop\\n\\t\"\t\\\n> +\t\t:\t\t\t\t\\\n> +\t\t:\t\"r\"(val)\t\t\\\n> +\t\t:\t\"memory\");\t\t\\\n> +\t })\t\t\t\t\t\\\n> +\n> +\t/* Restore CSRs first */\n> +\tWRITE_CSR(vcsr, src->vcsr);\n> +\tWRITE_CSR(vstart, src->vstart);\n> +#undef WRITE_CSR\n> +}\n> +\n> +int sbi_vector_domain_init(void)\n> +{\n> +\tcsr_set(CSR_MSTATUS, MSTATUS_VS);\n> +\tulong vlenb = vector_vlenb();\n> +\n> +\tif (vlenb > SBI_MAX_VLENB) {\n> +\t\tsbi_printf(\"[Vector ERR:] vlenb range error\\n\");\n> +\t\treturn SBI_ERR_BAD_RANGE;\n> +\t}\n> +\n> +\tcsr_clear(CSR_MSTATUS, MSTATUS_VS);\n\nWhat is the purpose of this CSR write? If you want to set the initial state of\nthe vector registers, this doesn't accomplish that; you have to write the vector\nregisters.\n\nRegards,\nSamuel\n\n> +\treturn SBI_OK;\n> +}\n> +\n> +#else\n> +\n> +void sbi_vector_save(struct sbi_vector_context *dst)\n> +{\n> +}\n> +\n> +void sbi_vector_restore(const struct sbi_vector_context *src)\n> +{\n> +}\n> +\n> +int sbi_vector_domain_init(void)\n> +{\n> +\treturn SBI_OK;\n> +}\n> +\n> +#endif /* OPENSBI_CC_SUPPORT_VECTOR */\n> --\n> 2.43.0\n>","headers":{"Return-Path":"\n ","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=MuQJ/LZV;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=cBQnmQTh;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org;\n envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n [IPv6:2607:7c80:54:3::133])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fqPRH42dLz1y2d\n\tfor ; Tue, 07 Apr 2026 08:40:11 +1000 (AEST)","from localhost ([::1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux))\n\tid 1w9sc0-00000005aIS-1sUG;\n\tMon, 06 Apr 2026 22:40:04 +0000","from mail-oi1-x231.google.com ([2607:f8b0:4864:20::231])\n\tby bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux))\n\tid 1w9sbx-00000005aHt-2cTa\n\tfor opensbi@lists.infradead.org;\n\tMon, 06 Apr 2026 22:40:02 +0000","by mail-oi1-x231.google.com with SMTP id\n 5614622812f47-466ec4c6846so1300973b6e.3\n for ;\n Mon, 06 Apr 2026 15:40:01 -0700 (PDT)","from [100.64.0.1] ([170.85.103.33])\n by smtp.gmail.com with ESMTPSA id\n 46e09a7af769-7dba7159fd9sm10901262a34.7.2026.04.06.15.39.59\n (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128);\n Mon, 06 Apr 2026 15:39:59 -0700 (PDT)"],"DKIM-Signature":["v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20210309; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:\n\tSubject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=kVGZBUr5lRyyISKMVxgUXL/qPto5HK50Tc8NR9XNZ20=; b=MuQJ/LZV8xPNF/\n\tj2mBarsSLzMWGjNvmFPmSLrNKaxqHOkw74Xy3puc1KAZtfiwSk7gyJNqPLN1RSduYZXvFQq6fA7B2\n\toT/XvRnxhypm6w+HRG40Sq9IZDT9k/JnTgCdI2Ydcd98mLABKtE+vQ5e3kNhiH9MzYwCisb3gR4wL\n\tXVpb5tbyI+bgHjAcNh0bkCFvysQPPpknfl8QoxT9kTPL7jmRDWsCj6PhQ5fyLYO8rmsewlmMfrON+\n\thDRyxvG+Ukn5kj+k8WKujm7uMt52+ILoL5NjNlx/nvy2BrsjRLGRA8S+yrMITeKUzklRaE4qcKL4v\n\tkevOAs45X/qGBYcgd73Q==;","v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=sifive.com; s=google; t=1775515200; x=1776120000;\n darn=lists.infradead.org;\n h=content-transfer-encoding:in-reply-to:from:content-language\n :references:cc:to:subject:user-agent:mime-version:date:message-id\n :from:to:cc:subject:date:message-id:reply-to;\n bh=/pX1YC5tISi+USHBQkf3/gYgjH84jLt2WiqEZ7zHo10=;\n b=cBQnmQThzv+uA862Lm/xqe3vRmMY3TIf2Zy+asDs6wo855cLzsTfzDud235oMVcKRe\n WvVdUqi3w0uYQz2UTkwowgPAgBKagy3+zuIayOPHHih2xRJiSEaFWxlSdKNpnl7n+sC5\n 1EjxDTB5hCo75GJXeGEY9NC/F6FIqlkCoUDN1PBNk8UIhwSdkw0HRzAobIhyqBfg1dj1\n sy+6YZUGvwfXE4nLXZjAVqI0nGcpT7lWp+zh7nGnBZ5wJgZZWzotJIp3Fbb83mi1b67U\n WTKK57xdN9pQmRiFqt4J+Wkm3JdWF/cV/a3cPvVmguzTviXQqifIjlOgsmGrOkTfTOn0\n WV+A=="],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1775515200; x=1776120000;\n h=content-transfer-encoding:in-reply-to:from:content-language\n :references:cc:to:subject:user-agent:mime-version:date:message-id\n :x-gm-gg:x-gm-message-state:from:to:cc:subject:date:message-id\n :reply-to;\n bh=/pX1YC5tISi+USHBQkf3/gYgjH84jLt2WiqEZ7zHo10=;\n b=ouDx7LMm7m1MEs9x/K6tBx/UgzT28QJ/dzPNYrBdChkMadIUwoQ88EdJYX7KjajhnB\n V47o2q8lvcv4DKVhXCO1df7BDsyBEwsIP53jDg4QRcbhpBpDRIXmL7PUp+6sS8X6mNP1\n xs31H2pT2xYVOYhnTp7KxNHX8MWZK44ybXvbhjbogOlstc8vltEk736YFabfCgtnkp/T\n RVSk+hL/h6hWY9vJrxiGmBZT8ewOd3Ry5qOsItA0XZ5aldWHNMbgx3XJL2m3Req9Cdsi\n FcjD9pignmjg9JjC3qaOHMixL4T5kOLbq8OeU4/N+zhRYc6w6G5a78y045YaoDfujN8P\n jjew==","X-Forwarded-Encrypted":"i=1;\n AJvYcCV5fR+6Q+U9M6rL7nAi3IoaAwNyOZqwf284hAIbAsDWZONModdwQNOeMCuNcEHJVarAXGgM66td@lists.infradead.org","X-Gm-Message-State":"AOJu0YxTQ51YghOhsJolX5uBT8jmwSOEFdFFAt4+SfKg2hoARyN5df9T\n\tQrKiyhjSurZ+Zsw6g9l3O872xGBDhI7fC21fjt4CnaRoaE64NSR3Z9jawwnKDUryImg=","X-Gm-Gg":"AeBDietBjdcQ/GENrEm1Df69gE+G6Qncq127KmgKUqa+GBvbZz6+dejLx6W94ucnOMh\n\taJH1XnnlyUhYujc8nyhMnQoOeCIM5Irufmd2TlqS3WleQRiLsNnMYKnDVge/T7jF1Fa+5iiaSWJ\n\tgM7dyguF1EKtTTrXl1rl7Tfavu3eJ1i3c0qKKH6Vz4Nn5CuJHobUDEHS3ZJ5N4q09yEzIFOqye2\n\tZaTGcqXWmeaBzM3DaR7t0oArpgPcOvgQ/GH0Lhlup2eFcEJdcPO3sPJKX5igEEK28fpmWE9TwZC\n\tYD7rh8m6oAc9JX/55sSqo20xMX7bIchlETPF5l1SdDAPeRv8b0Gf1tHYt5luf4RKZUtVw8WhQaK\n\t7wIHkR9InnR1pi6rpJ74kCvwUF7pXcoM50qB5fuiCJ2pgRI+WGyV4OKk+6LDKeFdO25Pukl5/0k\n\t/QWHCWkfxhJpRhPaKbIWCGEkPsWEXrIZSJt+U=","X-Received":"by 2002:a05:6808:5383:b0:467:268d:31d4 with SMTP id\n 5614622812f47-46ef60f1cd3mr6814012b6e.20.1775515200149;\n Mon, 06 Apr 2026 15:40:00 -0700 (PDT)","Message-ID":"","Date":"Mon, 6 Apr 2026 17:39:58 -0500","MIME-Version":"1.0","User-Agent":"Mozilla Thunderbird","Subject":"Re: [PATCH v4 1/3] lib: sbi: Add RISC-V vector context save/restore\n support","To":"dave.patel@riscstar.com","Cc":"Scott Bambrough ,\n Robin Randhawa ,\n Anup Patel , Ray Mao\n , Anup Patel ,\n Dhaval , Peter Lin ,\n opensbi@lists.infradead.org, radim.krcmar@oss.qualcomm.com","References":"<20260406193133.658066-1-dave.patel@riscstar.com>\n <20260406193133.658066-2-dave.patel@riscstar.com>","Content-Language":"en-US","From":"Samuel Holland ","In-Reply-To":"<20260406193133.658066-2-dave.patel@riscstar.com>","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20260406_154001_720274_CD81F9FF ","X-CRM114-Status":"GOOD ( 23.62 )","X-Spam-Score":"-2.1 (--)","X-Spam-Report":"Spam detection software,\n running on the system \"bombadil.infradead.org\",\n has NOT identified this incoming email as spam. The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: Hi Dave, On 2026-04-06 2:31 PM,\n dave.patel@riscstar.com wrote:\n > From: Dave Patel > > Eager context switch: Add\n support for saving and restoring RISC-V vector > extension state in Ope\n [...] \n Content analysis details: (-2.1 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no\n trust\n [2607:f8b0:4864:20:0:0:0:231 listed in]\n [list.dnswl.org]\n -0.0 SPF_PASS SPF: sender matches SPF record\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from\n envelope-from domain\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n author's\n domain\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]","X-BeenThere":"opensbi@lists.infradead.org","X-Mailman-Version":"2.1.34","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"opensbi\" ","Errors-To":"opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}},{"id":3674600,"web_url":"http://patchwork.ozlabs.org/comment/3674600/","msgid":"<2b7f38c5-01cb-4f39-979a-8a8a89eea07a@riscstar.com>","list_archive_url":null,"date":"2026-04-08T07:18:07","subject":"Re: [PATCH v4 1/3] lib: sbi: Add RISC-V vector context save/restore\n support","submitter":{"id":92617,"url":"http://patchwork.ozlabs.org/api/people/92617/","name":"Dave Patel","email":"dave.patel@riscstar.com"},"content":"On 4/6/26 23:39, Samuel Holland wrote:\n> Hi Dave,\n> \n> On 2026-04-06 2:31 PM, dave.patel@riscstar.com wrote:\n>> From: Dave Patel \n>>\n>> Eager context switch: Add support for saving and restoring RISC-V vector\n>> extension state in OpenSBI. This introduces a per-hart vector context\n>> structure and helper routines to perform full context save and restore.\n>>\n>> The vector context includes vcsr CSRs along with storage for all 32 vector\n>> registers. The register state is saved and restored using byte-wise vector\n>> load/store instructions (vs8r/vl8r).\n>>\n>> The implementation follows an eager context switching model where the entire\n>> vector state is saved and restored on every context switch. This provides a\n>> simple and deterministic mechanism without requiring lazy trap-based\n>> management.\n>>\n>> Notes:\n>> - The SBI_MAX_VLENB is configured using CONFIG_SBI_MAX_VLENB.\n>>\n>> Signed-off-by: Dave Patel \n>> ---\n>> include/sbi/sbi_vector.h | 29 ++++++++\n>> lib/sbi/Kconfig | 4 +\n>> lib/sbi/objects.mk | 1 +\n>> lib/sbi/sbi_vector.c | 154 +++++++++++++++++++++++++++++++++++++++\n>> 4 files changed, 188 insertions(+)\n>> create mode 100644 include/sbi/sbi_vector.h\n>> create mode 100644 lib/sbi/sbi_vector.c\n>>\n>> diff --git a/include/sbi/sbi_vector.h b/include/sbi/sbi_vector.h\n>> new file mode 100644\n>> index 00000000..13048716\n>> --- /dev/null\n>> +++ b/include/sbi/sbi_vector.h\n>> @@ -0,0 +1,29 @@\n>> +/* SPDX-License-Identifier: GPL-2.0\n> \n> This license is not compatible with the OpenSBI project. You need to release\n> these changes under a compatible license (assuming you are able to do so, i.e.\n> they are not derived from GPL code, etc. I am not a lawyer).\n> \nThanks, I have updated to match the Opensbi standards.\n\n>> + *\n>> + * Copyright (c) 2026 RISCstar Solutions.\n>> + *\n>> + * Authors:\n>> + * Dave Patel \n>> + */\n>> +\n>> +#ifndef __SBI_VECTOR_H__\n>> +#define __SBI_VECTOR_H__\n>> +\n>> +#include \n>> +\n>> +#define SBI_MAX_VLENB CONFIG_SBI_MAX_VLENB\n>> +\n>> +struct sbi_vector_context {\n>> +\tunsigned long vcsr;\n>> +\tunsigned long vstart;\n>> +\n>> +\t/* size depends on VLEN */\n>> +\tuint8_t vregs[32 * SBI_MAX_VLENB];\n>> +};\n>> +\n>> +void sbi_vector_save(struct sbi_vector_context *dst);\n>> +void sbi_vector_restore(const struct sbi_vector_context *src);\n>> +int sbi_vector_domain_init(void);\n>> +\n>> +#endif //__SBI_VECTOR_H__\n>> +\n>> diff --git a/lib/sbi/Kconfig b/lib/sbi/Kconfig\n>> index 8479f861..b2432150 100644\n>> --- a/lib/sbi/Kconfig\n>> +++ b/lib/sbi/Kconfig\n>> @@ -74,4 +74,8 @@ config SBI_ECALL_VIRQ\n>> \tbool \"VIRQ extension\"\n>> \tdefault y\n>>\n>> +config SBI_MAX_VLENB\n>> +\tint \"Vector VLENB size\"\n>> +\tdefault 256\n>> +\n>> endmenu\n>> diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk\n>> index 68fc2036..ecb2b54e 100644\n>> --- a/lib/sbi/objects.mk\n>> +++ b/lib/sbi/objects.mk\n>> @@ -109,3 +109,4 @@ libsbi-objs-y += sbi_trap_v_ldst.o\n>> libsbi-objs-y += sbi_unpriv.o\n>> libsbi-objs-y += sbi_expected_trap.o\n>> libsbi-objs-y += sbi_cppc.o\n>> +libsbi-objs-y += sbi_vector.o\n>> diff --git a/lib/sbi/sbi_vector.c b/lib/sbi/sbi_vector.c\n>> new file mode 100644\n>> index 00000000..85134f8b\n>> --- /dev/null\n>> +++ b/lib/sbi/sbi_vector.c\n>> @@ -0,0 +1,154 @@\n>> +/* SPDX-License-Identifier: GPL-2.0\n>> + *\n>> + * Copyright (c) 2026 RISCstar Solutions.\n>> + *\n>> + * Authors:\n>> + *\t Dave Patel \n>> + */\n>> +\n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +\n>> +#ifdef OPENSBI_CC_SUPPORT_VECTOR\n>> +\n>> +static inline unsigned long vector_vlenb(void)\n>> +{\n>> +\tunsigned long vlenb = 0;\n>> +\n>> +\tasm volatile (\n>> +\t\t\".option push\\n\\t\"\n>> +\t\t\".option arch, +v\\n\\t\"\n>> +\t\t\"csrr %0, vlenb\\n\\t\"\n>> +\t\t\".option pop\\n\\t\"\n>> +\t\t: \"=r\"(vlenb)\n>> +\t\t:\n>> +\t\t: \"memory\");\n>> +\n>> +\treturn vlenb;\n>> +}\n>> +\n>> +void sbi_vector_save(struct sbi_vector_context *dst)\n>> +{\n>> +\tif (!dst)\n>> +\t\treturn;\n>> +\n>> +#define READ_CSR(dst, csr)\t\t\t\t\\\n>> +\t({\t\t\t\t\t\t\\\n>> +\t\tasm volatile (\t\t\t\t\\\n>> +\t\t\t\"\t.option push\\n\\t\"\t\\\n>> +\t\t\t\"\t.option arch, +v\\n\\t\"\t\\\n>> +\t\t\t\"\tcsrr %0, \" #csr \"\\n\\t\"\t\\\n>> +\t\t\t\"\t.option pop\\n\\t\"\t\\\n>> +\t\t\t:\t\"=r\"(dst)\t\t\\\n>> +\t\t\t:\t\t\t\t\\\n>> +\t\t\t:\t\"memory\");\t\t\\\n>> +\t})\t\t\t\t\t\t\\\n>> +\n>> +\t/* Step 1: Save CSRs */\n>> +\tREAD_CSR(dst->vcsr, vcsr);\n>> +\tREAD_CSR(dst->vstart, vstart);\n>> +\n>> +#undef READ_CSR\n>> +\n>> +\tulong vlenb = vector_vlenb();\n>> +\tuint8_t *base = dst->vregs;\n>> +\n>> +\t/* Step 3: Save vector registers */\n>> +#define SAVE_VREG(i)\t\t\t\t\t\t\\\n>> +\t({\t\t\t\t\t\t\t\\\n>> +\tasm volatile(\t\t\t\t\t\t\\\n>> +\t\t\"\t.option push\\n\\t\"\t\t\t\\\n>> +\t\t\"\t.option arch, +v\\n\\t\"\t\t\t\\\n>> +\t\t\"\tvs8r.v v\" #i \", (%0)\\n\\t\"\t\t\\\n>> +\t\t\"\t.option pop\\n\\t\"\t\t\t\\\n>> +\t\t::\t\"r\"(base + (i) * vlenb)\t: \"memory\");\t\\\n>> +\t})\t\t\t\t\t\t\t\\\n>> +\n>> +\tSAVE_VREG(0);\n>> +\tSAVE_VREG(8);\n>> +\tSAVE_VREG(16);\n>> +\tSAVE_VREG(24);\n>> +\n>> +#undef SAVE_VREG\n>> +}\n>> +\n>> +void sbi_vector_restore(const struct sbi_vector_context *src)\n>> +{\n>> +\tif (!src)\n>> +\t\treturn;\n>> +\n>> +\tconst uint8_t *base = src->vregs;\n>> +\tulong vlenb = vector_vlenb();\n>> +\n>> +\t/* Step 2: Restore vector registers */\n>> +#define RESTORE_VREG(i)\t\t\t\t\t\\\n>> +\t({\t\t\t\t\t\t\t\\\n>> +\tasm volatile(\t\t\t\t\t\t\\\n>> +\t\t\"\t.option push\\n\\t\"\t\t\t\\\n>> +\t\t\"\t.option arch, +v\\n\\t\"\t\t\t\\\n>> +\t\t\"\tvl8r.v v\" #i \", (%0)\\n\\t\"\t\t\\\n>> +\t\t\"\t.option pop\\n\\t\"\t\t\t\\\n>> +\t\t::\t\"r\"(base + (i) * vlenb) : \"memory\");\t\\\n>> +\t })\t\t\t\t\t\t\t\\\n>> +\n>> +\tRESTORE_VREG(0);\n>> +\tRESTORE_VREG(8);\n>> +\tRESTORE_VREG(16);\n>> +\tRESTORE_VREG(24);\n>> +#undef RESTORE_VREG\n>> +\n>> +\t/* Step 3: Restore CSR's last */\n>> +#define WRITE_CSR(csr, val)\t\t\t\\\n>> +\t({\t\t\t\t\t\\\n>> +\tasm volatile(\t\t\t\t\\\n>> +\t\t\"\t.option push\\n\\t\"\t\\\n>> +\t\t\"\t.option arch, +v\\n\\t\"\t\\\n>> +\t\t\"\tcsrw \" #csr \", %0\\n\\t\"\t\\\n>> +\t\t\"\t.option pop\\n\\t\"\t\\\n>> +\t\t:\t\t\t\t\\\n>> +\t\t:\t\"r\"(val)\t\t\\\n>> +\t\t:\t\"memory\");\t\t\\\n>> +\t })\t\t\t\t\t\\\n>> +\n>> +\t/* Restore CSRs first */\n>> +\tWRITE_CSR(vcsr, src->vcsr);\n>> +\tWRITE_CSR(vstart, src->vstart);\n>> +#undef WRITE_CSR\n>> +}\n>> +\n>> +int sbi_vector_domain_init(void)\n>> +{\n>> +\tcsr_set(CSR_MSTATUS, MSTATUS_VS);\n>> +\tulong vlenb = vector_vlenb();\n>> +\n>> +\tif (vlenb > SBI_MAX_VLENB) {\n>> +\t\tsbi_printf(\"[Vector ERR:] vlenb range error\\n\");\n>> +\t\treturn SBI_ERR_BAD_RANGE;\n>> +\t}\n>> +\n>> +\tcsr_clear(CSR_MSTATUS, MSTATUS_VS);\n> \n> What is the purpose of this CSR write? If you want to set the initial state of\n> the vector registers, this doesn't accomplish that; you have to write the vector\n> registers.\n> \nThe code is to check the vlen at the startup, the csr set is used so\nthat the vector operation can be performed and cleared to bring it back\nto it's original state.\n\n\n> Regards,\n> Samuel\n> \n>> +\treturn SBI_OK;\n>> +}\n>> +\n>> +#else\n>> +\n>> +void sbi_vector_save(struct sbi_vector_context *dst)\n>> +{\n>> +}\n>> +\n>> +void sbi_vector_restore(const struct sbi_vector_context *src)\n>> +{\n>> +}\n>> +\n>> +int sbi_vector_domain_init(void)\n>> +{\n>> +\treturn SBI_OK;\n>> +}\n>> +\n>> +#endif /* OPENSBI_CC_SUPPORT_VECTOR */\n>> --\n>> 2.43.0\n>>\n> \nHi Samuel,\n Please see inline above.\nThanks\nDave","headers":{"Return-Path":"\n ","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=mswU1eQA;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=riscstar-com.20251104.gappssmtp.com\n header.i=@riscstar-com.20251104.gappssmtp.com header.a=rsa-sha256\n header.s=20251104 header.b=GXylH4Zg;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org;\n envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n [IPv6:2607:7c80:54:3::133])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frDtj0RbVz1xtJ\n\tfor ; Wed, 08 Apr 2026 17:18:20 +1000 (AEST)","from localhost ([::1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux))\n\tid 1wANB1-00000008PJd-07Wg;\n\tWed, 08 Apr 2026 07:18:15 +0000","from mail-wr1-x432.google.com ([2a00:1450:4864:20::432])\n\tby bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux))\n\tid 1wANAy-00000008PJH-0C72\n\tfor opensbi@lists.infradead.org;\n\tWed, 08 Apr 2026 07:18:13 +0000","by mail-wr1-x432.google.com with SMTP id\n ffacd0b85a97d-43cfde3c3f3so5642053f8f.3\n for ;\n Wed, 08 Apr 2026 00:18:10 -0700 (PDT)","from [172.27.130.2] (97e782b0.skybroadband.com. [151.231.130.176])\n by smtp.gmail.com with ESMTPSA id\n ffacd0b85a97d-43d1e4e221bsm53762959f8f.29.2026.04.08.00.18.08\n (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128);\n Wed, 08 Apr 2026 00:18:08 -0700 (PDT)"],"DKIM-Signature":["v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20210309; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:References:Cc:To:Subject:\n\tFrom:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=h+Jj6J2xAHJjWj2wguPhTwhYee46V0RvMD90LooO18I=; b=mswU1eQATqZ5eU\n\tub9MJ1Lk3G4yCzK9G5K2F2Io18Tk/QP2lcjCI95x4k6F+8AnIGGDsgyARUuc4cbHKpf0JPD2lPeYA\n\twCo0bAQ/Wu4uw6pG8Il0yLXBueIKxJ/VzWqPZmNMjYP06w2GEszAOVpEUt09xTFTpcpFfnaFh4Ovl\n\tS8zG8L6WPsLgR0mvtOOgRmJQ+IdGZQkgr921dUQF2mvdABB7+GJL4vBbdFv0kiDp726NgtDKSLTjo\n\t2xmhUxYEW/JLWoD/gK/b7R8A+ZzsqfQ3LB1gWbJ9wPq+qtjbKEYpvEJvsCVzXdCy2uX7FPuXab0uU\n\tuzo3QKW3njAv75RcWOfA==;","v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=riscstar-com.20251104.gappssmtp.com; s=20251104; t=1775632689;\n x=1776237489; darn=lists.infradead.org;\n h=content-transfer-encoding:in-reply-to:content-language:references\n :cc:to:subject:from:user-agent:mime-version:date:message-id:from:to\n :cc:subject:date:message-id:reply-to;\n bh=wP8rVY6O1YXSL3Rl9ZBgyVLQUG6sqimCK3HqgtHD/v4=;\n b=GXylH4ZgFuRrhtnLN4TwWSiE/0yhzYg4E+A+s38JTipVI8VMJZKwz+SMs5nd3q9oNm\n 66/uGaJ9n8HEblp3ZC0yDE0q9eUQv6uA6PnTboyvv87B3wzDnmQYNEHwfEqYGTLtVK8w\n DUSde632xa35N4BddmHm8xFvRmsSXLcvNFBS/IdVp1KUmBkK7rO5LWYKwNaq9ErPVlDC\n 571dYpOLExx0AzB3mle6CUgq+LvYqvqlpCrwty2ymfSjOF9072CTKg/IfmwIcSTf0dXi\n +R1qzCk+RZ662mxAn44tuqw4D/AUxVNd7VF1tuF8f/VDolwG7ZhRfKpTXzYLMxDURPV8\n uR0g=="],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1775632689; x=1776237489;\n h=content-transfer-encoding:in-reply-to:content-language:references\n :cc:to:subject:from:user-agent:mime-version:date:message-id:x-gm-gg\n :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to;\n bh=wP8rVY6O1YXSL3Rl9ZBgyVLQUG6sqimCK3HqgtHD/v4=;\n b=PqnVUNiHN8YoHFkDWiBgNiM7DR0tzuQu33Y4srWpjz0tAkkaSyMJqo/p2Kj82MELPi\n EoH/sZbMenOu9ilpDe7k1x9c3nz0GxgkavoGwTlOTfBQuBUuFPJsjD1ikJjxQppIFCfj\n IPlhEwXPRuT2wV7fJX97opByUr1FMNBL3aGMjao22vUljQnjV7sA0JsVlqSZJPir120W\n GqGxTspmuvBUOROpfMs9sPlhUuokTMlAmqldEebnvioVcVqtXFAaTBydyi9MOwOXq/gT\n BBROtwbJN47UfmPA8C7yLGbA5lqlpaFofpMUOZnsXxC4NptkaimY0znKXk4TynDMjNhM\n e/Jw==","X-Forwarded-Encrypted":"i=1;\n AJvYcCWU11OMZeOWMY9VJctQ/o8+fh5BDv03rK1DB9FGaB5QYYqt+rdzqfClgNQnMGcSz6g16+mZQzUm@lists.infradead.org","X-Gm-Message-State":"AOJu0Yzvgmgv5eIHW0c6ZiDMJ9xaLDmKCP0AHyhcx6ni5YmuBgMaUkJo\n\t7yGTAJwteSHuf+5Tst3jJs1S99mv+6XbFp0ff/ziVxRltEYheewsLxKE/LrdOy5tovw6aWGdAoI\n\tN+GW5r7o=","X-Gm-Gg":"AeBDietaAJfqu2Jtzo1gp4Vq86oD9NaupmgQgRHl7Y0hP0N3cuSUITClJ0uwu1T9TsX\n\t6E7gM46BjLgMHRNeWUdjBrHIzoS0rOJ7HwFyBznv4GsukJ+o68pqtZXLVppDR0kNqW5AUZhmNld\n\ttL/mJAS9KqOD1TmnXsE49NuU9N28FmNV+IKt07cicqd9ZVQlN7FkMQzsqRDfGk2f0Vuzo1Ddulc\n\tshVuso/vVpJyYMDg7cbddvvxzsOxXpydk9DigNrcs7zog60iC+7RO3gcqkQRfwzASLnZT1BkXGc\n\t/tK69Nu+EFGEGiPQf3Akp+9pYSOyZ2UK1XfMX3CBbEWdtahZhFgtv6z8AsacdkMCphe79lk1RRh\n\tm+EpFxbCcAktvGUY0gxW9wMMpceDWnVCqxxuxJwTmGVZ6sNCaBfOMV8MNCLy3NQd8qDdxZp2CEA\n\ta+8kwIlVC9AAnC734h0/9GOXg+maTy1x3h6DH+ueBNMuBCcaKRVpvbi/+LLS8PGw==","X-Received":"by 2002:a05:6000:230c:b0:43b:42af:75e with SMTP id\n ffacd0b85a97d-43d292fed0dmr28537695f8f.44.1775632689182;\n Wed, 08 Apr 2026 00:18:09 -0700 (PDT)","Message-ID":"<2b7f38c5-01cb-4f39-979a-8a8a89eea07a@riscstar.com>","Date":"Wed, 8 Apr 2026 08:18:07 +0100","MIME-Version":"1.0","User-Agent":"Mozilla Thunderbird","From":"Dave Patel ","Subject":"Re: [PATCH v4 1/3] lib: sbi: Add RISC-V vector context save/restore\n support","To":"Samuel Holland ","Cc":"Scott Bambrough ,\n Robin Randhawa ,\n Anup Patel , Ray Mao\n , Anup Patel ,\n Dhaval , Peter Lin ,\n opensbi@lists.infradead.org, radim.krcmar@oss.qualcomm.com","References":"<20260406193133.658066-1-dave.patel@riscstar.com>\n <20260406193133.658066-2-dave.patel@riscstar.com>\n ","Content-Language":"en-US","In-Reply-To":"","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20260408_001812_408456_05049AA5 ","X-CRM114-Status":"GOOD ( 24.79 )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"Spam detection software,\n running on the system \"bombadil.infradead.org\",\n has NOT identified this incoming email as spam. The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: On 4/6/26 23:39, Samuel Holland wrote: > Hi Dave,\n > > On 2026-04-06\n 2:31 PM,\n dave.patel@riscstar.com wrote: >> From: Dave Patel \n >> >> Eager context switch: Add support for sa [...]\n Content analysis details: (-1.9 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no\n trust\n [2a00:1450:4864:20:0:0:0:432 listed in]\n [list.dnswl.org]\n -0.0 SPF_PASS SPF: sender matches SPF record\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]","X-BeenThere":"opensbi@lists.infradead.org","X-Mailman-Version":"2.1.34","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"opensbi\" ","Errors-To":"opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}}]