[{"id":3673868,"web_url":"http://patchwork.ozlabs.org/comment/3673868/","msgid":"<7b8e5cb7-e5fb-4734-93df-de3e30c3f199@linaro.org>","list_archive_url":null,"date":"2026-04-06T21:33:07","subject":"Re: [PATCH v8 15/20] target/arm/tcg/translate-a64.c: use\n translator_ldl_end instead of arm_ldl_code","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/7/26 04:26, Pierrick Bouvier wrote:\n> Allows to reduce scope of target/arm/tcg/arm_ldst.h to aarch32 only.\n> \n> Suggested-by: Richard Henderson \n> Signed-off-by: Pierrick Bouvier \n> ---\n> target/arm/tcg/translate-a64.c | 5 ++---\n> 1 file changed, 2 insertions(+), 3 deletions(-)\n\nReviewed-by: Richard Henderson \n\n\nr~\n\n> \n> diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\n> index 35ad7530c4b..ebab9f36f08 100644\n> --- a/target/arm/tcg/translate-a64.c\n> +++ b/target/arm/tcg/translate-a64.c\n> @@ -25,7 +25,6 @@\n> #include \"translate-a64.h\"\n> #include \"tcg/tcg-op.h\"\n> #include \"qemu/log.h\"\n> -#include \"arm_ldst.h\"\n> #include \"semihosting/semihost.h\"\n> #include \"cpregs.h\"\n> \n> @@ -10800,7 +10799,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n> if (pc & 3) {\n> /*\n> * PC alignment fault. This has priority over the instruction abort\n> - * that we would receive from a translation fault via arm_ldl_code.\n> + * that we would receive from a translation fault via translator_ldl_end.\n> * This should only be possible after an indirect branch, at the\n> * start of the TB.\n> */\n> @@ -10812,7 +10811,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n> }\n> \n> s->pc_curr = pc;\n> - insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b);\n> + insn = translator_ldl_end(env, &s->base, pc, MO_LE);\n> s->insn = insn;\n> s->base.pc_next = pc + 4;\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=z2aWzrZd;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fqMyl6sC3z1xtJ\n\tfor ; Tue, 07 Apr 2026 07:33:51 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1w9rZP-0007Fj-4J; Mon, 06 Apr 2026 17:33:19 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1w9rZN-0007FD-DT\n for qemu-devel@nongnu.org; Mon, 06 Apr 2026 17:33:17 -0400","from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1w9rZL-0008JF-T9\n for qemu-devel@nongnu.org; Mon, 06 Apr 2026 17:33:17 -0400","by mail-pf1-x434.google.com with SMTP id\n d2e1a72fcca58-82c28f0a4ecso3255639b3a.3\n for ; Mon, 06 Apr 2026 14:33:15 -0700 (PDT)","from [192.168.1.105] (124-150-69-109.tpgi.com.au. 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