[{"id":3673872,"web_url":"http://patchwork.ozlabs.org/comment/3673872/","msgid":"","list_archive_url":null,"date":"2026-04-06T21:48:27","subject":"Re: [PATCH v8 16/20] target/arm/tcg/arm_ldst.h: merge in translate.c","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/7/26 04:26, Pierrick Bouvier wrote:\n> Only translate.c uses those functions, thus move them back to this file.\n> \n> Signed-off-by: Pierrick Bouvier \n> ---\n> target/arm/tcg/arm_ldst.h | 47 --------------------------------------\n> target/arm/tcg/translate.c | 22 +++++++++++++++++-\n> 2 files changed, 21 insertions(+), 48 deletions(-)\n\nYou could drop the inline markers with the move.\n\nAnyway,\nReviewed-by: Richard Henderson \n\n\nr~\n\n> \n> diff --git a/target/arm/tcg/arm_ldst.h b/target/arm/tcg/arm_ldst.h\n> index cee0548a1c7..e69de29bb2d 100644\n> --- a/target/arm/tcg/arm_ldst.h\n> +++ b/target/arm/tcg/arm_ldst.h\n> @@ -1,47 +0,0 @@\n> -/*\n> - * ARM load/store instructions for code (armeb-user support)\n> - *\n> - * Copyright (c) 2012 CodeSourcery, LLC\n> - *\n> - * This library is free software; you can redistribute it and/or\n> - * modify it under the terms of the GNU Lesser General Public\n> - * License as published by the Free Software Foundation; either\n> - * version 2.1 of the License, or (at your option) any later version.\n> - *\n> - * This library is distributed in the hope that it will be useful,\n> - * but WITHOUT ANY WARRANTY; without even the implied warranty of\n> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n> - * Lesser General Public License for more details.\n> - *\n> - * You should have received a copy of the GNU Lesser General Public\n> - * License along with this library; if not, see .\n> - */\n> -\n> -#ifndef ARM_LDST_H\n> -#define ARM_LDST_H\n> -\n> -#include \"exec/translator.h\"\n> -#include \"qemu/bswap.h\"\n> -\n> -/* Load an instruction and return it in the standard little-endian order */\n> -static inline uint32_t arm_ldl_code(CPUARMState *env, DisasContextBase *s,\n> - target_ulong addr, bool sctlr_b)\n> -{\n> - return translator_ldl_swap(env, s, addr, bswap_code(sctlr_b));\n> -}\n> -\n> -/* Ditto, for a halfword (Thumb) instruction */\n> -static inline uint16_t arm_lduw_code(CPUARMState *env, DisasContextBase* s,\n> - target_ulong addr, bool sctlr_b)\n> -{\n> -#ifndef CONFIG_USER_ONLY\n> - /* In big-endian (BE32) mode, adjacent Thumb instructions have been swapped\n> - within each word. Undo that now. */\n> - if (sctlr_b) {\n> - addr ^= 2;\n> - }\n> -#endif\n> - return translator_lduw_swap(env, s, addr, bswap_code(sctlr_b));\n> -}\n> -\n> -#endif\n> diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\n> index 6ea48efbac2..7fcf0656630 100644\n> --- a/target/arm/tcg/translate.c\n> +++ b/target/arm/tcg/translate.c\n> @@ -25,7 +25,6 @@\n> #define TCG_ADDRESS_BITS 32\n> #include \"tcg/tcg-op-mem.h\"\n> #include \"qemu/log.h\"\n> -#include \"arm_ldst.h\"\n> #include \"semihosting/semihost.h\"\n> #include \"cpregs.h\"\n> #include \"exec/target_page.h\"\n> @@ -6280,6 +6279,20 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)\n> }\n> }\n> \n> +/* Ditto, for a halfword (Thumb) instruction */\n> +static inline uint16_t arm_lduw_code(CPUARMState *env, DisasContextBase* s,\n> + target_ulong addr, bool sctlr_b)\n> +{\n> +#ifndef CONFIG_USER_ONLY\n> + /* In big-endian (BE32) mode, adjacent Thumb instructions have been swapped\n> + within each word. Undo that now. */\n> + if (sctlr_b) {\n> + addr ^= 2;\n> + }\n> +#endif\n> + return translator_lduw_swap(env, s, addr, bswap_code(sctlr_b));\n> +}\n> +\n> static bool insn_crosses_page(CPUARMState *env, DisasContext *s)\n> {\n> /* Return true if the insn at dc->base.pc_next might cross a page boundary.\n> @@ -6514,6 +6527,13 @@ static void arm_post_translate_insn(DisasContext *dc)\n> }\n> }\n> \n> +/* Load an instruction and return it in the standard little-endian order */\n> +static inline uint32_t arm_ldl_code(CPUARMState *env, DisasContextBase *s,\n> + target_ulong addr, bool sctlr_b)\n> +{\n> + return translator_ldl_swap(env, s, addr, bswap_code(sctlr_b));\n> +}\n> +\n> static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n> {\n> DisasContext *dc = container_of(dcbase, DisasContext, base);","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=BURbdRA5;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fqNJv5TThz1xtJ\n\tfor ; Tue, 07 Apr 2026 07:49:35 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1w9roG-0001fw-79; Mon, 06 Apr 2026 17:48:40 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1w9roE-0001fY-Rk\n for qemu-devel@nongnu.org; Mon, 06 Apr 2026 17:48:38 -0400","from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1w9roC-0002MD-V5\n for qemu-devel@nongnu.org; Mon, 06 Apr 2026 17:48:38 -0400","by mail-pf1-x42a.google.com with SMTP id\n d2e1a72fcca58-82cd6614a90so1899133b3a.3\n for ; Mon, 06 Apr 2026 14:48:36 -0700 (PDT)","from [192.168.1.105] (124-150-69-109.tpgi.com.au. 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::42a;\n envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3673878,"web_url":"http://patchwork.ozlabs.org/comment/3673878/","msgid":"<92cd883b-8eed-4570-9fd7-bf92e1110b76@linaro.org>","list_archive_url":null,"date":"2026-04-06T22:26:36","subject":"Re: [PATCH v8 16/20] target/arm/tcg/arm_ldst.h: merge in translate.c","submitter":{"id":85798,"url":"http://patchwork.ozlabs.org/api/people/85798/","name":"Pierrick Bouvier","email":"pierrick.bouvier@linaro.org"},"content":"On 4/6/26 2:48 PM, Richard Henderson wrote:\n> On 4/7/26 04:26, Pierrick Bouvier wrote:\n>> Only translate.c uses those functions, thus move them back to this file.\n>>\n>> Signed-off-by: Pierrick Bouvier \n>> ---\n>> target/arm/tcg/arm_ldst.h | 47 --------------------------------------\n>> target/arm/tcg/translate.c | 22 +++++++++++++++++-\n>> 2 files changed, 21 insertions(+), 48 deletions(-)\n> \n> You could drop the inline markers with the move.\n>\n\nWill do.\n\n> Anyway,\n> Reviewed-by: Richard Henderson \n> \n> \n> r~\n> \n>>\n>> diff --git a/target/arm/tcg/arm_ldst.h b/target/arm/tcg/arm_ldst.h\n>> index cee0548a1c7..e69de29bb2d 100644\n>> --- a/target/arm/tcg/arm_ldst.h\n>> +++ b/target/arm/tcg/arm_ldst.h\n>> @@ -1,47 +0,0 @@\n>> -/*\n>> - * ARM load/store instructions for code (armeb-user support)\n>> - *\n>> - * Copyright (c) 2012 CodeSourcery, LLC\n>> - *\n>> - * This library is free software; you can redistribute it and/or\n>> - * modify it under the terms of the GNU Lesser General Public\n>> - * License as published by the Free Software Foundation; either\n>> - * version 2.1 of the License, or (at your option) any later version.\n>> - *\n>> - * This library is distributed in the hope that it will be useful,\n>> - * but WITHOUT ANY WARRANTY; without even the implied warranty of\n>> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n>> - * Lesser General Public License for more details.\n>> - *\n>> - * You should have received a copy of the GNU Lesser General Public\n>> - * License along with this library; if not, see .\n>> - */\n>> -\n>> -#ifndef ARM_LDST_H\n>> -#define ARM_LDST_H\n>> -\n>> -#include \"exec/translator.h\"\n>> -#include \"qemu/bswap.h\"\n>> -\n>> -/* Load an instruction and return it in the standard little-endian order */\n>> -static inline uint32_t arm_ldl_code(CPUARMState *env, DisasContextBase *s,\n>> - target_ulong addr, bool sctlr_b)\n>> -{\n>> - return translator_ldl_swap(env, s, addr, bswap_code(sctlr_b));\n>> -}\n>> -\n>> -/* Ditto, for a halfword (Thumb) instruction */\n>> -static inline uint16_t arm_lduw_code(CPUARMState *env, DisasContextBase* s,\n>> - target_ulong addr, bool sctlr_b)\n>> -{\n>> -#ifndef CONFIG_USER_ONLY\n>> - /* In big-endian (BE32) mode, adjacent Thumb instructions have been swapped\n>> - within each word. Undo that now. */\n>> - if (sctlr_b) {\n>> - addr ^= 2;\n>> - }\n>> -#endif\n>> - return translator_lduw_swap(env, s, addr, bswap_code(sctlr_b));\n>> -}\n>> -\n>> -#endif\n>> diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\n>> index 6ea48efbac2..7fcf0656630 100644\n>> --- a/target/arm/tcg/translate.c\n>> +++ b/target/arm/tcg/translate.c\n>> @@ -25,7 +25,6 @@\n>> #define TCG_ADDRESS_BITS 32\n>> #include \"tcg/tcg-op-mem.h\"\n>> #include \"qemu/log.h\"\n>> -#include \"arm_ldst.h\"\n>> #include \"semihosting/semihost.h\"\n>> #include \"cpregs.h\"\n>> #include \"exec/target_page.h\"\n>> @@ -6280,6 +6279,20 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)\n>> }\n>> }\n>> \n>> +/* Ditto, for a halfword (Thumb) instruction */\n>> +static inline uint16_t arm_lduw_code(CPUARMState *env, DisasContextBase* s,\n>> + target_ulong addr, bool sctlr_b)\n>> +{\n>> +#ifndef CONFIG_USER_ONLY\n>> + /* In big-endian (BE32) mode, adjacent Thumb instructions have been swapped\n>> + within each word. Undo that now. */\n>> + if (sctlr_b) {\n>> + addr ^= 2;\n>> + }\n>> +#endif\n>> + return translator_lduw_swap(env, s, addr, bswap_code(sctlr_b));\n>> +}\n>> +\n>> static bool insn_crosses_page(CPUARMState *env, DisasContext *s)\n>> {\n>> /* Return true if the insn at dc->base.pc_next might cross a page boundary.\n>> @@ -6514,6 +6527,13 @@ static void arm_post_translate_insn(DisasContext *dc)\n>> }\n>> }\n>> \n>> +/* Load an instruction and return it in the standard little-endian order */\n>> +static inline uint32_t arm_ldl_code(CPUARMState *env, DisasContextBase *s,\n>> + target_ulong addr, bool sctlr_b)\n>> +{\n>> + return translator_ldl_swap(env, s, addr, bswap_code(sctlr_b));\n>> +}\n>> +\n>> static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n>> {\n>> DisasContext *dc = container_of(dcbase, DisasContext, base);\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=wXUgCt0O;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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