[{"id":3673884,"web_url":"http://patchwork.ozlabs.org/comment/3673884/","msgid":"","list_archive_url":null,"date":"2026-04-06T22:45:27","subject":"Re: [PATCH v8 19/20] target/arm/tcg/translate.c: remove\n TARGET_AARCH64","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/7/26 04:26, Pierrick Bouvier wrote:\n> We extract aarch64_translate_code function, and stub it accordingly.\n> \n> Suggested-by: Richard Henderson \n> Signed-off-by: Pierrick Bouvier \n> ---\n> target/arm/internals.h | 2 ++\n> target/arm/tcg/stubs32.c | 7 +++++++\n> target/arm/tcg/translate-a64.c | 8 ++++++++\n> target/arm/tcg/translate.c | 19 ++++++++-----------\n> 4 files changed, 25 insertions(+), 11 deletions(-)\n> \n> diff --git a/target/arm/internals.h b/target/arm/internals.h\n> index 8ec27508473..2850edcb198 100644\n> --- a/target/arm/internals.h\n> +++ b/target/arm/internals.h\n> @@ -381,6 +381,8 @@ void arm_init_cpreg_list(ARMCPU *cpu);\n> \n> void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);\n> void arm_translate_init(void);\n> +void aarch64_translate_code(CPUState *cs, TranslationBlock *tb,\n> + int *max_insns, vaddr pc, void *host_pc);\n> void arm_translate_code(CPUState *cs, TranslationBlock *tb,\n> int *max_insns, vaddr pc, void *host_pc);\n> \n> diff --git a/target/arm/tcg/stubs32.c b/target/arm/tcg/stubs32.c\n> index c5a0bc61f47..3945dc49e5e 100644\n> --- a/target/arm/tcg/stubs32.c\n> +++ b/target/arm/tcg/stubs32.c\n> @@ -3,6 +3,7 @@\n> */\n> \n> #include \"qemu/osdep.h\"\n> +#include \"target/arm/internals.h\"\n> #include \"target/arm/tcg/translate.h\"\n> \n> \n> @@ -15,3 +16,9 @@ void a64_translate_init(void)\n> {\n> /* Don't initialize for 32 bits. Call site will be fixed later. */\n> }\n> +\n> +void aarch64_translate_code(CPUState *cs, TranslationBlock *tb,\n> + int *max_insns, vaddr pc, void *host_pc)\n> +{\n> + g_assert_not_reached();\n> +}\n> diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\n> index ebab9f36f08..db3990576c0 100644\n> --- a/target/arm/tcg/translate-a64.c\n> +++ b/target/arm/tcg/translate-a64.c\n> @@ -10948,3 +10948,11 @@ const TranslatorOps aarch64_translator_ops = {\n> .translate_insn = aarch64_tr_translate_insn,\n> .tb_stop = aarch64_tr_tb_stop,\n> };\n> +\n> +void aarch64_translate_code(CPUState *cpu, TranslationBlock *tb,\n> + int *max_insns, vaddr pc, void *host_pc)\n> +{\n> + DisasContext dc = {};\n> + translator_loop(cpu, tb, max_insns, pc, host_pc,\n> + &aarch64_translator_ops, &dc.base, TCG_TYPE_I64);\n> +}\n> diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\n> index aea38507ef4..9a971325144 100644\n> --- a/target/arm/tcg/translate.c\n> +++ b/target/arm/tcg/translate.c\n> @@ -6906,19 +6906,16 @@ static const TranslatorOps thumb_translator_ops = {\n> void arm_translate_code(CPUState *cpu, TranslationBlock *tb,\n> int *max_insns, vaddr pc, void *host_pc)\n> {\n> - DisasContext dc = { };\n> - const TranslatorOps *ops = &arm_translator_ops;\n> CPUARMTBFlags tb_flags = arm_tbflags_from_tb(tb);\n> - TCGType addr_type = is_a64(cpu_env(cpu)) ? TCG_TYPE_I64 : TCG_TYPE_I32;\n> \n> - if (EX_TBFLAG_AM32(tb_flags, THUMB)) {\n> - ops = &thumb_translator_ops;\n> - }\n> -#ifdef TARGET_AARCH64\n> if (EX_TBFLAG_ANY(tb_flags, AARCH64_STATE)) {\n> - ops = &aarch64_translator_ops;\n> + aarch64_translate_code(cpu, tb, max_insns, pc, host_pc);\n> + } else {\n> + DisasContext dc = { };\n> + translator_loop(cpu, tb, max_insns, pc, host_pc,\n> + (EX_TBFLAG_AM32(tb_flags, THUMB)\n> + ? &thumb_translator_ops\n> + : &arm_translator_ops),\n> + &dc.base, TCG_TYPE_I32);\n> }\n> -#endif\n> -\n> - translator_loop(cpu, tb, max_insns, pc, host_pc, ops, &dc.base, addr_type);\n> }\n\nOh, I see my confusion on the previous patch.\nYes, re-ordering this would be helpful.\n\nReviewed-by: Richard Henderson \n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=PkoryWgq;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fqPZ02LZQz1xtJ\n\tfor ; Tue, 07 Apr 2026 08:46:00 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1w9shc-00018e-1q; Mon, 06 Apr 2026 18:45:52 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1w9shN-00015g-Uo\n for qemu-devel@nongnu.org; Mon, 06 Apr 2026 18:45:42 -0400","from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1w9shM-0002wy-4d\n for qemu-devel@nongnu.org; Mon, 06 Apr 2026 18:45:37 -0400","by mail-pg1-x529.google.com with SMTP id\n 41be03b00d2f7-c76cce85bd9so1530667a12.1\n for ; Mon, 06 Apr 2026 15:45:35 -0700 (PDT)","from [192.168.1.105] (124-150-69-109.tpgi.com.au. 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::529;\n envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3673887,"web_url":"http://patchwork.ozlabs.org/comment/3673887/","msgid":"<70ae25b0-11b2-430a-9d8b-4c3f095a6824@linaro.org>","list_archive_url":null,"date":"2026-04-06T22:46:59","subject":"Re: [PATCH v8 19/20] target/arm/tcg/translate.c: remove\n TARGET_AARCH64","submitter":{"id":85798,"url":"http://patchwork.ozlabs.org/api/people/85798/","name":"Pierrick Bouvier","email":"pierrick.bouvier@linaro.org"},"content":"On 4/6/26 3:45 PM, Richard Henderson wrote:\n> On 4/7/26 04:26, Pierrick Bouvier wrote:\n>> We extract aarch64_translate_code function, and stub it accordingly.\n>>\n>> Suggested-by: Richard Henderson \n>> Signed-off-by: Pierrick Bouvier \n>> ---\n>> target/arm/internals.h | 2 ++\n>> target/arm/tcg/stubs32.c | 7 +++++++\n>> target/arm/tcg/translate-a64.c | 8 ++++++++\n>> target/arm/tcg/translate.c | 19 ++++++++-----------\n>> 4 files changed, 25 insertions(+), 11 deletions(-)\n>>\n>> diff --git a/target/arm/internals.h b/target/arm/internals.h\n>> index 8ec27508473..2850edcb198 100644\n>> --- a/target/arm/internals.h\n>> +++ b/target/arm/internals.h\n>> @@ -381,6 +381,8 @@ void arm_init_cpreg_list(ARMCPU *cpu);\n>> \n>> void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);\n>> void arm_translate_init(void);\n>> +void aarch64_translate_code(CPUState *cs, TranslationBlock *tb,\n>> + int *max_insns, vaddr pc, void *host_pc);\n>> void arm_translate_code(CPUState *cs, TranslationBlock *tb,\n>> int *max_insns, vaddr pc, void *host_pc);\n>> \n>> diff --git a/target/arm/tcg/stubs32.c b/target/arm/tcg/stubs32.c\n>> index c5a0bc61f47..3945dc49e5e 100644\n>> --- a/target/arm/tcg/stubs32.c\n>> +++ b/target/arm/tcg/stubs32.c\n>> @@ -3,6 +3,7 @@\n>> */\n>> \n>> #include \"qemu/osdep.h\"\n>> +#include \"target/arm/internals.h\"\n>> #include \"target/arm/tcg/translate.h\"\n>> \n>> \n>> @@ -15,3 +16,9 @@ void a64_translate_init(void)\n>> {\n>> /* Don't initialize for 32 bits. Call site will be fixed later. */\n>> }\n>> +\n>> +void aarch64_translate_code(CPUState *cs, TranslationBlock *tb,\n>> + int *max_insns, vaddr pc, void *host_pc)\n>> +{\n>> + g_assert_not_reached();\n>> +}\n>> diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\n>> index ebab9f36f08..db3990576c0 100644\n>> --- a/target/arm/tcg/translate-a64.c\n>> +++ b/target/arm/tcg/translate-a64.c\n>> @@ -10948,3 +10948,11 @@ const TranslatorOps aarch64_translator_ops = {\n>> .translate_insn = aarch64_tr_translate_insn,\n>> .tb_stop = aarch64_tr_tb_stop,\n>> };\n>> +\n>> +void aarch64_translate_code(CPUState *cpu, TranslationBlock *tb,\n>> + int *max_insns, vaddr pc, void *host_pc)\n>> +{\n>> + DisasContext dc = {};\n>> + translator_loop(cpu, tb, max_insns, pc, host_pc,\n>> + &aarch64_translator_ops, &dc.base, TCG_TYPE_I64);\n>> +}\n>> diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\n>> index aea38507ef4..9a971325144 100644\n>> --- a/target/arm/tcg/translate.c\n>> +++ b/target/arm/tcg/translate.c\n>> @@ -6906,19 +6906,16 @@ static const TranslatorOps thumb_translator_ops = {\n>> void arm_translate_code(CPUState *cpu, TranslationBlock *tb,\n>> int *max_insns, vaddr pc, void *host_pc)\n>> {\n>> - DisasContext dc = { };\n>> - const TranslatorOps *ops = &arm_translator_ops;\n>> CPUARMTBFlags tb_flags = arm_tbflags_from_tb(tb);\n>> - TCGType addr_type = is_a64(cpu_env(cpu)) ? TCG_TYPE_I64 : TCG_TYPE_I32;\n>> \n>> - if (EX_TBFLAG_AM32(tb_flags, THUMB)) {\n>> - ops = &thumb_translator_ops;\n>> - }\n>> -#ifdef TARGET_AARCH64\n>> if (EX_TBFLAG_ANY(tb_flags, AARCH64_STATE)) {\n>> - ops = &aarch64_translator_ops;\n>> + aarch64_translate_code(cpu, tb, max_insns, pc, host_pc);\n>> + } else {\n>> + DisasContext dc = { };\n>> + translator_loop(cpu, tb, max_insns, pc, host_pc,\n>> + (EX_TBFLAG_AM32(tb_flags, THUMB)\n>> + ? &thumb_translator_ops\n>> + : &arm_translator_ops),\n>> + &dc.base, TCG_TYPE_I32);\n>> }\n>> -#endif\n>> -\n>> - translator_loop(cpu, tb, max_insns, pc, host_pc, ops, &dc.base, addr_type);\n>> }\n> \n> Oh, I see my confusion on the previous patch.\n> Yes, re-ordering this would be helpful.\n>\n\nYes, I think I missed the (implicit idea) that we would have two \ndifferent entry points for translations, in two separate files, and thus \nTCG_TYPE_VA could automatically set accordingly.\n\n> Reviewed-by: Richard Henderson \n> \n> \n> r~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=bi+LIb2X;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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