[{"id":3673817,"web_url":"http://patchwork.ozlabs.org/comment/3673817/","msgid":"","list_archive_url":null,"date":"2026-04-06T16:57:03","subject":"Re: [PATCH v2 1/5] sysreset: qemu virt: Use __raw_writel()","submitter":{"id":87364,"url":"http://patchwork.ozlabs.org/api/people/87364/","name":"Kuan-Wei Chiu","email":"visitorckw@gmail.com"},"content":"On Mon, Apr 06, 2026 at 11:24:07PM +0900, Daniel Palmer wrote:\n> The virt ctrl register seems to be native endian, currently this driver\n> uses writel(), which works by luck because its currently broken on m68k.\n> \n> Use __raw_writel() instead to avoid breaking this driver when the\n> endianness of writel() is fixed.\n> \n> Signed-off-by: Daniel Palmer \n\nAcked-by: Kuan-Wei Chiu \n\nRegards,\nKuan-Wei\n\n> ---\n> drivers/sysreset/sysreset_qemu_virt_ctrl.c | 2 +-\n> 1 file changed, 1 insertion(+), 1 deletion(-)\n> \n> diff --git a/drivers/sysreset/sysreset_qemu_virt_ctrl.c b/drivers/sysreset/sysreset_qemu_virt_ctrl.c\n> index e7cacc9b6e98..5ab16001922b 100644\n> --- a/drivers/sysreset/sysreset_qemu_virt_ctrl.c\n> +++ b/drivers/sysreset/sysreset_qemu_virt_ctrl.c\n> @@ -38,7 +38,7 @@ static int qemu_virt_ctrl_request(struct udevice *dev, enum sysreset_t type)\n> \t\treturn -EPROTONOSUPPORT;\n> \t}\n> \n> -\twritel(val, plat->reg + VIRT_CTRL_REG_CMD);\n> +\t__raw_writel(val, plat->reg + VIRT_CTRL_REG_CMD);\n> \n> \treturn -EINPROGRESS;\n> }\n> -- \n> 2.51.0\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=jJiWKVOG;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=gmail.com","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.b=\"jJiWKVOG\";\n\tdkim-atps=neutral","phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=gmail.com","phobos.denx.de;\n spf=pass smtp.mailfrom=visitorckw@gmail.com"],"Received":["from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fqFqZ6pZXz1xy1\n\tfor ; Tue, 07 Apr 2026 02:57:14 +1000 (AEST)","from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 4C5B383C2B;\n\tMon, 6 Apr 2026 18:57:12 +0200 (CEST)","by phobos.denx.de (Postfix, from userid 109)\n id 611A983E36; Mon, 6 Apr 2026 18:57:11 +0200 (CEST)","from mail-pl1-x633.google.com (mail-pl1-x633.google.com\n [IPv6:2607:f8b0:4864:20::633])\n (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 75B2D8352B\n for ; Mon, 6 Apr 2026 18:57:08 +0200 (CEST)","by mail-pl1-x633.google.com with SMTP id\n d9443c01a7336-2ab232cc803so17756145ad.3\n for ; Mon, 06 Apr 2026 09:57:08 -0700 (PDT)","from google.com (61-230-33-2.dynamic-ip.hinet.net. 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20260406142411.2992618-2-daniel@thingy.jp>","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"}},{"id":3674733,"web_url":"http://patchwork.ozlabs.org/comment/3674733/","msgid":"<99760ed8-b17a-4117-991a-b55e9775a5c1@kernel-space.org>","list_archive_url":null,"date":"2026-04-08T12:15:14","subject":"Re: [PATCH v2 1/5] sysreset: qemu virt: Use __raw_writel()","submitter":{"id":85702,"url":"http://patchwork.ozlabs.org/api/people/85702/","name":"Angelo Dureghello","email":"angelo@kernel-space.org"},"content":"Hi,\n\nOn 4/6/26 16:24, Daniel Palmer wrote:\n> The virt ctrl register seems to be native endian, currently this driver\n> uses writel(), which works by luck because its currently broken on m68k.\n> \n\nStill not clear why writel should be currently broken, it works\nfine in bigendian for m68k.\n\n> Use __raw_writel() instead to avoid breaking this driver when the\n> endianness of writel() is fixed.\n> \n> Signed-off-by: Daniel Palmer \n> ---\n> drivers/sysreset/sysreset_qemu_virt_ctrl.c | 2 +-\n> 1 file changed, 1 insertion(+), 1 deletion(-)\n> \n> diff --git a/drivers/sysreset/sysreset_qemu_virt_ctrl.c b/drivers/sysreset/sysreset_qemu_virt_ctrl.c\n> index e7cacc9b6e98..5ab16001922b 100644\n> --- a/drivers/sysreset/sysreset_qemu_virt_ctrl.c\n> +++ b/drivers/sysreset/sysreset_qemu_virt_ctrl.c\n> @@ -38,7 +38,7 @@ static int qemu_virt_ctrl_request(struct udevice *dev, enum sysreset_t type)\n> \t\treturn -EPROTONOSUPPORT;\n> \t}\n> \n> -\twritel(val, plat->reg + VIRT_CTRL_REG_CMD);\n> +\t__raw_writel(val, plat->reg + VIRT_CTRL_REG_CMD);\n> \n> \treturn -EINPROGRESS;\n> }\n\nRegards,\n\n-- Angelo","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=kernel-space.org header.i=@kernel-space.org\n header.a=rsa-sha256 header.s=s1 header.b=Va4W0UmE;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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