[{"id":3673702,"web_url":"http://patchwork.ozlabs.org/comment/3673702/","msgid":"<045cd971-7c84-4ca5-b64f-74c08abec0f9@163.com>","list_archive_url":null,"date":"2026-04-06T10:54:38","subject":"Re: [PATCH v5 3/3] PCI: dwc: Use common speed conversion function","submitter":{"id":89937,"url":"http://patchwork.ozlabs.org/api/people/89937/","name":"Hans Zhang","email":"18255117159@163.com"},"content":"Hi Mani,\n\nThis patch is missing one line of code:\nlink_speed = pcie_get_link_speed(pci->max_link_speed);\n\n\nI'll send out v6. Sorry for the noise.\n\nBest regards,\nHans\n\nOn 4/6/26 18:47, Hans Zhang wrote:\n> Replace the private switch-based speed conversion in\n> dw_pcie_link_set_max_speed() with the public pci_bus_speed2lnkctl2()\n> function.\n> \n> This eliminates duplicate conversion logic and ensures consistency with\n> other PCIe drivers, while handling invalid speeds by falling back to\n> hardware capabilities.\n> \n> Signed-off-by: Hans Zhang <18255117159@163.com>\n> Acked-by: Manivannan Sadhasivam \n> ---\n> drivers/pci/controller/dwc/pcie-designware.c | 17 ++---------------\n> 1 file changed, 2 insertions(+), 15 deletions(-)\n> \n> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c\n> index 06792ba92aa7..f2dd5da69c76 100644\n> --- a/drivers/pci/controller/dwc/pcie-designware.c\n> +++ b/drivers/pci/controller/dwc/pcie-designware.c\n> @@ -861,24 +861,11 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci)\n> \tctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);\n> \tctrl2 &= ~PCI_EXP_LNKCTL2_TLS;\n> \n> -\tswitch (pcie_get_link_speed(pci->max_link_speed)) {\n> -\tcase PCIE_SPEED_2_5GT:\n> -\t\tlink_speed = PCI_EXP_LNKCTL2_TLS_2_5GT;\n> -\t\tbreak;\n> -\tcase PCIE_SPEED_5_0GT:\n> -\t\tlink_speed = PCI_EXP_LNKCTL2_TLS_5_0GT;\n> -\t\tbreak;\n> -\tcase PCIE_SPEED_8_0GT:\n> -\t\tlink_speed = PCI_EXP_LNKCTL2_TLS_8_0GT;\n> -\t\tbreak;\n> -\tcase PCIE_SPEED_16_0GT:\n> -\t\tlink_speed = PCI_EXP_LNKCTL2_TLS_16_0GT;\n> -\t\tbreak;\n> -\tdefault:\n> +\tlink_speed = pci_bus_speed2lnkctl2(link_speed);\n> +\tif (link_speed == 0) {\n> \t\t/* Use hardware capability */\n> \t\tlink_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap);\n> \t\tctrl2 &= ~PCI_EXP_LNKCTL2_HASD;\n> -\t\tbreak;\n> \t}\n> \n> \tdw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed);","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=163.com header.i=@163.com header.a=rsa-sha256\n header.s=s110527 header.b=TY+l1gte;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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