[{"id":3675625,"web_url":"http://patchwork.ozlabs.org/comment/3675625/","msgid":"","list_archive_url":null,"date":"2026-04-10T03:08:58","subject":"Re: [PATCH v6 5/9] target/riscv: Use the tb->cs_base as the extend tb\n flags","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Thu, Apr 2, 2026 at 11:53 PM Max Chou wrote:\n>\n> We have more than 32-bits worth of state per TB, so use the\n> tb->cs_base, which is otherwise unused for RISC-V, as the extend flag.\n>\n> Reviewed-by: Daniel Henrique Barboza \n> Reviewed-by: Chao Liu \n> Signed-off-by: Max Chou \n\nReviewed-by: Alistair Francis \n\nAlistair\n\n> ---\n> include/exec/translation-block.h | 1 +\n> target/riscv/cpu.h | 3 +++\n> target/riscv/tcg/tcg-cpu.c | 7 ++++++-\n> 3 files changed, 10 insertions(+), 1 deletion(-)\n>\n> diff --git a/include/exec/translation-block.h b/include/exec/translation-block.h\n> index 4f83d5bec9..40cc699031 100644\n> --- a/include/exec/translation-block.h\n> +++ b/include/exec/translation-block.h\n> @@ -65,6 +65,7 @@ struct TranslationBlock {\n> * arm: an extension of tb->flags,\n> * s390x: instruction data for EXECUTE,\n> * sparc: the next pc of the instruction queue (for delay slots).\n> + * riscv: an extension of tb->flags,\n> */\n> uint64_t cs_base;\n>\n> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\n> index 962cc45073..4c0676ed53 100644\n> --- a/target/riscv/cpu.h\n> +++ b/target/riscv/cpu.h\n> @@ -703,6 +703,9 @@ FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1)\n> FIELD(TB_FLAGS, PM_PMM, 29, 2)\n> FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1)\n>\n> +FIELD(EXT_TB_FLAGS, MISA_EXT, 0, 32)\n> +FIELD(EXT_TB_FLAGS, ALTFMT, 32, 1)\n> +\n> #ifdef TARGET_RISCV32\n> #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)\n> #else\n> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\n> index c4f7da7193..f3f7808895 100644\n> --- a/target/riscv/tcg/tcg-cpu.c\n> +++ b/target/riscv/tcg/tcg-cpu.c\n> @@ -104,6 +104,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)\n> RISCVCPU *cpu = env_archcpu(env);\n> RISCVExtStatus fs, vs;\n> uint32_t flags = 0;\n> + uint64_t ext_flags = 0;\n> bool pm_signext = riscv_cpu_virt_mem_enabled(env);\n>\n> if (cpu->cfg.ext_zve32x) {\n> @@ -118,6 +119,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)\n>\n> /* lmul encoded as in DisasContext::lmul */\n> int8_t lmul = sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0, 3);\n> + uint8_t altfmt = FIELD_EX64(env->vtype, VTYPE, ALTFMT);\n> uint32_t vsew = FIELD_EX64(env->vtype, VTYPE, VSEW);\n> uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul);\n> uint32_t maxsz = vlmax << vsew;\n> @@ -133,6 +135,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)\n> flags = FIELD_DP32(flags, TB_FLAGS, VMA,\n> FIELD_EX64(env->vtype, VTYPE, VMA));\n> flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0);\n> + ext_flags = FIELD_DP64(ext_flags, EXT_TB_FLAGS, ALTFMT, altfmt);\n> } else {\n> flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);\n> }\n> @@ -189,10 +192,12 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)\n> flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env));\n> flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext);\n>\n> + ext_flags = FIELD_DP64(ext_flags, EXT_TB_FLAGS, MISA_EXT, env->misa_ext);\n> +\n> return (TCGTBCPUState){\n> .pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc,\n> .flags = flags,\n> - .cs_base = env->misa_ext,\n> + .cs_base = ext_flags,\n> };\n> }\n>\n> --\n> 2.52.0\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=fnmJEu+8;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n 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action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3677036,"web_url":"http://patchwork.ozlabs.org/comment/3677036/","msgid":"","list_archive_url":null,"date":"2026-04-14T06:47:02","subject":"Re: [PATCH v6 5/9] target/riscv: Use the tb->cs_base as the extend tb\n flags","submitter":{"id":91422,"url":"http://patchwork.ozlabs.org/api/people/91422/","name":"Nutty.Liu","email":"nutty.liu@hotmail.com"},"content":"On 4/2/2026 8:52 PM, Max Chou wrote:\n> We have more than 32-bits worth of state per TB, so use the\n> tb->cs_base, which is otherwise unused for RISC-V, as the extend flag.\n>\n> Reviewed-by: Daniel Henrique Barboza \n> Reviewed-by: Chao Liu \n> Signed-off-by: Max Chou \nReviewed-by: Nutty Liu \n\nThanks,\nNutty","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=hotmail.com header.i=@hotmail.com header.a=rsa-sha256\n header.s=selector1 header.b=jtf5p5gv;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fvw2x48j3z1y2d\n\tfor ; Tue, 14 Apr 2026 16:53:11 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby 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