[{"id":3673379,"web_url":"http://patchwork.ozlabs.org/comment/3673379/","msgid":"<723d3321-cf32-4739-bfdf-88cd8dcac394@mailbox.org>","list_archive_url":null,"date":"2026-04-03T23:00:01","subject":"Re: [PATCH v3 1/6] imx9: Add support for saving DDR training data to\n NVM","submitter":{"id":85664,"url":"http://patchwork.ozlabs.org/api/people/85664/","name":"Marek Vasut","email":"marek.vasut@mailbox.org"},"content":"On 4/2/26 11:40 AM, Simona Toaca (OSS) wrote:\n> From: Simona Toaca \n> \n> DDR training data can be saved to NVM and be available\n> to OEI at boot time, which will trigger QuickBoot flow.\n> \n> U-Boot only checks for data integrity (CRC32), while\n> OEI is in charge of authentication when it tries to\n> load the data from NVM.\n> \n> On iMX95 A0/A1, 'authentication' is done via another\n> CRC32. On the other boards, authentication is done by\n\nOn the other ... SoC revisions (not boards) , ... ?\n\n[...]\n\n> +++ b/arch/arm/include/asm/arch-imx9/ddr.h\n> @@ -1,6 +1,6 @@\n> /* SPDX-License-Identifier: GPL-2.0+ */\n> /*\n> - * Copyright 2022 NXP\n> + * Copyright 2022-2026 NXP\n> */\n> \n> #ifndef __ASM_ARCH_IMX8M_DDR_H\n> @@ -100,6 +100,52 @@ struct dram_timing_info {\n> \n> extern struct dram_timing_info dram_timing;\n> \n> +/* Quick Boot related */\n> +#define DDRPHY_QB_CSR_SIZE\t5168\n> +#define DDRPHY_QB_ACSM_SIZE\t(4 * 1024)\n> +#define DDRPHY_QB_MSB_SIZE\t0x200\n> +#define DDRPHY_QB_PSTATES\t0\n> +#define DDRPHY_QB_PST_SIZE\t(DDRPHY_QB_PSTATES * 4 * 1024)\n> +\n> +/**\n> + * This structure needs to be aligned with the one in OEI.\n> + */\n> +struct ddrphy_qb_state {\n> +\tu32 crc;\t\t /* Used for ensuring integrity in DRAM */\n> +#define MAC_LENGTH 8 /* 256 bits, 32-bit aligned */\n\nPlease indent with tabs.\n\n> +\tu32 mac[MAC_LENGTH];\t /* For 95A0/1 use mac[0] to keep CRC32 value */\n\n\n[...]\n\n> +++ b/arch/arm/include/asm/mach-imx/qb.h\n> @@ -0,0 +1,15 @@\n> +/* SPDX-License-Identifier: GPL-2.0+ */\n> +/*\n> + * Copyright 2026 NXP\n> + */\n> +\n> +#ifndef __IMX_QB_H__\n> +#define __IMX_QB_H__\n> +\n> +#include \n> +\n> +bool qb_check(void);\n> +int qb(int qb_dev, bool save);\n> +void spl_qb_save(void);\n\nPlease call the functions something less opaque than \"qb()\" , imx_qb_*() \nwould alrady be so much better.\n\n[...]\n\n> diff --git a/arch/arm/mach-imx/imx9/qb.c b/arch/arm/mach-imx/imx9/qb.c\n> new file mode 100644\n> index 00000000000..220545192d4\n> --- /dev/null\n> +++ b/arch/arm/mach-imx/imx9/qb.c\n> @@ -0,0 +1,379 @@\n> +// SPDX-License-Identifier: GPL-2.0+\n> +/**\n> + * Copyright 2024-2026 NXP\n> + */\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#include \n> +#include \n> +#include \n> +\n> +#define QB_STATE_LOAD_SIZE SZ_64K\n> +\n> +#define MMC_DEV\t\t0\n> +#define QSPI_DEV\t1\n> +\n> +#define IMG_FLAGS_IMG_TYPE_MASK 0xF\n> +#define IMG_FLAGS_IMG_TYPE(x) FIELD_GET(IMG_FLAGS_IMG_TYPE_MASK, (x))\n> +\n> +#define IMG_TYPE_DDR_TDATA_DUMMY 0xD /* dummy DDR training data image */\n> +\n> +bool qb_check(void)\n> +{\n> +\tstruct ddrphy_qb_state *qb_state;\n> +\tu32 size, crc;\n> +\n> +\t/**\n> +\t * Ensure CRC is not empty, the reason is that\n> +\t * the data is invalidated after first save run\n> +\t * or after it is overwritten.\n> +\t */\n> +\tqb_state = (struct ddrphy_qb_state *)CONFIG_QB_SAVED_STATE_BASE;\n> +\tsize = sizeof(struct ddrphy_qb_state) - sizeof(qb_state->crc);\n> +\tcrc = crc32(0, (u8 *)qb_state->mac, size);\n> +\n> +\tif (!qb_state->crc || crc != qb_state->crc)\n> +\t\treturn false;\n> +\n> +\treturn true;\n> +}\n> +\n> +static unsigned long qb_get_boot_device_offset(void *dev, int dev_type)\n> +{\n> +\tunsigned long offset = 0;\n> +\tstruct mmc *mmc;\n> +\n> +\tswitch (dev_type) {\n> +\tcase MMC_DEV:\n> +\t\tmmc = dev;\n> +\n> +\t\tif (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE) {\n> +\t\t\toffset = CONTAINER_HDR_MMCSD_OFFSET;\n\nMultiple return in this case will make the function simpler:\n\nreturn CONTAINER_HDR_MMCSD_OFFSET;\n\n> +\t\t} else {\n\nNo need for } else { anymore.\n\n> +\t\t\tu8 part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);\n> +\n> +\t\t\tif (part == EMMC_BOOT_PART_BOOT1 || part == EMMC_BOOT_PART_BOOT2)\n> +\t\t\t\toffset = CONTAINER_HDR_EMMC_OFFSET;\n\nreturn CONTAINER_HDR_EMMC_OFFSET;\n\n> +\t\t\telse\n> +\t\t\t\toffset = CONTAINER_HDR_MMCSD_OFFSET;\n\nreturn CONTAINER_HDR_MMCSD_OFFSET;\n\n> +\t\t}\n> +\t\tbreak;\n> +\tcase QSPI_DEV:\n> +\t\toffset = CONTAINER_HDR_QSPI_OFFSET;\n> +\t\tbreak;\n> +\tdefault:\n> +\t\treturn -EOPNOTSUPP;\n> +\t}\n> +\n> +\treturn offset;\n> +}\n\n[...]\n\n> +static int get_dev_qbdata_offset(void *dev, int dev_type, unsigned long offset,\n> +\t\t\t\t u32 *qbdata_offset)\n> +{\n> +\tint ret = -EOPNOTSUPP;\n> +\tu16 ctnr_hdr_align = CONTAINER_HDR_ALIGNMENT;\n> +\tvoid *buf = kmalloc(ctnr_hdr_align, GFP_KERNEL);\n\nCan you use buffer on stack ? u8 buf[CONTAINER_HDR_ALIGNMENT]; ? That \nwould allow you to remove all the goto statements.\n\nIf not, use malloc() not kmalloc().\n\n> +\tif (!buf) {\n> +\t\tprintf(\"kmalloc buffer failed\\n\");\n\nif malloc fails, so will printing, so drop this print and return -ENOMEM \nonly.\n\n> +\t\treturn -ENOMEM;\n> +\t}\n> +\n> +\tswitch (dev_type) {\n> +\tcase MMC_DEV:\n> +\t\tunsigned long count = 0;\n> +\t\tstruct mmc *mmc = dev;\n> +\n> +\t\tif (!(CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(MMC_WRITE)))\n> +\t\t\tgoto get_dev_qbdata_offset_exit;\n> +\n> +\t\tcount = blk_dread(mmc_get_blk_desc(mmc),\n> +\t\t\t\t offset / mmc->read_bl_len,\n> +\t\t\t\t ctnr_hdr_align / mmc->read_bl_len,\n> +\t\t\t\t buf);\n> +\t\tif (count == 0) {\n> +\t\t\tprintf(\"Read container image from MMC/SD failed\\n\");\n> +\t\t\tret = -EIO;\n> +\t\t\tgoto get_dev_qbdata_offset_exit;\n> +\t\t}\n> +\t\tbreak;\n> +\tcase QSPI_DEV:\n> +\t\tif (!CONFIG_IS_ENABLED(SPI))\n> +\t\t\tgoto get_dev_qbdata_offset_exit;\n> +\n> +\t\tret = spi_flash_read(dev, offset,\n> +\t\t\t\t ctnr_hdr_align, buf);\n> +\t\tif (ret) {\n> +\t\t\tprintf(\"Read container header from QSPI failed\\n\");\n> +\t\t\tret = -EIO;\n> +\t\t\tgoto get_dev_qbdata_offset_exit;\n> +\t\t}\n> +\t\tbreak;\n> +\tdefault:\n> +\t\tprintf(\"Support for device %d not enabled\\n\", dev_type);\n> +\t\tgoto get_dev_qbdata_offset_exit;\n> +\t}\n> +\n> +\tret = qb_parse_container(buf, qbdata_offset);\n> +\n> +get_dev_qbdata_offset_exit:\n> +\tfree(buf);\n> +\n> +\treturn ret;\n> +}\n\n[...]\n\n> +void spl_qb_save(void)\n> +{\n> +\tint dev = spl_boot_device();\n> +\n> +\t/* Save QB data on current boot device */\n> +\tif (qb(dev, true))\n\nPlease call this function something less opaque than \"qb()\" , pick \nsomething more descriptive.\n\n> +\t\tprintf(\"QB save failed\\n\");\n> +}\n[...]","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org;\n s=mail20150812; t=1775279380;\n h=from:from:reply-to:subject:subject:date:date:message-id:message-id:\n to:to:cc:cc:mime-version:mime-version:content-type:content-type:\n content-transfer-encoding:content-transfer-encoding:\n in-reply-to:in-reply-to:references:references;\n bh=UowXNcZas2C80sRZEvBY65054QBKalsPVvg2XspKauE=;\n b=wTL5qHmWTd5QHtneV51HrJyMWRzn7cI2x6HgXhrTIhTaWNuQ9SxTyK+PLg6wsZorg8k/t0\n wBtwkwi/PRiKQ4RVO3SYgoxrmug8pyqcW001x0ZRwnOGRjPuSV1Gc0VPaq+i/BHhldIiBX\n pM36RbRIiAEvmzQUi3EVb26unNHkmsaXJebiXxGvdu9UCbU9gXwSKFja3dgSMmxyi41UT3\n 0SfHefRa2DCTK5TyqY/W91pYex2P4A1OGXHw3P3hlZuXdO+CJOLwjRIHxqf3HachzR6QQ1\n TVnzMnUqZzdnKKTyJrsQ2Z9pgtMTRhFX6IOJjkBtSBKsQQs6UPjX+VY0oAZ6jw==","Message-ID":"<723d3321-cf32-4739-bfdf-88cd8dcac394@mailbox.org>","Date":"Sat, 4 Apr 2026 01:00:01 +0200","MIME-Version":"1.0","Subject":"Re: [PATCH v3 1/6] imx9: Add support for saving DDR training data to\n NVM","To":"\"Simona Toaca (OSS)\" , uboot-imx@nxp.com,\n u-boot@lists.denx.de","Cc":"Stefano Babic , festevam@gmail.com,\n peng.fan@nxp.com, alice.guo@nxp.com, viorel.suman@nxp.com,\n simona.toaca@nxp.com, ye.li@nxp.com, ping.bai@nxp.com,\n sebastien.szymanski@armadeus.com, ravi@prevas.dk,\n joao.goncalves@toradex.com, ji.luo@nxp.com, semen.protsenko@linaro.org,\n tharvey@gateworks.com, qijian.guo@nxp.com","References":"\n <7edcce04b39aabc1f58e09814e7fadff226e2bb8.1775121078.git.simona.toaca@nxp.com>","Content-Language":"en-US","From":"Marek Vasut ","In-Reply-To":"\n <7edcce04b39aabc1f58e09814e7fadff226e2bb8.1775121078.git.simona.toaca@nxp.com>","Content-Type":"text/plain; charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","X-MBO-RS-META":"k8wrmdxa6b9t49icst6d7txbodomqzko","X-MBO-RS-ID":"5f076326857ef3d99cb","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"}},{"id":3673554,"web_url":"http://patchwork.ozlabs.org/comment/3673554/","msgid":"","list_archive_url":null,"date":"2026-04-05T11:49:56","subject":"Re: [PATCH v3 1/6] imx9: Add support for saving DDR training data to\n NVM","submitter":{"id":6170,"url":"http://patchwork.ozlabs.org/api/people/6170/","name":"Simon Glass","email":"sjg@chromium.org"},"content":"Hi,\n\nOn Thu, 2 Apr 2026 at 03:29, Simona Toaca (OSS)\n wrote:\n>\n> From: Simona Toaca \n>\n> DDR training data can be saved to NVM and be available\n> to OEI at boot time, which will trigger QuickBoot flow.\n>\n> U-Boot only checks for data integrity (CRC32), while\n> OEI is in charge of authentication when it tries to\n> load the data from NVM.\n>\n> On iMX95 A0/A1, 'authentication' is done via another\n> CRC32. On the other boards, authentication is done by\n> using ELE to check the MAC stored in the ddrphy_qb_state\n> structure.\n>\n> Supported platforms: iMX94, iMX95, iMX952 (using OEI)\n> Supported storage types: eMMC, SD, SPI flash.\n>\n> Signed-off-by: Viorel Suman \n> Signed-off-by: Ye Li \n> Signed-off-by: Simona Toaca \n> ---\n> arch/arm/include/asm/arch-imx9/ddr.h | 48 +++-\n> arch/arm/include/asm/mach-imx/qb.h | 15 ++\n> arch/arm/mach-imx/imx9/Makefile | 6 +-\n> arch/arm/mach-imx/imx9/qb.c | 379 +++++++++++++++++++++++++++\n> arch/arm/mach-imx/imx9/scmi/soc.c | 7 +\n> drivers/ddr/imx/imx9/Kconfig | 7 +\n> 6 files changed, 459 insertions(+), 3 deletions(-)\n> create mode 100644 arch/arm/include/asm/mach-imx/qb.h\n> create mode 100644 arch/arm/mach-imx/imx9/qb.c\n\nNote that this feature is present on x86 boards already.\n\nI wonder if we could make this more generic? E.g. it could be a\nfunction of UCLASS_RAM ? I could do the x86 part to try it out if you\nlike.\n\nRegards,\nSimon","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256\n header.s=google header.b=F2PZX3wt;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=chromium.org","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=chromium.org header.i=@chromium.org\n header.b=\"F2PZX3wt\";\n\tdkim-atps=neutral","phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=chromium.org","phobos.denx.de;\n spf=pass smtp.mailfrom=sjg@chromium.org"],"Received":["from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fpW3w4sz9z1yCs\n\tfor ; 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Sun, 05 Apr 2026\n 04:50:08 -0700 (PDT)","MIME-Version":"1.0","References":"\n <7edcce04b39aabc1f58e09814e7fadff226e2bb8.1775121078.git.simona.toaca@nxp.com>","In-Reply-To":"\n <7edcce04b39aabc1f58e09814e7fadff226e2bb8.1775121078.git.simona.toaca@nxp.com>","From":"Simon Glass ","Date":"Sun, 5 Apr 2026 05:49:56 -0600","X-Gm-Features":"AQROBzDq7w7Z5nKrfivdktDw_qk0K_ji8ZCrWMJV6K_zDXwCTiHFgMDHsektPy4","Message-ID":"\n ","Subject":"Re: [PATCH v3 1/6] imx9: Add support for saving DDR training data to\n NVM","To":"\"Simona Toaca (OSS)\" ","Cc":"uboot-imx@nxp.com, u-boot@lists.denx.de,\n Stefano Babic , festevam@gmail.com, peng.fan@nxp.com,\n alice.guo@nxp.com, viorel.suman@nxp.com, simona.toaca@nxp.com, ye.li@nxp.com,\n ping.bai@nxp.com, marex@nabladev.com, sebastien.szymanski@armadeus.com,\n ravi@prevas.dk, joao.goncalves@toradex.com, ji.luo@nxp.com,\n semen.protsenko@linaro.org, tharvey@gateworks.com, qijian.guo@nxp.com","Content-Type":"text/plain; charset=\"UTF-8\"","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"}},{"id":3673681,"web_url":"http://patchwork.ozlabs.org/comment/3673681/","msgid":"","list_archive_url":null,"date":"2026-04-06T08:39:36","subject":"Re: [PATCH v3 1/6] imx9: Add support for saving DDR training data to\n NVM","submitter":{"id":92829,"url":"http://patchwork.ozlabs.org/api/people/92829/","name":"Simona Toaca","email":"simona.toaca@oss.nxp.com"},"content":"Hi Simon,\n\nOn Sun, Apr 05, 2026 at 05:49:56AM -0600, Simon Glass wrote:\n> Hi,\n> \n> On Thu, 2 Apr 2026 at 03:29, Simona Toaca (OSS)\n> wrote:\n> >\n> > From: Simona Toaca \n> >\n> > DDR training data can be saved to NVM and be available\n> > to OEI at boot time, which will trigger QuickBoot flow.\n> >\n> > U-Boot only checks for data integrity (CRC32), while\n> > OEI is in charge of authentication when it tries to\n> > load the data from NVM.\n> >\n> > On iMX95 A0/A1, 'authentication' is done via another\n> > CRC32. On the other boards, authentication is done by\n> > using ELE to check the MAC stored in the ddrphy_qb_state\n> > structure.\n> >\n> > Supported platforms: iMX94, iMX95, iMX952 (using OEI)\n> > Supported storage types: eMMC, SD, SPI flash.\n> >\n> > Signed-off-by: Viorel Suman \n> > Signed-off-by: Ye Li \n> > Signed-off-by: Simona Toaca \n> > ---\n> > arch/arm/include/asm/arch-imx9/ddr.h | 48 +++-\n> > arch/arm/include/asm/mach-imx/qb.h | 15 ++\n> > arch/arm/mach-imx/imx9/Makefile | 6 +-\n> > arch/arm/mach-imx/imx9/qb.c | 379 +++++++++++++++++++++++++++\n> > arch/arm/mach-imx/imx9/scmi/soc.c | 7 +\n> > drivers/ddr/imx/imx9/Kconfig | 7 +\n> > 6 files changed, 459 insertions(+), 3 deletions(-)\n> > create mode 100644 arch/arm/include/asm/mach-imx/qb.h\n> > create mode 100644 arch/arm/mach-imx/imx9/qb.c\n> \n> Note that this feature is present on x86 boards already.\n> \n> I wonder if we could make this more generic? E.g. it could be a\n> function of UCLASS_RAM ? I could do the x86 part to try it out if you\n> like.\n> \n\nCan you please point me to the implementation for x86? This Quickboot\nfeature is specific to Synopsis DDR PHYs, and the location where we\nsave this data is specific to iMX9 series (since it is needed by OEI).\nI need a bit more details about what you mean.\n\nThank you,\nSimona","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector1-NXP1-onmicrosoft-com\n header.b=mmgKNFkd;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.nxp.com","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com\n header.b=\"mmgKNFkd\";\n\tdkim-atps=neutral","phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.nxp.com","phobos.denx.de;\n spf=pass smtp.mailfrom=simona.toaca@oss.nxp.com","dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=oss.nxp.com;"],"Received":["from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fq2XM0S0qz1yFt\n\tfor ; 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