[{"id":3673004,"web_url":"http://patchwork.ozlabs.org/comment/3673004/","msgid":"<20260403-glossy-industrious-pug-4f2b2c@quoll>","list_archive_url":null,"date":"2026-04-03T07:27:36","subject":"Re: [PATCH v3 1/2] dt-bindings: pwm: dwc: add reset optional","submitter":{"id":68952,"url":"http://patchwork.ozlabs.org/api/people/68952/","name":"Krzysztof Kozlowski","email":"krzk@kernel.org"},"content":"On Thu, Apr 02, 2026 at 05:18:54PM +0800, dongxuyang@eswincomputing.com wrote:\n> From: Xuyang Dong \n> \n> The DesignWare PWM controller provides separate reset signals for each\n\nSo one controller has signals. Plural, right? Then why do you define\nonly one reset signal?\n\n> clock domain, as specified in the hardware documentation. Without\n> asserting and deasserting these resets during probe, PWM outputs may\n> remain in an undefined state after system reboot.\n> \n> To address this, the driver now supports an optional 'resets' property.\n\nThis is binding change, not driver.\n\n> A full reset is performed only when no PWM channel is enabled, as\n> determined by reading the enable bit in each channel's control register.\n\nDo you describe hardware or driver behavior? This is not a change about\ndriver. Describe the hardware here - what is expected with that reset.\n\n> This allows safe coexistence with bootloaders that have already\n> configured active PWM channels.\n\nBest regards,\nKrzysztof","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=mwIiDh6B;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pwm+bounces-8461-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"mwIiDh6B\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fn9Kn75FPz1yD3\n\tfor ; Fri, 03 Apr 2026 18:27:41 +1100 (AEDT)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 1BA003020A44\n\tfor ; Fri, 3 Apr 2026 07:27:40 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id B71A5371CE4;\n\tFri, 3 Apr 2026 07:27:39 +0000 (UTC)","from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 9384D35AC17;\n\tFri, 3 Apr 2026 07:27:39 +0000 (UTC)","by smtp.kernel.org (Postfix) with ESMTPSA id D80C5C4CEF7;\n\tFri, 3 Apr 2026 07:27:38 +0000 (UTC)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1775201259; cv=none;\n b=UgtUSsJSLwriT2aAtU9YAlDvqqW2ZtcZfWtvT7UtG07SpWaZJFF8ZWORVUTQo6TIqaMGKQTGEBGOoKCqMq+150A7wb6OsSXkYK6Trxzh6orl9iomXM/sufWtAwlmjhTaqUUa2CaZWbXKRdSZMZ3a5blYkMVVC5m9KmRx2g0NnoY=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1775201259; c=relaxed/simple;\n\tbh=2vo7+fR3vUjOvvIWMIpPkrw6WJ8KcnfyAW5ibwuUpKQ=;\n\th=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:\n\t Content-Type:Content-Disposition:In-Reply-To;\n b=lBENEjdddBiGtj80ImF3KUrz6TGcqqUZ8DknXftcgcMSbx79UqaPr1elBw4UdxfgRbWqOsaRpoZqrx0mIE/QfaNWelpinGgXogzHxtZvZJdQMDgF70mYBoAUIBjSXxyukgnvdKtS9Hp/c5tAJqoWBEBtBtaFd6HahmBLoax2KYQ=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=mwIiDh6B; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1775201259;\n\tbh=2vo7+fR3vUjOvvIWMIpPkrw6WJ8KcnfyAW5ibwuUpKQ=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=mwIiDh6BaeI29WV698WF/KodgC80rkQQqQT3suX1ZVXp8cFTr2Fx0QuP5hRqkxfT/\n\t 0cjasxASspJCmf/XCQZ7sy83izC74x6GwLm//Gl3agf+Cy/l0C8tF+h90Hr5uLtCpD\n\t uuQFqIoDguzQD/uMryv60Xa3YEBY82K0lWXoPeKBQW9ZhGfoP69GI9ITRLUL1fkhtr\n\t gvJ31Z/GxPCxzaUyiTuun4oDc7eekYaDp8hKN4AoWEoFJEqg5KHDfqfyiC63vXeyqz\n\t oyzcFDDg/rb05ywk0YE0sYhC5sDZAWTzgmEW01GfH+HlKWK1lS8cxXUbyJbl468QEK\n\t jO87ey05Oyz/w==","Date":"Fri, 3 Apr 2026 09:27:36 +0200","From":"Krzysztof Kozlowski ","To":"dongxuyang@eswincomputing.com","Cc":"ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org,\n\tconor+dt@kernel.org, ben-linux@fluff.org, ben.dooks@codethink.co.uk,\n\tp.zabel@pengutronix.de, linux-pwm@vger.kernel.org,\n devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, ningyu@eswincomputing.com,\n linmin@eswincomputing.com,\n\txuxiang@eswincomputing.com, wangguosheng@eswincomputing.com,\n pinkesh.vaghela@einfochips.com","Subject":"Re: [PATCH v3 1/2] dt-bindings: pwm: dwc: add reset optional","Message-ID":"<20260403-glossy-industrious-pug-4f2b2c@quoll>","References":"<20260402091718.1608-1-dongxuyang@eswincomputing.com>\n <20260402091854.1666-1-dongxuyang@eswincomputing.com>","Precedence":"bulk","X-Mailing-List":"linux-pwm@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Disposition":"inline","In-Reply-To":"<20260402091854.1666-1-dongxuyang@eswincomputing.com>"}}]