[{"id":3673490,"web_url":"http://patchwork.ozlabs.org/comment/3673490/","msgid":"<177532369190.32405.4551053455262557653.b4-ty@b4>","list_archive_url":null,"date":"2026-04-04T17:28:11","subject":"Re: [PATCH] PCI: cadence: Use cdns_pcie_read_sz() for byte or word\n read access","submitter":{"id":91273,"url":"http://patchwork.ozlabs.org/api/people/91273/","name":"Manivannan Sadhasivam","email":"manivannan.sadhasivam@oss.qualcomm.com"},"content":"On Thu, 02 Apr 2026 14:25:45 +0530, Aksh Garg wrote:\n> The commit 18ac51ae9df9 (\"PCI: cadence: Implement capability search\n> using PCI core APIs\") assumes all the platforms using Cadence PCIe\n> controller support byte and word register accesses. This is not true\n> for all platforms (e.g., TI J721E SoC, which only supports dword\n> register accesses).\n> \n> This causes capability searches via cdns_pcie_find_capability() to fail\n> on such platforms.\n> \n> [...]\n\nApplied, thanks!\n\n[1/1] PCI: cadence: Use cdns_pcie_read_sz() for byte or word read access\n commit: d9cf7154deed71a4f23e81101571c79cdc77be00\n\nBest regards,","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=cHRBhglz;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=MCwRe1yW;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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