[{"id":3673359,"web_url":"http://patchwork.ozlabs.org/comment/3673359/","msgid":"<1c6d7e6f-eb16-4820-a4c2-35767c8db919@linaro.org>","list_archive_url":null,"date":"2026-04-04T01:01:33","subject":"Re: [RFC PATCH 3/4] alpha: Replace helper_set_alarm with Typhoon\n Cchip MMIO register","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/2/26 03:04, Yodel Eldar wrote:\n> From: Yodel Eldar \n> \n> This commit creates a QEMU-specific (non-standard) MMIO register\n> in Typhoon's Cchip to replace helper_set_alarm() and to move\n> the QEMUTimer pointer, alarm_timer, out of the Alpha CPU and into\n> the chipset code.\n> \n> Currently, PALcode writes to the QEMU-specific, synthetic\n> Processor Register (index 251) and triggers the invocation of\n> helper_set_alarm() as a side effect in QEMU, thereby setting\n> the timer alarm expiration value.\n> \n> This works, because the AlphaCPU contains the QEMUTimer and\n> CPUAlphaState stores the alarm expiration value; however, the timer\n> alarm callback resides in and is specific to the Typhoon chipset,\n> thus the CPU and the chipset are entangled.\n> \n> By designating the currently unused offset (0x7c0) of Cchip as the\n> location of the timer alarm expiration, we can disentangle and\n> better encapsulate both.\n> \n> Suggested-by: Philippe Mathieu-Daudé \n> Signed-off-by: Yodel Eldar \n> ---\n> \n> Notes:\n> The patch to the palcode-clipper binary that follows this\n> one is necessary for this patch to work; I've left the\n> diff to the source in the notes of it for reproduction.\n> \n> Philippe:\n> Thanks, again, for the suggestion of decoupling the CPU from\n> the Typhoon using IRQ lines. In my response, I guessed that\n> getting the CPU index would be trickier than moving the timer\n> into TyphoonState; perhaps you'll find it amusing (as I do)\n> that it appears I had that backwards (due to the PALcode\n> peculiarity)!\n> \n> The remaining CPU interrupts will be refactored in v2 of that\n> series.\n\nI'm not keen on this. I would much rather keep the synthetic processor register than add \na synthetic CChip mmio.\n\nIn any case, this is also doing more than one thing at a time. For instance, Connecting \nthe irq on typhoon to the irq on the cpu does not depend on anything else.\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=N3Gb3k4y;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fnckZ13FGz1yCs\n\tfor ; Sat, 04 Apr 2026 12:02:14 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1w8pOS-0002lh-SP; Fri, 03 Apr 2026 21:01:44 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1w8pOR-0002lS-FK\n for qemu-devel@nongnu.org; Fri, 03 Apr 2026 21:01:43 -0400","from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1w8pOP-0004TL-63\n for qemu-devel@nongnu.org; Fri, 03 Apr 2026 21:01:42 -0400","by mail-pj1-x102a.google.com with SMTP id\n 98e67ed59e1d1-35c238f1063so1418991a91.1\n for ; Fri, 03 Apr 2026 18:01:40 -0700 (PDT)","from [192.168.1.105] (124-150-69-109.tpgi.com.au. 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::102a;\n envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3673513,"web_url":"http://patchwork.ozlabs.org/comment/3673513/","msgid":"<0f822f37-de4a-44d3-81dc-61f9caee0403@yodel.dev>","list_archive_url":null,"date":"2026-04-04T23:32:34","subject":"Re: [RFC PATCH 3/4] alpha: Replace helper_set_alarm with Typhoon\n Cchip MMIO register","submitter":{"id":92094,"url":"http://patchwork.ozlabs.org/api/people/92094/","name":"Yodel Eldar","email":"yodel.eldar@yodel.dev"},"content":"On 03/04/2026 20:01, Richard Henderson wrote:\n> On 4/2/26 03:04, Yodel Eldar wrote:\n>> From: Yodel Eldar \n>>\n>> This commit creates a QEMU-specific (non-standard) MMIO register\n>> in Typhoon's Cchip to replace helper_set_alarm() and to move\n>> the QEMUTimer pointer, alarm_timer, out of the Alpha CPU and into\n>> the chipset code.\n>>\n>> Currently, PALcode writes to the QEMU-specific, synthetic\n>> Processor Register (index 251) and triggers the invocation of\n>> helper_set_alarm() as a side effect in QEMU, thereby setting\n>> the timer alarm expiration value.\n>>\n>> This works, because the AlphaCPU contains the QEMUTimer and\n>> CPUAlphaState stores the alarm expiration value; however, the timer\n>> alarm callback resides in and is specific to the Typhoon chipset,\n>> thus the CPU and the chipset are entangled.\n>>\n>> By designating the currently unused offset (0x7c0) of Cchip as the\n>> location of the timer alarm expiration, we can disentangle and\n>> better encapsulate both.\n>>\n>> Suggested-by: Philippe Mathieu-Daudé \n>> Signed-off-by: Yodel Eldar \n>> ---\n>>\n>> Notes:\n>>      The patch to the palcode-clipper binary that follows this\n>>      one is necessary for this patch to work; I've left the\n>>      diff to the source in the notes of it for reproduction.\n>>      Philippe:\n>>      Thanks, again, for the suggestion of decoupling the CPU from\n>>      the Typhoon using IRQ lines. In my response, I guessed that\n>>      getting the CPU index would be trickier than moving the timer\n>>      into TyphoonState; perhaps you'll find it amusing (as I do)\n>>      that it appears I had that backwards (due to the PALcode\n>>      peculiarity)!\n>>      The remaining CPU interrupts will be refactored in v2 of that\n>>      series.\n> \n> I'm not keen on this.  I would much rather keep the synthetic processor \n> register than add a synthetic CChip mmio.\n> \n\nNo problem... Are we okay with exposing a typhoon timer helper\nand TyphoonState to target/alpha/sys_helper.c via the inclusion\nof hw/alpha/alpha_sys.h?\n\nIf so, we can add an opaque pointer parameter to helper_set_alarm\ncarrying the TyphoonState and invoke the typhoon timer helper;\ne.g.:\n\n/* Inside target/alpha/sys_helper.c */\n#include \"hw/alpha/alpha_sys.h\"\n\nvoid helper_set_alarm(CPUAlphaState *env, uint64_t expire, void *opaque)\n{\n CPUState *cs = env_cpu(env);\n TyphoonState *s = TYPHOON_PCI_HOST_BRIDGE(opaque);\n int cpu_index = cs->cpu_index & 3;\n\n if (expire) {\n env->alarm_expire = expire;\n typhoon_timer_mod(s, cpu_index, expire);\n } else {\n typhoon_timer_del(s, cpu_index);\n }\n\n}\n\nWe'd have to keep alarm_expire in CPUAlphaState, because\npalcode-clipper would still expect it, but alarm timers would\nbe moved into the typhoon as an array indexed by cpu_index.\n\nWDYT?\n\n> In any case, this is also doing more than one thing at a time. For \n> instance, Connecting the irq on typhoon to the irq on the cpu does not \n> depend on anything else.\n> \n\nThanks for the example; I'll split it next time.\n\nThanks again,\nYodel\n\n> \n> r~\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=yodel.dev header.i=@yodel.dev header.a=rsa-sha256\n header.s=rsa2048 header.b=i1RFT8qd;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fpBjm51CKz1y2d\n\tfor ; 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however, the timer\n>>> alarm callback resides in and is specific to the Typhoon chipset,\n>>> thus the CPU and the chipset are entangled.\n>>>\n>>> By designating the currently unused offset (0x7c0) of Cchip as the\n>>> location of the timer alarm expiration, we can disentangle and\n>>> better encapsulate both.\n>>>\n>>> Suggested-by: Philippe Mathieu-Daudé \n>>> Signed-off-by: Yodel Eldar \n>>> ---\n>>>\n>>> Notes:\n>>>      The patch to the palcode-clipper binary that follows this\n>>>      one is necessary for this patch to work; I've left the\n>>>      diff to the source in the notes of it for reproduction.\n>>>      Philippe:\n>>>      Thanks, again, for the suggestion of decoupling the CPU from\n>>>      the Typhoon using IRQ lines. In my response, I guessed that\n>>>      getting the CPU index would be trickier than moving the timer\n>>>      into TyphoonState; perhaps you'll find it amusing (as I do)\n>>>      that it appears I had that backwards (due to the PALcode\n>>>      peculiarity)!\n>>>      The remaining CPU interrupts will be refactored in v2 of that\n>>>      series.\n>>\n>> I'm not keen on this.  I would much rather keep the synthetic processor register than \n>> add a synthetic CChip mmio.\n>>\n> \n> No problem... Are we okay with exposing a typhoon timer helper\n> and TyphoonState to target/alpha/sys_helper.c via the inclusion\n> of hw/alpha/alpha_sys.h?\n> \n> If so, we can add an opaque pointer parameter to helper_set_alarm\n> carrying the TyphoonState and invoke the typhoon timer helper;\n> e.g.:\n> \n> /* Inside target/alpha/sys_helper.c */\n> #include \"hw/alpha/alpha_sys.h\"\n> \n> void helper_set_alarm(CPUAlphaState *env, uint64_t expire, void *opaque)\n> {\n>     CPUState *cs = env_cpu(env);\n>     TyphoonState *s = TYPHOON_PCI_HOST_BRIDGE(opaque);\n>     int cpu_index = cs->cpu_index & 3;\n> \n>     if (expire) {\n>         env->alarm_expire = expire;\n>         typhoon_timer_mod(s, cpu_index, expire);\n>     } else {\n>         typhoon_timer_del(s, cpu_index);\n>     }\n> \n> }\n> \n> We'd have to keep alarm_expire in CPUAlphaState, because\n> palcode-clipper would still expect it, but alarm timers would\n> be moved into the typhoon as an array indexed by cpu_index.\n> \n> WDYT?\n\nI don't understand why you want to move the QEMUTimer. What do we gain by preventing the \ncpu from accessing the QEMUTimer?\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=X0PAjsYH;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fpnx408WZz1xtJ\n\tfor ; Mon, 06 Apr 2026 09:00:22 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1w9WRO-0002Ai-CR; Sun, 05 Apr 2026 18:59:39 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1w9WRM-0002AY-Hc\n for qemu-devel@nongnu.org; Sun, 05 Apr 2026 18:59:36 -0400","from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1w9WRK-0007zt-Nr\n for qemu-devel@nongnu.org; Sun, 05 Apr 2026 18:59:36 -0400","by mail-pg1-x533.google.com with SMTP id\n 41be03b00d2f7-c76cce85bd9so1098233a12.1\n for ; Sun, 05 Apr 2026 15:59:32 -0700 (PDT)","from [192.168.1.105] (124-150-69-109.tpgi.com.au. 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::533;\n envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3673615,"web_url":"http://patchwork.ozlabs.org/comment/3673615/","msgid":"","list_archive_url":null,"date":"2026-04-05T23:19:30","subject":"Re: [RFC PATCH 3/4] alpha: Replace helper_set_alarm with Typhoon\n Cchip MMIO register","submitter":{"id":92094,"url":"http://patchwork.ozlabs.org/api/people/92094/","name":"Yodel Eldar","email":"yodel.eldar@yodel.dev"},"content":"On 04/04/2026 18:32, Yodel Eldar wrote:\n> On 03/04/2026 20:01, Richard Henderson wrote:\n>> On 4/2/26 03:04, Yodel Eldar wrote:\n>>> From: Yodel Eldar \n>>>\n>>> This commit creates a QEMU-specific (non-standard) MMIO register\n>>> in Typhoon's Cchip to replace helper_set_alarm() and to move\n>>> the QEMUTimer pointer, alarm_timer, out of the Alpha CPU and into\n>>> the chipset code.\n>>>\n>>> Currently, PALcode writes to the QEMU-specific, synthetic\n>>> Processor Register (index 251) and triggers the invocation of\n>>> helper_set_alarm() as a side effect in QEMU, thereby setting\n>>> the timer alarm expiration value.\n>>>\n>>> This works, because the AlphaCPU contains the QEMUTimer and\n>>> CPUAlphaState stores the alarm expiration value; however, the timer\n>>> alarm callback resides in and is specific to the Typhoon chipset,\n>>> thus the CPU and the chipset are entangled.\n>>>\n>>> By designating the currently unused offset (0x7c0) of Cchip as the\n>>> location of the timer alarm expiration, we can disentangle and\n>>> better encapsulate both.\n>>>\n>>> Suggested-by: Philippe Mathieu-Daudé \n>>> Signed-off-by: Yodel Eldar \n>>> ---\n>>>\n>>> Notes:\n>>>      The patch to the palcode-clipper binary that follows this\n>>>      one is necessary for this patch to work; I've left the\n>>>      diff to the source in the notes of it for reproduction.\n>>>      Philippe:\n>>>      Thanks, again, for the suggestion of decoupling the CPU from\n>>>      the Typhoon using IRQ lines. In my response, I guessed that\n>>>      getting the CPU index would be trickier than moving the timer\n>>>      into TyphoonState; perhaps you'll find it amusing (as I do)\n>>>      that it appears I had that backwards (due to the PALcode\n>>>      peculiarity)!\n>>>      The remaining CPU interrupts will be refactored in v2 of that\n>>>      series.\n>>\n>> I'm not keen on this.  I would much rather keep the synthetic \n>> processor register than add a synthetic CChip mmio.\n>>\n> \n> No problem... Are we okay with exposing a typhoon timer helper\n> and TyphoonState to target/alpha/sys_helper.c via the inclusion\n> of hw/alpha/alpha_sys.h?\n> \n> If so, we can add an opaque pointer parameter to helper_set_alarm\n> carrying the TyphoonState and invoke the typhoon timer helper;\n> e.g.:\n> \n> /* Inside target/alpha/sys_helper.c */\n> #include \"hw/alpha/alpha_sys.h\"\n> \n> void helper_set_alarm(CPUAlphaState *env, uint64_t expire, void *opaque)\n> {\n>     CPUState *cs = env_cpu(env);\n>     TyphoonState *s = TYPHOON_PCI_HOST_BRIDGE(opaque);\n>     int cpu_index = cs->cpu_index & 3;\n> \n>     if (expire) {\n>         env->alarm_expire = expire;\n>         typhoon_timer_mod(s, cpu_index, expire);\n>     } else {\n>         typhoon_timer_del(s, cpu_index);\n>     }\n> \n> }\n> \n\nHmm, on second thought, I'm not sure this is doable\nwithout setting a link property between CPU and\nTyphoon, and if we're relegated to that than\nadding the link property in Typhoon's instance_init\n(as in in Patch 8 of \"QOMify Clipper and Typhoon\" [1])\nto use them in Typhoon's realize to create the timers\nis preferable over using them in TCG helper/translate.\n\nThe MMIO approach may be the only way to achieve\nencapsulation here, but it adds complexity and is\nprobably not as performant than using a process\nregister, so I understand the pushback against it.\n\nLet's set aside the MMIO patch; I'll integrate the\nMemTxAttrs patch (to eliminate current_cpu from the\nMISC register read) into the larger QOMify series and\nreplace all occurrences of cpu_{,reset_}interrupt with\nIRQ lines, but leave the alarm timers in the CPU. Since\nthe callback for the timer alarm belongs to Typhoon,\nthe Cchip will for the time being continue to have a\nreference to the CPUs (though, I'll continue to think\nabout gentler ways of eliminating them).\n\nPhilippe: I hope two out of three nexuses will be\nenough for now?\n\nRichard: Thanks for taking the time to check this out\nand for the feedback; I'll incorporate it into v2.\n\n[1] <20260310-qomify-alpha-v1-8-4375b00a85ff@yodel.dev>\n\nThanks,\nYodel\n\n> We'd have to keep alarm_expire in CPUAlphaState, because\n> palcode-clipper would still expect it, but alarm timers would\n> be moved into the typhoon as an array indexed by cpu_index.\n> \n> WDYT?\n> \n>> In any case, this is also doing more than one thing at a time. For \n>> instance, Connecting the irq on typhoon to the irq on the cpu does not \n>> depend on anything else.\n>>\n> \n> Thanks for the example; I'll split it next time.\n> \n> Thanks again,\n> Yodel\n> \n>>\n>> r~\n>>\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=yodel.dev header.i=@yodel.dev header.a=rsa-sha256\n header.s=rsa2048 header.b=skvrIIGl;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fppN73Nrtz1xy1\n\tfor ; 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keydata=\n xjMEZxqXdhYJKwYBBAHaRw8BAQdAkletQdG3CLyANZyuf2t7Z9PK4b6HiT+DdSPUB2mHzmPN\n I1lvZGVsIEVsZGFyIDx5b2RlbC5lbGRhckB5b2RlbC5kZXY+wpkEExYKAEECGwMFCQOcG00F\n CwkIBwIGFQoJCAsCBBYCAwECHgECF4AWIQTTzRjNQG27imap+N+V7k+3NmVNrAUCaNWASwIZ\n AQAKCRCV7k+3NmVNrNnSAPoDjQXa6v7ZzdQSaLdRfAQy/5SsUucv+zp3WAP4pXdgJQEAzMMC\n Ctx4l6b13Fs2hZdRXEnF/4BZ9t1K68nwzZOV3QnOOARnGpd2EgorBgEEAZdVAQUBAQdAKPIy\n 3W/DKFsm1e+31zoqmOY0pqz8vjIM846wM6lEY2QDAQgHwn4EGBYIACYCGwwWIQTTzRjNQG27\n imap+N+V7k+3NmVNrAUCaNWG7QUJA5wi9wAKCRCV7k+3NmVNrPusAQCQDQwETy7VT6UhHPho\n TkrQnsNqQfFU3tXqCTiViToktQD7B/U2/to97hQIJCWbK6yd3T+KPZJPMcHMg2XRyedUvgA=","In-Reply-To":"<0f822f37-de4a-44d3-81dc-61f9caee0403@yodel.dev>","Content-Type":"text/plain; charset=UTF-8; format=flowed","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=143.55.232.12;\n envelope-from=bounce+0e9322.97607e-qemu-devel=nongnu.org@yodel.dev;\n helo=v512.v5f06b487.use4.send.mailgun.net","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n HELO_STATIC_HOST=-0.001, RCVD_IN_MSPIKE_H2=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3673626,"web_url":"http://patchwork.ozlabs.org/comment/3673626/","msgid":"","list_archive_url":null,"date":"2026-04-05T23:30:20","subject":"Re: [RFC PATCH 3/4] alpha: Replace helper_set_alarm with Typhoon\n Cchip MMIO register","submitter":{"id":92094,"url":"http://patchwork.ozlabs.org/api/people/92094/","name":"Yodel Eldar","email":"yodel.eldar@yodel.dev"},"content":"Hi, Richard!\n\nOn 05/04/2026 17:59, Richard Henderson wrote:\n> On 4/5/26 09:32, Yodel Eldar wrote:\n>> On 03/04/2026 20:01, Richard Henderson wrote:\n>>> On 4/2/26 03:04, Yodel Eldar wrote:\n>>>> From: Yodel Eldar \n>>>>\n>>>> This commit creates a QEMU-specific (non-standard) MMIO register\n>>>> in Typhoon's Cchip to replace helper_set_alarm() and to move\n>>>> the QEMUTimer pointer, alarm_timer, out of the Alpha CPU and into\n>>>> the chipset code.\n>>>>\n>>>> Currently, PALcode writes to the QEMU-specific, synthetic\n>>>> Processor Register (index 251) and triggers the invocation of\n>>>> helper_set_alarm() as a side effect in QEMU, thereby setting\n>>>> the timer alarm expiration value.\n>>>>\n>>>> This works, because the AlphaCPU contains the QEMUTimer and\n>>>> CPUAlphaState stores the alarm expiration value; however, the timer\n>>>> alarm callback resides in and is specific to the Typhoon chipset,\n>>>> thus the CPU and the chipset are entangled.\n>>>>\n>>>> By designating the currently unused offset (0x7c0) of Cchip as the\n>>>> location of the timer alarm expiration, we can disentangle and\n>>>> better encapsulate both.\n>>>>\n>>>> Suggested-by: Philippe Mathieu-Daudé \n>>>> Signed-off-by: Yodel Eldar \n>>>> ---\n>>>>\n>>>> Notes:\n>>>>      The patch to the palcode-clipper binary that follows this\n>>>>      one is necessary for this patch to work; I've left the\n>>>>      diff to the source in the notes of it for reproduction.\n>>>>      Philippe:\n>>>>      Thanks, again, for the suggestion of decoupling the CPU from\n>>>>      the Typhoon using IRQ lines. In my response, I guessed that\n>>>>      getting the CPU index would be trickier than moving the timer\n>>>>      into TyphoonState; perhaps you'll find it amusing (as I do)\n>>>>      that it appears I had that backwards (due to the PALcode\n>>>>      peculiarity)!\n>>>>      The remaining CPU interrupts will be refactored in v2 of that\n>>>>      series.\n>>>\n>>> I'm not keen on this.  I would much rather keep the synthetic \n>>> processor register than add a synthetic CChip mmio.\n>>>\n>>\n>> No problem... Are we okay with exposing a typhoon timer helper\n>> and TyphoonState to target/alpha/sys_helper.c via the inclusion\n>> of hw/alpha/alpha_sys.h?\n>>\n>> If so, we can add an opaque pointer parameter to helper_set_alarm\n>> carrying the TyphoonState and invoke the typhoon timer helper;\n>> e.g.:\n>>\n>> /* Inside target/alpha/sys_helper.c */\n>> #include \"hw/alpha/alpha_sys.h\"\n>>\n>> void helper_set_alarm(CPUAlphaState *env, uint64_t expire, void *opaque)\n>> {\n>>      CPUState *cs = env_cpu(env);\n>>      TyphoonState *s = TYPHOON_PCI_HOST_BRIDGE(opaque);\n>>      int cpu_index = cs->cpu_index & 3;\n>>\n>>      if (expire) {\n>>          env->alarm_expire = expire;\n>>          typhoon_timer_mod(s, cpu_index, expire);\n>>      } else {\n>>          typhoon_timer_del(s, cpu_index);\n>>      }\n>>\n>> }\n>>\n>> We'd have to keep alarm_expire in CPUAlphaState, because\n>> palcode-clipper would still expect it, but alarm timers would\n>> be moved into the typhoon as an array indexed by cpu_index.\n>>\n>> WDYT?\n> \n> I don't understand why you want to move the QEMUTimer.  What do we gain \n> by preventing the cpu from accessing the QEMUTimer?\n> \n\nFor architectural accuracy and separation of concerns,\nI wanted to eliminate the references to the CPUs in\nTyphoon's Cchip, but as I mentioned in the email I just\nsent before I saw your reply, I understand the MMIO\napproach is probably too heavy-handed.\n\nI'll drop the MMIO patch and am setting aside alternative\napproaches to focus on the rest of the QOMify series.\n\nThanks a lot for your comments and time.\n\nYodel\n\n> \n> r~\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=yodel.dev header.i=@yodel.dev header.a=rsa-sha256\n header.s=rsa2048 header.b=X3LtXfBt;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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