[{"id":3673356,"web_url":"http://patchwork.ozlabs.org/comment/3673356/","msgid":"<47236dc2-cb06-4070-815c-b4f12128b99c@linaro.org>","list_archive_url":null,"date":"2026-04-04T00:52:51","subject":"Re: [RFC PATCH 2/4] alpha: Propagate CPU index via MemTxAttrs","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/2/26 03:04, Yodel Eldar wrote:\n> From: Yodel Eldar \n> \n> Currently, a read of the Typhoon Cchip's MISC register\n> dereferences current_cpu for the CPU index. To decouple\n> Typhoon from the CPU, let's instead pass the CPU index\n> through the requester_id attribute of the memory transaction.\n> \n> Signed-off-by: Yodel Eldar \n> ---\n> hw/alpha/typhoon.c | 7 ++++---\n> target/alpha/helper.c | 15 ++++++++++++---\n> 2 files changed, 16 insertions(+), 6 deletions(-)\n\n> +static inline QEMU_ALWAYS_INLINE\n> +MemTxAttrs alpha_cpu_get_mem_attrs(const CPUState *cs)\n> +{\n> + return (MemTxAttrs){ .requester_id = cs->cpu_index };\n> +}\n\nNo need for QEMU_ALWAYS_INLINE.\n\nOtherwise,\nReviewed-by: Richard Henderson \n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=E4HST4tV;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fncXk0QZBz1yD3\n\tfor ; Sat, 04 Apr 2026 11:53:42 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1w8pG3-000836-Mj; Fri, 03 Apr 2026 20:53:03 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1w8pG1-00082m-6p\n for qemu-devel@nongnu.org; Fri, 03 Apr 2026 20:53:01 -0400","from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1w8pFz-0002zn-OC\n for qemu-devel@nongnu.org; Fri, 03 Apr 2026 20:53:00 -0400","by mail-pj1-x102d.google.com with SMTP id\n 98e67ed59e1d1-35c238f1063so1417284a91.1\n for ; Fri, 03 Apr 2026 17:52:58 -0700 (PDT)","from [192.168.1.105] (124-150-69-109.tpgi.com.au. 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To decouple\n>> Typhoon from the CPU, let's instead pass the CPU index\n>> through the requester_id attribute of the memory transaction.\n>>\n>> Signed-off-by: Yodel Eldar \n>> ---\n>>   hw/alpha/typhoon.c    |  7 ++++---\n>>   target/alpha/helper.c | 15 ++++++++++++---\n>>   2 files changed, 16 insertions(+), 6 deletions(-)\n> \n>> +static inline QEMU_ALWAYS_INLINE\n>> +MemTxAttrs alpha_cpu_get_mem_attrs(const CPUState *cs)\n>> +{\n>> +    return (MemTxAttrs){ .requester_id = cs->cpu_index };\n>> +}\n> \n> No need for QEMU_ALWAYS_INLINE.\n> \n\nConsider it gone.\n\n> Otherwise,\n> Reviewed-by: Richard Henderson \n> \n\nThanks for the R-b.\n\nYodel\n\n> \n> r~\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=yodel.dev header.i=@yodel.dev header.a=rsa-sha256\n header.s=rsa2048 header.b=rlEkOk7M;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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