[{"id":3669588,"web_url":"http://patchwork.ozlabs.org/comment/3669588/","msgid":"","list_archive_url":null,"date":"2026-03-26T09:47:36","subject":"Re: [PATCH v2 4/7] pwm: tegra: Parametrize enable register offset","submitter":{"id":92481,"url":"http://patchwork.ozlabs.org/api/people/92481/","name":"Thierry Reding","email":"thierry.reding@kernel.org"},"content":"On Wed, Mar 25, 2026 at 07:17:02PM +0900, Mikko Perttunen wrote:\n> On Tegra264, the PWM enablement bit is not located at the base address\n> of the PWM controller. Hence, introduce an enablement offset field in\n> the tegra_pwm_soc structure to describe the offset of the register.\n> \n> Co-developed-by: Yi-Wei Wang \n> Signed-off-by: Yi-Wei Wang \n> Signed-off-by: Mikko Perttunen \n> ---\n> drivers/pwm/pwm-tegra.c | 17 ++++++++++++-----\n> 1 file changed, 12 insertions(+), 5 deletions(-)\n> \n> diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c\n> index cf54f75d92a5..22d709986e8c 100644\n> --- a/drivers/pwm/pwm-tegra.c\n> +++ b/drivers/pwm/pwm-tegra.c\n> @@ -61,6 +61,7 @@\n> \n> struct tegra_pwm_soc {\n> \tunsigned int num_channels;\n> +\tunsigned int enable_reg;\n> };\n> \n> struct tegra_pwm_chip {\n> @@ -197,8 +198,9 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,\n> \t\terr = pm_runtime_resume_and_get(pwmchip_parent(chip));\n> \t\tif (err)\n> \t\t\treturn err;\n> -\t} else\n> +\t} else if (pc->soc->enable_reg == PWM_CSR_0) {\n> \t\tval |= PWM_ENABLE;\n> +\t}\n\nThis looks incomplete for the Tegra264 case where\n\n\tpc->soc->enable_reg == PWM_CSR_1\n\n> \n> \tpwm_writel(pwm, PWM_CSR_0, val);\n\nI think we need another write for PWM_CSR_1 here to properly toggle the\nPWM_ENABLE bit on Tegra264.\n\nOr am I missing something?\n\nThierry","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=rckrPF4v;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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micalg=pgp-sha512;\n\tprotocol=\"application/pgp-signature\"; boundary=\"eikxdheegqdrxdfr\"","Content-Disposition":"inline","In-Reply-To":"<20260325-t264-pwm-v2-4-998d885984b3@nvidia.com>"}},{"id":3670833,"web_url":"http://patchwork.ozlabs.org/comment/3670833/","msgid":"<177483744958.916245.860145469758840098.b4-reply@b4>","list_archive_url":null,"date":"2026-03-30T02:24:09","subject":"Re: [PATCH v2 4/7] pwm: tegra: Parametrize enable register offset","submitter":{"id":26499,"url":"http://patchwork.ozlabs.org/api/people/26499/","name":"Mikko Perttunen","email":"mperttunen@nvidia.com"},"content":"On 2026-03-26 10:47 +0100, Thierry Reding wrote:\n> On Wed, Mar 25, 2026 at 07:17:02PM +0900, Mikko Perttunen wrote:\n> > On Tegra264, the PWM enablement bit is not located at the base address\n> > of the PWM controller. Hence, introduce an enablement offset field in\n> > the tegra_pwm_soc structure to describe the offset of the register.\n> > \n> > Co-developed-by: Yi-Wei Wang \n> > Signed-off-by: Yi-Wei Wang \n> > Signed-off-by: Mikko Perttunen \n> > ---\n> > drivers/pwm/pwm-tegra.c | 17 ++++++++++++-----\n> > 1 file changed, 12 insertions(+), 5 deletions(-)\n> > \n> > diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c\n> > index cf54f75d92a5..22d709986e8c 100644\n> > --- a/drivers/pwm/pwm-tegra.c\n> > +++ b/drivers/pwm/pwm-tegra.c\n> > @@ -61,6 +61,7 @@\n> > \n> > struct tegra_pwm_soc {\n> > \tunsigned int num_channels;\n> > +\tunsigned int enable_reg;\n> > };\n> > \n> > struct tegra_pwm_chip {\n> > @@ -197,8 +198,9 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,\n> > \t\terr = pm_runtime_resume_and_get(pwmchip_parent(chip));\n> > \t\tif (err)\n> > \t\t\treturn err;\n> > -\t} else\n> > +\t} else if (pc->soc->enable_reg == PWM_CSR_0) {\n> > \t\tval |= PWM_ENABLE;\n> > +\t}\n> \n> This looks incomplete for the Tegra264 case where\n> \n> \tpc->soc->enable_reg == PWM_CSR_1\n> \n> > \n> > \tpwm_writel(pwm, PWM_CSR_0, val);\n> \n> I think we need another write for PWM_CSR_1 here to properly toggle the\n> PWM_ENABLE bit on Tegra264.\n> \n> Or am I missing something?\n\nThis check is here just so we don't change the value of PWM_ENABLE when\nwriting the CSR_0 register. The function doesn't write to CSR_1 so\nnothing needs to be done on Tegra264.\n\nI agree it's not the clearest, but it'll get cleaned up when adding\nsupport for configurable depth, as at that point we will need to write\nboth registers on Tegra264.\n\n> \n> Thierry","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=Dsl0oNc7;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-pwm+bounces-8404-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com 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register offset","From":"Mikko Perttunen ","To":"Thierry Reding ","Cc":"Mikko Perttunen ,\n Thierry Reding ,\n =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= ,\n Jonathan Hunter , Rob Herring ,\n Krzysztof Kozlowski ,\n Conor Dooley , linux-pwm@vger.kernel.org,\n linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,\n devicetree@vger.kernel.org, Yi-Wei Wang ","In-Reply-To":"","References":"<20260325-t264-pwm-v2-0-998d885984b3@nvidia.com>\n <20260325-t264-pwm-v2-4-998d885984b3@nvidia.com> ","Date":"Mon, 30 Mar 2026 11:24:09 +0900","Message-Id":"<177483744958.916245.860145469758840098.b4-reply@b4>","X-Mailer":"b4 0.16-dev-ad80c","X-ClientProxiedBy":"TYCP286CA0239.JPNP286.PROD.OUTLOOK.COM\n (2603:1096:400:3c7::17) To SJ2PR12MB9161.namprd12.prod.outlook.com\n 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Mon, Mar 30, 2026 at 11:24:09AM +0900, Mikko Perttunen wrote:\n> On 2026-03-26 10:47 +0100, Thierry Reding wrote:\n> > On Wed, Mar 25, 2026 at 07:17:02PM +0900, Mikko Perttunen wrote:\n> > > On Tegra264, the PWM enablement bit is not located at the base address\n> > > of the PWM controller. Hence, introduce an enablement offset field in\n> > > the tegra_pwm_soc structure to describe the offset of the register.\n> > > \n> > > Co-developed-by: Yi-Wei Wang \n> > > Signed-off-by: Yi-Wei Wang \n> > > Signed-off-by: Mikko Perttunen \n> > > ---\n> > > drivers/pwm/pwm-tegra.c | 17 ++++++++++++-----\n> > > 1 file changed, 12 insertions(+), 5 deletions(-)\n> > > \n> > > diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c\n> > > index cf54f75d92a5..22d709986e8c 100644\n> > > --- a/drivers/pwm/pwm-tegra.c\n> > > +++ b/drivers/pwm/pwm-tegra.c\n> > > @@ -61,6 +61,7 @@\n> > > \n> > > struct tegra_pwm_soc {\n> > > \tunsigned int num_channels;\n> > > +\tunsigned int enable_reg;\n> > > };\n> > > \n> > > struct tegra_pwm_chip {\n> > > @@ -197,8 +198,9 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,\n> > > \t\terr = pm_runtime_resume_and_get(pwmchip_parent(chip));\n> > > \t\tif (err)\n> > > \t\t\treturn err;\n> > > -\t} else\n> > > +\t} else if (pc->soc->enable_reg == PWM_CSR_0) {\n> > > \t\tval |= PWM_ENABLE;\n> > > +\t}\n> > \n> > This looks incomplete for the Tegra264 case where\n> > \n> > \tpc->soc->enable_reg == PWM_CSR_1\n> > \n> > > \n> > > \tpwm_writel(pwm, PWM_CSR_0, val);\n> > \n> > I think we need another write for PWM_CSR_1 here to properly toggle the\n> > PWM_ENABLE bit on Tegra264.\n> > \n> > Or am I missing something?\n> \n> This check is here just so we don't change the value of PWM_ENABLE when\n> writing the CSR_0 register. The function doesn't write to CSR_1 so\n> nothing needs to be done on Tegra264.\n> \n> I agree it's not the clearest, but it'll get cleaned up when adding\n> support for configurable depth, as at that point we will need to write\n> both registers on Tegra264.\n\nAh... nevermind. I realize now that we're not touching PWM_CSR_1 at all\nin tegra_pwm_config(), so there's no need to explicitly set PWM_ENABLE.\n\nIf moving to the new APIs, that would need to change, but for the legacy\nPWM callbacks this is probably fine.\n\nThierry","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=pLpjq19P;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; helo=sto.lore.kernel.org;\n envelope-from=linux-pwm+bounces-8441-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"pLpjq19P\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sto.lore.kernel.org (sto.lore.kernel.org\n [IPv6:2600:3c09:e001:a7::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4flKbs1L0Sz1yGH\n\tfor ; Tue, 31 Mar 2026 18:33:29 +1100 (AEDT)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sto.lore.kernel.org (Postfix) with ESMTP id 41646304AC0F\n\tfor ; Tue, 31 Mar 2026 07:29:04 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 6A8473C13EF;\n\tTue, 31 Mar 2026 07:27:18 +0000 (UTC)","from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 4428A3BE632;\n\tTue, 31 Mar 2026 07:27:18 +0000 (UTC)","by smtp.kernel.org (Postfix) with ESMTPSA id 859FFC19423;\n\tTue, 31 Mar 2026 07:27:17 +0000 (UTC)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1774942038; cv=none;\n b=SjY2wRn/DMv0MM0X8d1KG4giC1ro0Qiun4AzzrOYQTr5Y3TFIgsUk1di0b2VLSx9j1liCl1Voyzgzf8SAteGcuk/EiMpxHn7GmOTUy8sLyRkB9ChhvSPvT+4E7NvSHE3XRl79oK/NP0qsfirAZrD0lLBLa7bT7BTeqXSr1SBhPI=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1774942038; c=relaxed/simple;\n\tbh=X3yeokNyZn70wlzcDKDkqaW2bU/NrHBKm0YhEEm8C3s=;\n\th=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:\n\t Content-Type:Content-Disposition:In-Reply-To;\n b=pM9m3ODD+VTMoC8kz95CShpDFlgpdKhcnLtwup+yR4jWZj55xmZhnn7EEZbwWiamjOFpXOPwzMejoMTlN4NI5cE14TeYpjA36dyeRo4iMN4nALMV3hPeaiaw/xn4y2sWMGIUyDwX38BgX+rXPO9kAbF5RfnYehXE5owL2bdJAz4=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=pLpjq19P; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1774942037;\n\tbh=X3yeokNyZn70wlzcDKDkqaW2bU/NrHBKm0YhEEm8C3s=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=pLpjq19PE1SvYAIgikedhFgItbR1nnEWD5PfIOYkpgq1UhPPvheKQ6vZtsFZCaCBq\n\t u6T8jCDGkZi8NHC8rIRG4A8h9p9/x7bFjYWOixLN02gtHe6EwClLJ83jKSIOWAJtUN\n\t Dl0WvfrJ6kZL7V6xrGCaIXk2yw1OF1mwZAlNa6HcJ1egtOfv1JfKCoNOuFB8qxrl2j\n\t cG81rVGfxEbq1beD6Znz8Ja2INBnqa5RbQolxmANaiteZaTPfP9s5fKHZkv+a7uwNi\n\t rXNLXkxumleCcNn5vZC1Z7h6TSN7AUCmsrkEO3iC3oc9Jj26CEtXQ1wmn5upb2IKey\n\t YtJgUUgCLmmLQ==","Date":"Tue, 31 Mar 2026 09:27:15 +0200","From":"Thierry Reding ","To":"Mikko Perttunen ","Cc":"Thierry Reding , Uwe =?utf-8?q?Kleine-K=C3=B6?=\n\t=?utf-8?q?nig?= ,\n Jonathan Hunter , Rob Herring ,\n Krzysztof Kozlowski ,\n Conor Dooley , linux-pwm@vger.kernel.org,\n linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,\n devicetree@vger.kernel.org, Yi-Wei Wang ","Subject":"Re: [PATCH v2 4/7] pwm: tegra: Parametrize enable register offset","Message-ID":"","References":"<20260325-t264-pwm-v2-0-998d885984b3@nvidia.com>\n <20260325-t264-pwm-v2-4-998d885984b3@nvidia.com>\n \n <177483744958.916245.860145469758840098.b4-reply@b4>","Precedence":"bulk","X-Mailing-List":"linux-pwm@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha512;\n\tprotocol=\"application/pgp-signature\"; boundary=\"czd7pk4dwbs6pmxq\"","Content-Disposition":"inline","In-Reply-To":"<177483744958.916245.860145469758840098.b4-reply@b4>"}}]