[{"id":3669580,"web_url":"http://patchwork.ozlabs.org/comment/3669580/","msgid":"","list_archive_url":null,"date":"2026-03-26T09:35:52","subject":"Re: [PATCH v2 2/7] pwm: tegra: Avoid hard-coded max clock frequency","submitter":{"id":92481,"url":"http://patchwork.ozlabs.org/api/people/92481/","name":"Thierry Reding","email":"thierry.reding@kernel.org"},"content":"On Wed, Mar 25, 2026 at 07:17:00PM +0900, Mikko Perttunen wrote:\n> From: Yi-Wei Wang \n> \n> The clock driving the Tegra PWM IP can be sourced from different parent\n> clocks. Hence, let dev_pm_opp_set_rate() set the max clock rate based\n> upon the current parent clock that can be specified via device-tree.\n> \n> After this, the Tegra194 SoC data becomes redundant, so get rid of it.\n> \n> Signed-off-by: Yi-Wei Wang \n> Co-developed-by: Mikko Perttunen \n> Signed-off-by: Mikko Perttunen \n> ---\n> drivers/pwm/pwm-tegra.c | 16 +++-------------\n> 1 file changed, 3 insertions(+), 13 deletions(-)\n\nReviewed-by: Thierry Reding ","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=oH8Um9n/;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; helo=tor.lore.kernel.org;\n envelope-from=linux-pwm+bounces-8377-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"oH8Um9n/\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhJmp3XZGz1yGL\n\tfor ; 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a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1774517756; c=relaxed/simple;\n\tbh=Ysu//SzXdYM6Ja+X6GEXyxKMAawC5e8zz4sEbazP0d4=;\n\th=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:\n\t Content-Type:Content-Disposition:In-Reply-To;\n b=VeW7XaO9XrzQZ9BMMB/X94RcH7Yw+NAxp+rn7GmBfOxgkeCJ1ovQFaqvnpKcKJR6RZ16ZYzDydxa6h+3j6K0jw2fujdFwAFTJToA0JPrNalOlYgfzCNq+PsKQe+8o/K7x5U+Kf5FrCfmKGj7WM4DRtVSdbXP9RbYk2njF3+e6+c=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=oH8Um9n/; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1774517755;\n\tbh=Ysu//SzXdYM6Ja+X6GEXyxKMAawC5e8zz4sEbazP0d4=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=oH8Um9n/IJfBZbg973mfuAr9z2kYsZMM/BnlOSikR66gxhSLZf4n1lzFXGyMM9UfA\n\t ymFvLZuTftEjpFlHHzZc2Jv9VB9ls5q0DiKt0bgktR5VMumPeasdXaO4mEf9sSUQe/\n\t NaJDrY/mACV6K1Zeh51karwpyzkrl8OHHODXEDC3V3klyZP1+e2lbpKm8cFsa+Xarf\n\t C0sYoQC02o54ubEXk7hoca/GXtX2Ab5viJEPQpTpGQcuxYkGq0D/18gLOwZ2dkGMKy\n\t 9K+iDAunkdWXD2NtX3etjbg3hZweJGGqnelkB1yFkA82p7GKvzE7nVJtvA01QwyIAZ\n\t cjce83tWRd+cw==","Date":"Thu, 26 Mar 2026 10:35:52 +0100","From":"Thierry Reding ","To":"Mikko Perttunen ","Cc":"Thierry Reding , Uwe =?utf-8?q?Kleine-K=C3=B6?=\n\t=?utf-8?q?nig?= ,\n Jonathan Hunter , Rob Herring ,\n Krzysztof Kozlowski ,\n Conor Dooley , linux-pwm@vger.kernel.org,\n linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,\n devicetree@vger.kernel.org, Yi-Wei Wang ","Subject":"Re: [PATCH v2 2/7] pwm: tegra: Avoid hard-coded max clock frequency","Message-ID":"","References":"<20260325-t264-pwm-v2-0-998d885984b3@nvidia.com>\n <20260325-t264-pwm-v2-2-998d885984b3@nvidia.com>","Precedence":"bulk","X-Mailing-List":"linux-pwm@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha512;\n\tprotocol=\"application/pgp-signature\"; boundary=\"cusgvpbw2bgo3jwv\"","Content-Disposition":"inline","In-Reply-To":"<20260325-t264-pwm-v2-2-998d885984b3@nvidia.com>"}},{"id":3671156,"web_url":"http://patchwork.ozlabs.org/comment/3671156/","msgid":"<202603302259.NdAkuCVx-lkp@intel.com>","list_archive_url":null,"date":"2026-03-30T14:36:53","subject":"Re: [PATCH v2 2/7] pwm: tegra: Avoid hard-coded max clock frequency","submitter":{"id":67315,"url":"http://patchwork.ozlabs.org/api/people/67315/","name":"kernel test robot","email":"lkp@intel.com"},"content":"Hi Mikko,\n\nkernel test robot noticed the following build warnings:\n\n[auto build test WARNING on 11439c4635edd669ae435eec308f4ab8a0804808]\n\nurl: https://github.com/intel-lab-lkp/linux/commits/Mikko-Perttunen/dt-bindings-pwm-Document-Tegra194-and-Tegra264-controllers/20260329-233356\nbase: 11439c4635edd669ae435eec308f4ab8a0804808\npatch link: https://lore.kernel.org/r/20260325-t264-pwm-v2-2-998d885984b3%40nvidia.com\npatch subject: [PATCH v2 2/7] pwm: tegra: Avoid hard-coded max clock frequency\nconfig: nios2-allmodconfig (https://download.01.org/0day-ci/archive/20260330/202603302259.NdAkuCVx-lkp@intel.com/config)\ncompiler: nios2-linux-gcc (GCC) 11.5.0\nreproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260330/202603302259.NdAkuCVx-lkp@intel.com/reproduce)\n\nIf you fix the issue in a separate patch/commit (i.e. not just a new version of\nthe same patch/commit), kindly add following tags\n| Reported-by: kernel test robot \n| Closes: https://lore.kernel.org/oe-kbuild-all/202603302259.NdAkuCVx-lkp@intel.com/\n\nAll warnings (new ones prefixed by >>):\n\n In file included from include/linux/kernel.h:17,\n from include/linux/clk.h:13,\n from drivers/pwm/pwm-tegra.c:39:\n drivers/pwm/pwm-tegra.c: In function 'tegra_pwm_probe':\n>> include/linux/limits.h:26:25: warning: unsigned conversion from 'long long int' to 'long unsigned int' changes value from '9223372036854775807' to '4294967295' [-Woverflow]\n 26 | #define S64_MAX ((s64)(U64_MAX >> 1))\n | ^~~~~~~~~~~~~~~~~~~~~\n drivers/pwm/pwm-tegra.c:303:47: note: in expansion of macro 'S64_MAX'\n 303 | ret = dev_pm_opp_set_rate(&pdev->dev, S64_MAX);\n | ^~~~~~~\n\n\nvim +26 include/linux/limits.h\n\n3c9d017cc283df Andy Shevchenko 2023-08-04 14 \n54d50897d544c8 Masahiro Yamada 2019-03-07 15 #define U8_MAX\t\t((u8)~0U)\n54d50897d544c8 Masahiro Yamada 2019-03-07 16 #define S8_MAX\t\t((s8)(U8_MAX >> 1))\n54d50897d544c8 Masahiro Yamada 2019-03-07 17 #define S8_MIN\t\t((s8)(-S8_MAX - 1))\n54d50897d544c8 Masahiro Yamada 2019-03-07 18 #define U16_MAX\t\t((u16)~0U)\n54d50897d544c8 Masahiro Yamada 2019-03-07 19 #define S16_MAX\t\t((s16)(U16_MAX >> 1))\n54d50897d544c8 Masahiro Yamada 2019-03-07 20 #define S16_MIN\t\t((s16)(-S16_MAX - 1))\n54d50897d544c8 Masahiro Yamada 2019-03-07 21 #define U32_MAX\t\t((u32)~0U)\n3f50f132d8400e John Fastabend 2020-03-30 22 #define U32_MIN\t\t((u32)0)\n54d50897d544c8 Masahiro Yamada 2019-03-07 23 #define S32_MAX\t\t((s32)(U32_MAX >> 1))\n54d50897d544c8 Masahiro Yamada 2019-03-07 24 #define S32_MIN\t\t((s32)(-S32_MAX - 1))\n54d50897d544c8 Masahiro Yamada 2019-03-07 25 #define U64_MAX\t\t((u64)~0ULL)\n54d50897d544c8 Masahiro Yamada 2019-03-07 @26 #define S64_MAX\t\t((s64)(U64_MAX >> 1))\n54d50897d544c8 Masahiro Yamada 2019-03-07 27 #define S64_MIN\t\t((s64)(-S64_MAX - 1))\n54d50897d544c8 Masahiro Yamada 2019-03-07 28","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=f1XNAf7L;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20260325-t264-pwm-v2-2-998d885984b3@nvidia.com>"}},{"id":3671165,"web_url":"http://patchwork.ozlabs.org/comment/3671165/","msgid":"<202603302251.AFXspVqF-lkp@intel.com>","list_archive_url":null,"date":"2026-03-30T14:47:32","subject":"Re: [PATCH v2 2/7] pwm: tegra: Avoid hard-coded max clock frequency","submitter":{"id":67315,"url":"http://patchwork.ozlabs.org/api/people/67315/","name":"kernel test robot","email":"lkp@intel.com"},"content":"Hi Mikko,\n\nkernel test robot noticed the following build warnings:\n\n[auto build test WARNING on 11439c4635edd669ae435eec308f4ab8a0804808]\n\nurl: https://github.com/intel-lab-lkp/linux/commits/Mikko-Perttunen/dt-bindings-pwm-Document-Tegra194-and-Tegra264-controllers/20260329-233356\nbase: 11439c4635edd669ae435eec308f4ab8a0804808\npatch link: https://lore.kernel.org/r/20260325-t264-pwm-v2-2-998d885984b3%40nvidia.com\npatch subject: [PATCH v2 2/7] pwm: tegra: Avoid hard-coded max clock frequency\nconfig: hexagon-randconfig-r113-20260330 (https://download.01.org/0day-ci/archive/20260330/202603302251.AFXspVqF-lkp@intel.com/config)\ncompiler: clang version 23.0.0git (https://github.com/llvm/llvm-project 2cd67b8b69f78e3f95918204320c3075a74ba16c)\nsparse: v0.6.5-rc1\nreproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260330/202603302251.AFXspVqF-lkp@intel.com/reproduce)\n\nIf you fix the issue in a separate patch/commit (i.e. not just a new version of\nthe same patch/commit), kindly add following tags\n| Reported-by: kernel test robot \n| Closes: https://lore.kernel.org/oe-kbuild-all/202603302251.AFXspVqF-lkp@intel.com/\n\nsparse warnings: (new ones prefixed by >>)\n>> drivers/pwm/pwm-tegra.c:303:47: sparse: sparse: cast truncates bits from constant value (7fffffffffffffff becomes ffffffff)\n\nvim +303 drivers/pwm/pwm-tegra.c\n\n 266\t\n 267\tstatic int tegra_pwm_probe(struct platform_device *pdev)\n 268\t{\n 269\t\tstruct pwm_chip *chip;\n 270\t\tstruct tegra_pwm_chip *pc;\n 271\t\tconst struct tegra_pwm_soc *soc;\n 272\t\tint ret;\n 273\t\n 274\t\tsoc = of_device_get_match_data(&pdev->dev);\n 275\t\n 276\t\tchip = devm_pwmchip_alloc(&pdev->dev, soc->num_channels, sizeof(*pc));\n 277\t\tif (IS_ERR(chip))\n 278\t\t\treturn PTR_ERR(chip);\n 279\t\tpc = to_tegra_pwm_chip(chip);\n 280\t\n 281\t\tpc->soc = soc;\n 282\t\n 283\t\tpc->regs = devm_platform_ioremap_resource(pdev, 0);\n 284\t\tif (IS_ERR(pc->regs))\n 285\t\t\treturn PTR_ERR(pc->regs);\n 286\t\n 287\t\tplatform_set_drvdata(pdev, chip);\n 288\t\n 289\t\tpc->clk = devm_clk_get(&pdev->dev, NULL);\n 290\t\tif (IS_ERR(pc->clk))\n 291\t\t\treturn PTR_ERR(pc->clk);\n 292\t\n 293\t\tret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);\n 294\t\tif (ret)\n 295\t\t\treturn ret;\n 296\t\n 297\t\tpm_runtime_enable(&pdev->dev);\n 298\t\tret = pm_runtime_resume_and_get(&pdev->dev);\n 299\t\tif (ret)\n 300\t\t\treturn ret;\n 301\t\n 302\t\t/* Set maximum frequency of the IP */\n > 303\t\tret = dev_pm_opp_set_rate(&pdev->dev, S64_MAX);\n 304\t\tif (ret < 0) {\n 305\t\t\tdev_err(&pdev->dev, \"Failed to set max frequency: %d\\n\", ret);\n 306\t\t\tgoto put_pm;\n 307\t\t}\n 308\t\n 309\t\t/*\n 310\t\t * The requested and configured frequency may differ due to\n 311\t\t * clock register resolutions. Get the configured frequency\n 312\t\t * so that PWM period can be calculated more accurately.\n 313\t\t */\n 314\t\tpc->clk_rate = clk_get_rate(pc->clk);\n 315\t\n 316\t\t/* Set minimum limit of PWM period for the IP */\n 317\t\tpc->min_period_ns =\n 318\t\t (NSEC_PER_SEC / (pc->clk_rate >> PWM_DUTY_WIDTH)) + 1;\n 319\t\n 320\t\tpc->rst = devm_reset_control_get_exclusive(&pdev->dev, \"pwm\");\n 321\t\tif (IS_ERR(pc->rst)) {\n 322\t\t\tret = PTR_ERR(pc->rst);\n 323\t\t\tdev_err(&pdev->dev, \"Reset control is not found: %d\\n\", ret);\n 324\t\t\tgoto put_pm;\n 325\t\t}\n 326\t\n 327\t\treset_control_deassert(pc->rst);\n 328\t\n 329\t\tchip->ops = &tegra_pwm_ops;\n 330\t\n 331\t\tret = pwmchip_add(chip);\n 332\t\tif (ret < 0) {\n 333\t\t\tdev_err(&pdev->dev, \"pwmchip_add() failed: %d\\n\", ret);\n 334\t\t\treset_control_assert(pc->rst);\n 335\t\t\tgoto put_pm;\n 336\t\t}\n 337\t\n 338\t\tpm_runtime_put(&pdev->dev);\n 339\t\n 340\t\treturn 0;\n 341\tput_pm:\n 342\t\tpm_runtime_put_sync_suspend(&pdev->dev);\n 343\t\tpm_runtime_force_suspend(&pdev->dev);\n 344\t\treturn ret;\n 345\t}\n 346","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=byu97nM0;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20260325-t264-pwm-v2-2-998d885984b3@nvidia.com>"}}]