[{"id":3668998,"web_url":"http://patchwork.ozlabs.org/comment/3668998/","msgid":"","list_archive_url":null,"date":"2026-03-25T11:21:42","subject":"Re: [PATCH V2] rs6000: Fix [su]mul_highpart patterns to use unspec\n [PR122665]","submitter":{"id":91453,"url":"http://patchwork.ozlabs.org/api/people/91453/","name":"Avinash Jayakar","email":"avinashd@linux.ibm.com"},"content":"Hi Jeevitha,\n\nJust some minor comments and a general query.\n\nOn Wed, 2026-03-25 at 14:23 +0530, jeevitha wrote:\n> Hi All,\n> \n> The following patch is to fix PR122665 has been bootstrapped and\n> regtested on\n> powerpc64le-linux.\n> \n> Changes from V1:\n>   * Moved the unspec declarations from vsx.md to rs6000.md, as these\n>     will be reused in future RFC implementation.\n> \n> rs6000: Fix [su]mul_highpart patterns to use unspec [PR122665]\n> \n> The existing smul3_highpart and umul3_highpart patterns\n> incorrectly defined the high-part multiply by shifting both operands\n> before multiplication. This does not match the semantics of the\n> instructions vmulhs and vmulhu, which perform a widened\n> multiplication and then return the high part.\n> \n> This patch replaces the incorrect patterns with UNSPEC_VMULHS and\n> UNSPEC_VMULHU forms, and updates the predicate to use\n> altivec_register_operand, since these instructions accept only\n> Altivec registers.\n> \n> 2025-03-25  Jeevitha Palanisamy  \nPlease update year.\n> \n> gcc/\n> \tPR target/122665\n> \t* config/rs6000/rs6000.md (UNSPEC_VMULHS, UNSPEC_VMULHU):\n> New.\n\nNew unspec.\n> \t* config/rs6000/vsx.md (smul3_highpart): Use\n> UNSPEC_VMULHS.\n> \t(umul3_highpart): Use UNSPEC_VMULHU.\n> \n> \n> diff --git a/gcc/config/rs6000/rs6000.md\n> b/gcc/config/rs6000/rs6000.md\n> index 3089551552c..a5481df6880 100644\n> --- a/gcc/config/rs6000/rs6000.md\n> +++ b/gcc/config/rs6000/rs6000.md\n> @@ -173,6 +173,8 @@\n>     UNSPEC_XXSPLTIW_CONST\n>     UNSPEC_FMAX\n>     UNSPEC_FMIN\n> +   UNSPEC_VMULHS\n> +   UNSPEC_VMULHU\n>    ])\n>  \n>  ;;\n> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md\n> index cfad9b8c6d5..f4979e447de 100644\n> --- a/gcc/config/rs6000/vsx.md\n> +++ b/gcc/config/rs6000/vsx.md\n> @@ -6547,25 +6547,19 @@\n>     (set_attr \"size\" \"\")])\n>  \n>  (define_insn \"smul3_highpart\"\n> -  [(set (match_operand:VIlong 0 \"vsx_register_operand\" \"=v\")\n> -\t(mult:VIlong (ashiftrt\n> -\t\t       (match_operand:VIlong 1\n> \"vsx_register_operand\" \"v\")\n> -\t\t       (const_int 32))\n> -\t\t     (ashiftrt\n> -\t\t       (match_operand:VIlong 2\n> \"vsx_register_operand\" \"v\")\n> -\t\t       (const_int 32))))]\n> +  [(set (match_operand:VIlong 0 \"altivec_register_operand\" \"=v\")\n> +        (unspec:VIlong [(match_operand:VIlong 1\n> \"altivec_register_operand\" \"v\")\n> +                        (match_operand:VIlong 2\n> \"altivec_register_operand\" \"v\")]\n> +                       UNSPEC_VMULHS))]\n>    \"TARGET_POWER10\"\n>    \"vmulhs %0,%1,%2\"\n>    [(set_attr \"type\" \"veccomplex\")])\n>  \n>  (define_insn \"umul3_highpart\"\n> -  [(set (match_operand:VIlong 0 \"vsx_register_operand\" \"=v\")\n> -\t(us_mult:VIlong (ashiftrt\n> -\t\t\t  (match_operand:VIlong 1\n> \"vsx_register_operand\" \"v\")\n> -\t\t\t  (const_int 32))\n> -\t\t\t(ashiftrt\n> -\t\t\t  (match_operand:VIlong 2\n> \"vsx_register_operand\" \"v\")\n> -\t\t\t  (const_int 32))))]\n> +  [(set (match_operand:VIlong 0 \"altivec_register_operand\" \"=v\")\n> +        (unspec:VIlong [(match_operand:VIlong 1\n> \"altivec_register_operand\" \"v\")\n> +                        (match_operand:VIlong 2\n> \"altivec_register_operand\" \"v\")]\n> +                       UNSPEC_VMULHU))]\n>    \"TARGET_POWER10\"\n>    \"vmulhu %0,%1,%2\"\n>    [(set_attr \"type\" \"veccomplex\")])\n\nJust had a query regarding the previous way it was implemented. So for\nunsigned case in the V4SI mode, \n\n\n (ashiftrt (match_operand:V4SI 1) (const_int 32))\n\nShould have been optimized to 0 right, and therefore fail to generate\nanything. Does it mean that in backend we do not match such patterns?\n\nThanks and regards,\nAvinash Jayakar","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=ng+AYMR8;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)","sourceware.org;\n\tdkim=pass (2048-bit key,\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=ng+AYMR8","sourceware.org;\n dmarc=none (p=none dis=none) header.from=linux.ibm.com","sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com","server2.sourceware.org;\n arc=none smtp.remote-ip=148.163.156.1"],"Received":["from vm01.sourceware.org (vm01.sourceware.org\n [IPv6:2620:52:6:3111::32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fgkyl2NLjz1xy1\n\tfor ; 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charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","User-Agent":"Evolution 3.56.2 (3.56.2-2.fc42) ","MIME-Version":"1.0","X-TM-AS-GCONF":"00","X-Proofpoint-ORIG-GUID":"WflHl-FkkBNzGUIb0MuaTT0Yn-GlRahh","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwMzI1MDA4MCBTYWx0ZWRfX0oZi/jBiZWtI\n ofVFIRW3MdY++INZz465TLfW+ZnkxVMD0e3B8NiqWqvVusW/OBMbnAbneA0oo9fKXyj66zOcrCw\n QpBBkiZU+hA8E4g6Rq+Zo91b5rFwtiqS3tjGD2iLtPgPjE5Rq1x4heq19dajm/W1aEOzVPZxy1M\n sSTxehw/8MqurUe/uIX5ygMI4BODtWP0k2SriCjdz9Lf1vo8q8NR/NDiMc1dnrQppez4MNtIjkf\n 2SvhJzfW2+woJpGdHMKAngUp9FdzPQMBNev+0y3+TeWn602acWbNGBSDuBMx8vVB6jWUcyYl19D\n Lb0/sGRFRZbf0Pf5cC/heHhx6qz9RVt5LYwLG3UPXkt9zdmMfYDotEBGVrl3VA/DMcL94i44mrq\n BiJO8/zgvn1bH2VncyjL9uoEr3NUyArduWmbjk5WrrlL2HoWsvjoUgzc8YcVh16ukU/kM4BBwqo\n uM14G1C5+f5Z3pXDOyA==","X-Proofpoint-GUID":"WflHl-FkkBNzGUIb0MuaTT0Yn-GlRahh","X-Authority-Analysis":"v=2.4 cv=OsZCCi/t c=1 sm=1 tr=0 ts=69c3c54c cx=c_pps\n a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17\n a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=RnoormkPH1_aCDwRdu11:22 a=U7nrCbtTmkRpXpFmAIza:22 a=VnNF1IyMAAAA:8\n a=fYv5EycnZ8VRK3qiwVYA:9 a=QEXdDO2ut3YA:10","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-03-25_03,2026-03-24_01,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n impostorscore=0 adultscore=0 clxscore=1015 phishscore=0 suspectscore=0\n lowpriorityscore=0 priorityscore=1501 bulkscore=0 spamscore=0 malwarescore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603250080","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"}},{"id":3672022,"web_url":"http://patchwork.ozlabs.org/comment/3672022/","msgid":"<72b795b7-6a20-41bf-b56e-af996a53ecfb@linux.ibm.com>","list_archive_url":null,"date":"2026-04-01T05:00:40","subject":"[PING^1] [PATCH V2] rs6000: Fix [su]mul_highpart patterns to use\n unspec [PR122665]","submitter":{"id":88218,"url":"http://patchwork.ozlabs.org/api/people/88218/","name":"jeevitha","email":"jeevitha@linux.ibm.com"},"content":"Gentle ping!\n\n\nThanks & Regards\n Jeevitha\n\nOn 25/03/26 2:23 pm, jeevitha wrote:\n> Hi All,\n> \n> The following patch is to fix PR122665 has been bootstrapped and regtested on\n> powerpc64le-linux.\n> \n> Changes from V1:\n> * Moved the unspec declarations from vsx.md to rs6000.md, as these\n> will be reused in future RFC implementation.\n> \n> rs6000: Fix [su]mul_highpart patterns to use unspec [PR122665]\n> \n> The existing smul3_highpart and umul3_highpart patterns\n> incorrectly defined the high-part multiply by shifting both operands\n> before multiplication. This does not match the semantics of the\n> instructions vmulhs and vmulhu, which perform a widened\n> multiplication and then return the high part.\n> \n> This patch replaces the incorrect patterns with UNSPEC_VMULHS and\n> UNSPEC_VMULHU forms, and updates the predicate to use\n> altivec_register_operand, since these instructions accept only\n> Altivec registers.\n> \n> 2025-03-25 Jeevitha Palanisamy \n> \n> gcc/\n> \tPR target/122665\n> \t* config/rs6000/rs6000.md (UNSPEC_VMULHS, UNSPEC_VMULHU): New.\n> \t* config/rs6000/vsx.md (smul3_highpart): Use UNSPEC_VMULHS.\n> \t(umul3_highpart): Use UNSPEC_VMULHU.\n> \n> \n> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md\n> index 3089551552c..a5481df6880 100644\n> --- a/gcc/config/rs6000/rs6000.md\n> +++ b/gcc/config/rs6000/rs6000.md\n> @@ -173,6 +173,8 @@\n> UNSPEC_XXSPLTIW_CONST\n> UNSPEC_FMAX\n> UNSPEC_FMIN\n> + UNSPEC_VMULHS\n> + UNSPEC_VMULHU\n> ])\n> \n> ;;\n> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md\n> index cfad9b8c6d5..f4979e447de 100644\n> --- a/gcc/config/rs6000/vsx.md\n> +++ b/gcc/config/rs6000/vsx.md\n> @@ -6547,25 +6547,19 @@\n> (set_attr \"size\" \"\")])\n> \n> (define_insn \"smul3_highpart\"\n> - [(set (match_operand:VIlong 0 \"vsx_register_operand\" \"=v\")\n> -\t(mult:VIlong (ashiftrt\n> -\t\t (match_operand:VIlong 1 \"vsx_register_operand\" \"v\")\n> -\t\t (const_int 32))\n> -\t\t (ashiftrt\n> -\t\t (match_operand:VIlong 2 \"vsx_register_operand\" \"v\")\n> -\t\t (const_int 32))))]\n> + [(set (match_operand:VIlong 0 \"altivec_register_operand\" \"=v\")\n> + (unspec:VIlong [(match_operand:VIlong 1 \"altivec_register_operand\" \"v\")\n> + (match_operand:VIlong 2 \"altivec_register_operand\" \"v\")]\n> + UNSPEC_VMULHS))]\n> \"TARGET_POWER10\"\n> \"vmulhs %0,%1,%2\"\n> [(set_attr \"type\" \"veccomplex\")])\n> \n> (define_insn \"umul3_highpart\"\n> - [(set (match_operand:VIlong 0 \"vsx_register_operand\" \"=v\")\n> -\t(us_mult:VIlong (ashiftrt\n> -\t\t\t (match_operand:VIlong 1 \"vsx_register_operand\" \"v\")\n> -\t\t\t (const_int 32))\n> -\t\t\t(ashiftrt\n> -\t\t\t (match_operand:VIlong 2 \"vsx_register_operand\" \"v\")\n> -\t\t\t (const_int 32))))]\n> + [(set (match_operand:VIlong 0 \"altivec_register_operand\" \"=v\")\n> + (unspec:VIlong [(match_operand:VIlong 1 \"altivec_register_operand\" \"v\")\n> + (match_operand:VIlong 2 \"altivec_register_operand\" \"v\")]\n> + UNSPEC_VMULHU))]\n> \"TARGET_POWER10\"\n> \"vmulhu %0,%1,%2\"\n> [(set_attr \"type\" \"veccomplex\")])\n>","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=L0Y5pH0W;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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