[{"id":3670418,"web_url":"http://patchwork.ozlabs.org/comment/3670418/","msgid":"<87v7ehgu24.fsf@suse.de>","list_archive_url":null,"date":"2026-03-27T15:40:03","subject":"Re: [PATCH v3 2/2] tests/qtest: Add Intel IOMMU bare-metal test","submitter":{"id":85343,"url":"http://patchwork.ozlabs.org/api/people/85343/","name":"Fabiano Rosas","email":"farosas@suse.de"},"content":"Fengyuan Yu <15fengyuan@gmail.com> writes:\n\n> Add a qtest suite for the Intel IOMMU (VT-d) device on the Q35 machine.\n> The test exercises both Legacy and Scalable translation modes using\n> iommu-testdev and the qos-intel-iommu helpers, without requiring any\n> guest kernel or firmware.\n>\n> The test validates:\n> - Legacy-mode Root Entry Table and Context Entry Table configuration\n> - Scalable-mode Context Entry, PASID Directory, and PASID Table setup\n> - Legacy-mode 4-level page table walks for 48-bit address translation\n> - Scalable-mode second-level and first-level 4-level page table walks\n> - Pass-through mode in both Legacy and Scalable modes\n> - DMA transaction execution with memory content verification\n>\n> Reviewed-by: Chao Liu \n> Signed-off-by: Fengyuan Yu <15fengyuan@gmail.com>\n> ---\n> MAINTAINERS | 1 +\n> tests/qtest/iommu-intel-test.c | 216 +++++++++++++++++++++++++++++++++\n> tests/qtest/meson.build | 2 +\n> 3 files changed, 219 insertions(+)\n> create mode 100644 tests/qtest/iommu-intel-test.c\n>\n> diff --git a/MAINTAINERS b/MAINTAINERS\n> index ba0901bf4f..420f7ab6cf 100644\n> --- a/MAINTAINERS\n> +++ b/MAINTAINERS\n> @@ -4016,6 +4016,7 @@ F: hw/i386/intel_iommu_accel.*\n> F: include/hw/i386/intel_iommu.h\n> F: tests/functional/x86_64/test_intel_iommu.py\n> F: tests/qtest/intel-iommu-test.c\n> +F: tests/qtest/iommu-intel-test.c\n> \n> AMD-Vi Emulation\n> M: Alejandro Jimenez \n> diff --git a/tests/qtest/iommu-intel-test.c b/tests/qtest/iommu-intel-test.c\n> new file mode 100644\n> index 0000000000..a52c45e298\n> --- /dev/null\n> +++ b/tests/qtest/iommu-intel-test.c\n> @@ -0,0 +1,216 @@\n> +/*\n> + * QTest for Intel IOMMU (VT-d) with iommu-testdev\n> + *\n> + * This QTest file is used to test the Intel IOMMU with iommu-testdev so that\n> + * we can test VT-d without any guest kernel or firmware.\n> + *\n> + * Copyright (c) 2026 Fengyuan Yu <15fengyuan@gmail.com>\n> + *\n> + * SPDX-License-Identifier: GPL-2.0-or-later\n> + */\n> +\n> +#include \"qemu/osdep.h\"\n> +#include \"libqtest.h\"\n> +#include \"libqos/pci.h\"\n> +#include \"libqos/pci-pc.h\"\n> +#include \"hw/i386/intel_iommu_internal.h\"\n> +#include \"hw/misc/iommu-testdev.h\"\n> +#include \"libqos/qos-intel-iommu.h\"\n> +\n> +#define DMA_LEN 4\n> +\n> +static uint64_t intel_iommu_expected_gpa(uint64_t iova)\n> +{\n> + return (QVTD_PT_VAL & VTD_PAGE_MASK_4K) + (iova & 0xfff);\n> +}\n> +\n> +static void save_fn(QPCIDevice *dev, int devfn, void *data)\n> +{\n> + QPCIDevice **pdev = (QPCIDevice **) data;\n> +\n> + *pdev = dev;\n> +}\n> +\n> +static QPCIDevice *setup_qtest_pci_device(QTestState *qts, QPCIBus **pcibus,\n> + QPCIBar *bar)\n> +{\n> + QPCIDevice *dev = NULL;\n> +\n> + *pcibus = qpci_new_pc(qts, NULL);\n> + g_assert(*pcibus != NULL);\n> +\n> + qpci_device_foreach(*pcibus, IOMMU_TESTDEV_VENDOR_ID,\n> + IOMMU_TESTDEV_DEVICE_ID, save_fn, &dev);\n> +\n> + g_assert(dev);\n> + qpci_device_enable(dev);\n> + *bar = qpci_iomap(dev, 0, NULL);\n> + g_assert_false(bar->is_io);\n> +\n> + return dev;\n> +}\n> +\n> +static const char *qvtd_iommu_args(QVTDTransMode mode)\n> +{\n> + switch (mode) {\n> + case QVTD_TM_SCALABLE_FLT:\n> + return \"-device intel-iommu,x-scalable-mode=on,x-flts=on \";\n> + case QVTD_TM_SCALABLE_PT:\n> + case QVTD_TM_SCALABLE_SLT:\n> + return \"-device intel-iommu,x-scalable-mode=on \";\n> + default:\n> + return \"-device intel-iommu \";\n> + }\n> +}\n> +\n> +static bool qvtd_check_caps(QTestState *qts, QVTDTransMode mode)\n> +{\n> + uint64_t ecap = qtest_readq(qts,\n> + Q35_HOST_BRIDGE_IOMMU_ADDR + DMAR_ECAP_REG);\n> +\n> + /* All scalable modes require SMTS */\n> + if (qvtd_is_scalable(mode) && !(ecap & VTD_ECAP_SMTS)) {\n> + g_test_skip(\"ECAP.SMTS not supported\");\n> + return false;\n> + }\n> +\n> + switch (mode) {\n> + case QVTD_TM_SCALABLE_PT:\n> + if (!(ecap & VTD_ECAP_PT)) {\n> + g_test_skip(\"ECAP.PT not supported\");\n> + return false;\n> + }\n> + break;\n> + case QVTD_TM_SCALABLE_SLT:\n> + if (!(ecap & VTD_ECAP_SSTS)) {\n> + g_test_skip(\"ECAP.SSTS not supported\");\n> + return false;\n> + }\n> + break;\n> + case QVTD_TM_SCALABLE_FLT:\n> + if (!(ecap & VTD_ECAP_FSTS)) {\n> + g_test_skip(\"ECAP.FSTS not supported\");\n> + return false;\n> + }\n> + break;\n> + default:\n> + break;\n> + }\n> +\n> + return true;\n> +}\n> +\n> +static void run_intel_iommu_translation(const QVTDTestConfig *cfg)\n> +{\n> + QTestState *qts;\n> + QPCIBus *pcibus;\n> + QPCIDevice *dev;\n> + QPCIBar bar;\n> +\n> + if (!qtest_has_machine(\"q35\")) {\n> + g_test_skip(\"q35 machine not available\");\n> + return;\n> + }\n> +\n> + /* Initialize QEMU environment for Intel IOMMU testing */\n> + qts = qtest_initf(\"-machine q35 -smp 1 -m 512 -net none \"\n> + \"%s -device iommu-testdev\",\n> + qvtd_iommu_args(cfg->trans_mode));\n> +\n> + /* Check CAP/ECAP capabilities for required translation mode */\n> + if (!qvtd_check_caps(qts, cfg->trans_mode)) {\n> + qtest_quit(qts);\n> + return;\n> + }\n> +\n> + /* Setup and configure IOMMU-testdev PCI device */\n> + dev = setup_qtest_pci_device(qts, &pcibus, &bar);\n> + g_assert(dev);\n> +\n> + g_test_message(\"### Intel IOMMU translation mode=%d ###\", cfg->trans_mode);\n> + qvtd_run_translation_case(qts, dev, bar, Q35_HOST_BRIDGE_IOMMU_ADDR, cfg);\n> + g_free(dev);\n> + qpci_free_pc(pcibus);\n> + qtest_quit(qts);\n> +}\n> +\n> +static void test_intel_iommu_legacy_pt(void)\n> +{\n> + QVTDTestConfig cfg = {\n> + .trans_mode = QVTD_TM_LEGACY_PT,\n> + .dma_gpa = QVTD_IOVA, /* pass-through: GPA == IOVA */\n> + .dma_len = DMA_LEN,\n> + .expected_result = 0,\n> + };\n> +\n> + run_intel_iommu_translation(&cfg);\n> +}\n> +\n> +static void test_intel_iommu_legacy_trans(void)\n> +{\n> + QVTDTestConfig cfg = {\n> + .trans_mode = QVTD_TM_LEGACY_TRANS,\n> + .dma_gpa = intel_iommu_expected_gpa(QVTD_IOVA),\n> + .dma_len = DMA_LEN,\n> + .expected_result = 0,\n> + };\n> +\n> + run_intel_iommu_translation(&cfg);\n> +}\n> +\n> +static void test_intel_iommu_scalable_pt(void)\n> +{\n> + QVTDTestConfig cfg = {\n> + .trans_mode = QVTD_TM_SCALABLE_PT,\n> + .dma_gpa = QVTD_IOVA, /* pass-through: GPA == IOVA */\n> + .dma_len = DMA_LEN,\n> + .expected_result = 0,\n> + };\n> +\n> + run_intel_iommu_translation(&cfg);\n> +}\n> +\n> +static void test_intel_iommu_scalable_slt(void)\n> +{\n> + QVTDTestConfig cfg = {\n> + .trans_mode = QVTD_TM_SCALABLE_SLT,\n> + .dma_gpa = intel_iommu_expected_gpa(QVTD_IOVA),\n> + .dma_len = DMA_LEN,\n> + .expected_result = 0,\n> + };\n> +\n> + run_intel_iommu_translation(&cfg);\n> +}\n> +\n> +static void test_intel_iommu_scalable_flt(void)\n> +{\n> + QVTDTestConfig cfg = {\n> + .trans_mode = QVTD_TM_SCALABLE_FLT,\n> + .dma_gpa = intel_iommu_expected_gpa(QVTD_IOVA),\n> + .dma_len = DMA_LEN,\n> + .expected_result = 0,\n> + };\n> +\n> + run_intel_iommu_translation(&cfg);\n> +}\n> +\n> +int main(int argc, char **argv)\n> +{\n> + g_test_init(&argc, &argv, NULL);\n> +\n> + /* Legacy mode tests */\n> + qtest_add_func(\"/iommu-testdev/intel/legacy-pt\",\n> + test_intel_iommu_legacy_pt);\n> + qtest_add_func(\"/iommu-testdev/intel/legacy-trans\",\n> + test_intel_iommu_legacy_trans);\n> +\n> + /* Scalable mode tests */\n> + qtest_add_func(\"/iommu-testdev/intel/scalable-pt\",\n> + test_intel_iommu_scalable_pt);\n> + qtest_add_func(\"/iommu-testdev/intel/scalable-slt\",\n> + test_intel_iommu_scalable_slt);\n> + qtest_add_func(\"/iommu-testdev/intel/scalable-flt\",\n> + test_intel_iommu_scalable_flt);\n> +\n> + return g_test_run();\n> +}\n> diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build\n> index be4fa627b5..264bce9f81 100644\n> --- a/tests/qtest/meson.build\n> +++ b/tests/qtest/meson.build\n> @@ -96,6 +96,8 @@ qtests_i386 = \\\n> (config_all_devices.has_key('CONFIG_SDHCI_PCI') ? ['fuzz-sdcard-test'] : []) + \\\n> (config_all_devices.has_key('CONFIG_ESP_PCI') ? ['am53c974-test'] : []) + \\\n> (config_all_devices.has_key('CONFIG_VTD') ? ['intel-iommu-test'] : []) + \\\n> + (config_all_devices.has_key('CONFIG_VTD') and\n> + config_all_devices.has_key('CONFIG_IOMMU_TESTDEV') ? ['iommu-intel-test'] : []) + \\\n> (host_os != 'windows' and \\\n> config_all_devices.has_key('CONFIG_ACPI_ERST') ? ['erst-test'] : []) + \\\n> (config_all_devices.has_key('CONFIG_PCIE_PORT') and \\\n\nReviewed-by: Fabiano Rosas ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=suse.de header.i=@suse.de header.a=rsa-sha256\n header.s=susede2_rsa header.b=zJdii8qa;\n\tdkim=pass header.d=suse.de header.i=@suse.de header.a=ed25519-sha256\n header.s=susede2_ed25519 header.b=alrADyNa;\n\tdkim=pass (1024-bit key) header.d=suse.de header.i=@suse.de\n header.a=rsa-sha256 header.s=susede2_rsa header.b=zJdii8qa;\n\tdkim=neutral header.d=suse.de header.i=@suse.de header.a=ed25519-sha256\n header.s=susede2_ed25519 header.b=alrADyNa;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)","smtp-out2.suse.de;\n\tnone"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fj4bs2KQbz1yFr\n\tfor ; Sat, 28 Mar 2026 02:40:41 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1w69IE-0001Rf-Nw; Fri, 27 Mar 2026 11:40:14 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from ) id 1w69IB-0001OI-1l\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 11:40:11 -0400","from smtp-out2.suse.de ([2a07:de40:b251:101:10:150:64:2])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from ) id 1w69I8-0001Dg-J4\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 11:40:10 -0400","from imap1.dmz-prg2.suse.org (unknown [10.150.64.97])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest\n SHA256)\n (No client certificate requested)\n by smtp-out2.suse.de (Postfix) with ESMTPS id 88B515BD9A;\n Fri, 27 Mar 2026 15:40:05 +0000 (UTC)","from imap1.dmz-prg2.suse.org (localhost [127.0.0.1])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest\n SHA256)\n (No client certificate requested)\n by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 242C04A0A2;\n Fri, 27 Mar 2026 15:40:04 +0000 (UTC)","from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167])\n by imap1.dmz-prg2.suse.org with ESMTPSA id h20QOdSkxml6GwAAD6G6ig\n (envelope-from ); Fri, 27 Mar 2026 15:40:04 +0000"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de;\n s=susede2_rsa;\n t=1774626005;\n h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc:\n mime-version:mime-version:content-type:content-type:\n in-reply-to:in-reply-to:references:references;\n bh=Du5X0Rd6QmmM3pwqzCM2kpZq2MgX34sdd2CBHs0AL4o=;\n b=zJdii8qaNDX1/8i57gL3XA05crxx8ZjXjjUuZg60q8V3bFvMjYB4QFGdaO0oer7aIU807H\n 9tqIoK8VgBQyk5Mfdy5w5KvKXPO+YdLn0pVRrIYAZBtl/bFRQOc3tcFXwXWusH5zZ9S0pX\n VuoZwEdyxGmFH+VxTPX/L/5R2/bE8qc=","v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de;\n s=susede2_ed25519; t=1774626005;\n h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc:\n mime-version:mime-version:content-type:content-type:\n in-reply-to:in-reply-to:references:references;\n bh=Du5X0Rd6QmmM3pwqzCM2kpZq2MgX34sdd2CBHs0AL4o=;\n b=alrADyNaNqbIhERmvinDtc3B/NPnqMvuMa3b0S2MIbD6ZVtAqjigFdQUgv8WJTCZ5sxZUL\n xTLU3kGjRO3iJaBA==","v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de;\n s=susede2_rsa;\n t=1774626005;\n h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc:\n mime-version:mime-version:content-type:content-type:\n in-reply-to:in-reply-to:references:references;\n bh=Du5X0Rd6QmmM3pwqzCM2kpZq2MgX34sdd2CBHs0AL4o=;\n b=zJdii8qaNDX1/8i57gL3XA05crxx8ZjXjjUuZg60q8V3bFvMjYB4QFGdaO0oer7aIU807H\n 9tqIoK8VgBQyk5Mfdy5w5KvKXPO+YdLn0pVRrIYAZBtl/bFRQOc3tcFXwXWusH5zZ9S0pX\n VuoZwEdyxGmFH+VxTPX/L/5R2/bE8qc=","v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de;\n s=susede2_ed25519; t=1774626005;\n h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc:\n mime-version:mime-version:content-type:content-type:\n in-reply-to:in-reply-to:references:references;\n bh=Du5X0Rd6QmmM3pwqzCM2kpZq2MgX34sdd2CBHs0AL4o=;\n b=alrADyNaNqbIhERmvinDtc3B/NPnqMvuMa3b0S2MIbD6ZVtAqjigFdQUgv8WJTCZ5sxZUL\n xTLU3kGjRO3iJaBA=="],"From":"Fabiano Rosas ","To":"Fengyuan Yu <15fengyuan@gmail.com>, \"Michael S. Tsirkin\" ,\n Jason Wang , Yi Liu , =?utf-8?q?Cl?=\n\t=?utf-8?q?=C3=A9ment?= Mathieu--Drif ,\n Laurent Vivier , Paolo Bonzini ,\n Tao Tang ","Cc":"qemu-devel@nongnu.org, Chao Liu , Fengyuan Yu\n <15fengyuan@gmail.com>","Subject":"Re: [PATCH v3 2/2] tests/qtest: Add Intel IOMMU bare-metal test","In-Reply-To":"\n ","References":"\n ","Date":"Fri, 27 Mar 2026 12:40:03 -0300","Message-ID":"<87v7ehgu24.fsf@suse.de>","MIME-Version":"1.0","Content-Type":"text/plain","X-Spam-Score":"-2.80","X-Spamd-Result":"default: False [-2.80 / 50.00]; BAYES_HAM(-3.00)[100.00%];\n SUSPICIOUS_RECIPS(1.50)[]; NEURAL_HAM_LONG(-1.00)[-1.000];\n NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain];\n FREEMAIL_ENVRCPT(0.00)[gmail.com]; RCVD_TLS_ALL(0.00)[];\n ARC_NA(0.00)[]; MISSING_XM_UA(0.00)[];\n RCVD_VIA_SMTP_AUTH(0.00)[];\n FUZZY_RATELIMITED(0.00)[rspamd.com]; TO_DN_SOME(0.00)[];\n MIME_TRACE(0.00)[0:+]; TAGGED_RCPT(0.00)[];\n MID_RHS_MATCH_FROM(0.00)[]; RCPT_COUNT_SEVEN(0.00)[11];\n FROM_HAS_DN(0.00)[]; FREEMAIL_CC(0.00)[nongnu.org,gmail.com];\n FREEMAIL_TO(0.00)[gmail.com,redhat.com,intel.com,bull.com,phytium.com.cn];\n FROM_EQ_ENVFROM(0.00)[]; RCVD_COUNT_TWO(0.00)[2];\n TO_MATCH_ENVRCPT_ALL(0.00)[];\n DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519];\n DBL_BLOCKED_OPENRESOLVER(0.00)[oracle.com:email,\n imap1.dmz-prg2.suse.org:helo,\n suse.de:mid, suse.de:email]","Received-SPF":"pass client-ip=2a07:de40:b251:101:10:150:64:2;\n envelope-from=farosas@suse.de; helo=smtp-out2.suse.de","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3670971,"web_url":"http://patchwork.ozlabs.org/comment/3670971/","msgid":"","list_archive_url":null,"date":"2026-03-30T09:11:30","subject":"Re: [PATCH v3 2/2] tests/qtest: Add Intel IOMMU bare-metal test","submitter":{"id":91412,"url":"http://patchwork.ozlabs.org/api/people/91412/","name":"Tao Tang","email":"tangtao1634@phytium.com.cn"},"content":"Hi Fengyuan,\n\nOn 2026/3/25 15:09, Fengyuan Yu wrote:\n> Add a qtest suite for the Intel IOMMU (VT-d) device on the Q35 machine.\n> The test exercises both Legacy and Scalable translation modes using\n> iommu-testdev and the qos-intel-iommu helpers, without requiring any\n> guest kernel or firmware.\n>\n> The test validates:\n> - Legacy-mode Root Entry Table and Context Entry Table configuration\n> - Scalable-mode Context Entry, PASID Directory, and PASID Table setup\n> - Legacy-mode 4-level page table walks for 48-bit address translation\n> - Scalable-mode second-level and first-level 4-level page table walks\n> - Pass-through mode in both Legacy and Scalable modes\n> - DMA transaction execution with memory content verification\n>\n> Reviewed-by: Chao Liu \n> Signed-off-by: Fengyuan Yu <15fengyuan@gmail.com>\n\nReviewed-by: Tao Tang ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Mon, 30 Mar 2026 05:11:39 -0400","from prodtpl.icoremail.net (unknown [10.12.1.20])\n by hzbj-icmmx-6 (Coremail) with SMTP id AQAAfwDnn2dEPspp1u83AA--.22301S2;\n Mon, 30 Mar 2026 17:11:32 +0800 (CST)","from [10.31.91.158] (unknown [218.76.62.144])\n by mail (Coremail) with SMTP id AQAAf8DwsJJCPsppcm0HAA--.15710S2;\n Mon, 30 Mar 2026 17:11:31 +0800 (CST)"],"Message-ID":"","Date":"Mon, 30 Mar 2026 17:11:30 +0800","MIME-Version":"1.0","User-Agent":"Mozilla Thunderbird","Subject":"Re: [PATCH v3 2/2] tests/qtest: Add Intel IOMMU bare-metal test","To":"Fengyuan Yu <15fengyuan@gmail.com>, \"Michael S. Tsirkin\" ,\n Jason Wang , Yi Liu , =?utf-8?q?Cl?=\n\t=?utf-8?q?=C3=A9ment_Mathieu--Drif?= ,\n Fabiano Rosas , Laurent Vivier ,\n Paolo Bonzini ","Cc":"qemu-devel@nongnu.org, Chao Liu ","References":"\n ","From":"Tao Tang ","In-Reply-To":"\n ","Content-Type":"text/plain; charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","X-CM-TRANSID":"AQAAf8DwsJJCPsppcm0HAA--.15710S2","X-CM-SenderInfo":"pwdqw3tdrrljuu6sx5pwlxzhxfrphubq/1tbiAQAKBWnJfH8DuwAAsV","X-Coremail-Antispam":"1Uk129KBjvdXoW7JFW7Kr4kKF4xXrW3XF4fXwb_yoWfCrg_ur\n 1rCrykZw4DXr4fJw45KFsxXrW0kr4vgw4Igr1Ikry5Aas7KrsrJrn7XFnYvrZavrZxGFya\n krn8Ca15Crs7XjkaLaAFLSUrUUUUbb8apTn2vfkv8UJUUUU8wcxFpf9Il3svdxBIdaVrnU\n Uv73VFW2AGmfu7jjvjm3AaLaJ3UjIYCTnIWjDUYxBIdaVFxhVjvjDU0xZFpf9x0zRUUUUU\n UUUU=","Received-SPF":"pass client-ip=129.150.39.64;\n envelope-from=tangtao1634@phytium.com.cn; helo=sgoci-sdnproxy-4.icoremail.net","X-Spam_score_int":"1","X-Spam_score":"0.1","X-Spam_bar":"/","X-Spam_report":"(0.1 / 5.0 requ) BAYES_00=-1.9,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1, RCVD_IN_VALIDITY_RPBL_BLOCKED=1,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}}]