[{"id":3669503,"web_url":"http://patchwork.ozlabs.org/comment/3669503/","msgid":"","list_archive_url":null,"date":"2026-03-26T07:13:29","subject":"Re: [PATCH v5 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition\n trace support","submitter":{"id":66060,"url":"http://patchwork.ozlabs.org/api/people/66060/","name":"Anand Moon","email":"linux.amoon@gmail.com"},"content":"Hi Shawn,\n\nOn Wed, 25 Mar 2026 at 07:29, Shawn Lin wrote:\n>\n> Rockchip platforms provide a 64x4 bytes debug FIFO to trace the\n> LTSSM history. Any LTSSM change will be recorded. It's useful\n> for debug purpose, for example link failure, etc.\n>\n> Signed-off-by: Shawn Lin \n> ---\nTested-by: Anand Moon \n\nThanks\n-Anand","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=DaMcgFKE;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; helo=sto.lore.kernel.org;\n envelope-from=linux-pci+bounces-51143-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com\n header.b=\"DaMcgFKE\"","smtp.subspace.kernel.org;\n arc=pass smtp.client-ip=209.85.208.47","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=gmail.com"],"Received":["from sto.lore.kernel.org (sto.lore.kernel.org\n [IPv6:2600:3c09:e001:a7::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhFPg3splz1y1G\n\tfor ; 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Thu, 26 Mar 2026\n 00:13:45 -0700 (PDT)","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","References":"<1774403912-210670-1-git-send-email-shawn.lin@rock-chips.com>\n <1774403912-210670-4-git-send-email-shawn.lin@rock-chips.com>","In-Reply-To":"<1774403912-210670-4-git-send-email-shawn.lin@rock-chips.com>","From":"Anand Moon ","Date":"Thu, 26 Mar 2026 12:43:29 +0530","X-Gm-Features":"AQROBzDOhjtwDHUqjyR7aLHKrElwwWK5j8GxED5sK_-NhNXgE0WUA3wwNc4lR-Q","Message-ID":"\n ","Subject":"Re: [PATCH v5 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition\n trace support","To":"Shawn Lin ","Cc":"Manivannan Sadhasivam ,\n Bjorn Helgaas ,\n\tlinux-rockchip@lists.infradead.org, linux-pci@vger.kernel.org,\n\tlinux-trace-kernel@vger.kernel.org, linux-doc@vger.kernel.org,\n\tSteven Rostedt ","Content-Type":"text/plain; charset=\"UTF-8\""}}]