[{"id":3669834,"web_url":"http://patchwork.ozlabs.org/comment/3669834/","msgid":"","list_archive_url":null,"date":"2026-03-26T16:44:51","subject":"RE: [PATCH 1/1] target/i386/kvm: Use logical counter index for AMD\n PMU getter","submitter":{"id":88429,"url":"http://patchwork.ozlabs.org/api/people/88429/","name":"Chen, Zide","email":"zide.chen@intel.com"},"content":"> -----Original Message-----\n> From: Dongli Zhang \n> Sent: Tuesday, March 24, 2026 7:13 PM\n> To: qemu-devel@nongnu.org\n> Cc: kvm@vger.kernel.org; pbonzini@redhat.com; mtosatti@redhat.com;\n> dapeng1.mi@linux.intel.com; Liu, Zhao1 ;\n> sandipan.das@amd.com; Chen, Zide ;\n> joe.jin@oracle.com\n> Subject: [PATCH 1/1] target/i386/kvm: Use logical counter index for AMD PMU\n> getter\n> \n> For Intel PMU, the counter and selector MSR ranges are disjoint. AMD PMU\n> behaves the same way when PerfCore is unavailable.\n> \n> However, once PerfCore is present, AMD PMU switches to an interleaved\n> layout in which selector and counter MSRs share a single alternating range.\n> \n> MSR_F15H_PERF_CTL0 = 0xc0010200\n> MSR_F15H_PERF_CTR0 = 0xc0010201\n> ... ...\n> ... ...\n> MSR_F15H_PERF_CTL5 = 0xc001020a\n> MSR_F15H_PERF_CTR5 = 0xc001020b\n> \n> The commit 4c7f05232c (\"target/i386/kvm: reset AMD PMU registers during\n> VM\n> reset\") added the getter/putter pair for AMD PMU MSRs to clear them on\n> reset, but it ignored that, without PerfCore, AMD reuses alternating MSR\n> addresses for selectors and counters. env->msr_gp_counters[] holds the raw\n> counts and env->msr_gp_evtsel[] holds the selectors, so with the interleaved\n> layout we must translate the MSR address back to the logical counter index\n> instead of treating the interleaved slot as the array index.\n> \n> The arrays are sized to MAX_GP_COUNTERS = 18, so the code never writes\n> past the end. And in the reset path QEMU simply zeroes everything, so that\n> use case still works.\n> \n> However, the live migration is broken. The PMU state is stored at the wrong\n> indices, so the destination VM reloads mismatched selector/counter pairs. Fix\n> the getter to use the logical counter index rather than the raw interleaved\n> offset.\n> \n> Fixes: 4c7f05232c (\"target/i386/kvm: reset AMD PMU registers during VM\n> reset\")\n> Signed-off-by: Dongli Zhang \n> ---\n\nReviewed-by: Zide Chen \n\n> target/i386/kvm/kvm.c | 4 ++--\n> 1 file changed, 2 insertions(+), 2 deletions(-)\n> \n> diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index\n> 9e352882c8..b4e549c62b 100644\n> --- a/target/i386/kvm/kvm.c\n> +++ b/target/i386/kvm/kvm.c\n> @@ -5239,9 +5239,9 @@ static int kvm_get_msrs(X86CPU *cpu)\n> MSR_F15H_PERF_CTL0 + AMD64_NUM_COUNTERS_CORE * 2 - 1:\n> index = index - MSR_F15H_PERF_CTL0;\n> if (index & 0x1) {\n> - env->msr_gp_counters[index] = msrs[i].data;\n> + env->msr_gp_counters[index >> 1] = msrs[i].data;\n> } else {\n> - env->msr_gp_evtsel[index] = msrs[i].data;\n> + env->msr_gp_evtsel[index >> 1] = msrs[i].data;\n> }\n> break;\n> case HV_X64_MSR_HYPERCALL:\n> --\n> 2.39.3","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=NLQjW23K;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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envelope-from=zide.chen@intel.com;\n helo=mgamail.intel.com","X-Spam_score_int":"-43","X-Spam_score":"-4.4","X-Spam_bar":"----","X-Spam_report":"(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3673770,"web_url":"http://patchwork.ozlabs.org/comment/3673770/","msgid":"<683add92-c9ba-4a21-b1f8-12e40a9a99d6@oracle.com>","list_archive_url":null,"date":"2026-04-06T15:17:43","subject":"Re: [PATCH 1/1] target/i386/kvm: Use logical counter index for AMD\n PMU getter","submitter":{"id":70292,"url":"http://patchwork.ozlabs.org/api/people/70292/","name":"Dongli Zhang","email":"dongli.zhang@oracle.com"},"content":"Ping?\n\nAny chance we can merge this bugfix? This change fixes AMD vPMU live migration\nfor the upcoming v11.0.0.\n\nThank you very much!\n\nDongli Zhang\n\nOn 3/26/26 9:44 AM, Chen, Zide wrote:\n> \n> \n[snip]\n>>\n>> Fixes: 4c7f05232c (\"target/i386/kvm: reset AMD PMU registers during VM\n>> reset\")\n>> Signed-off-by: Dongli Zhang \n>> ---\n> \n> Reviewed-by: Zide Chen ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oracle.com header.i=@oracle.com header.a=rsa-sha256\n header.s=corp-2025-04-25 header.b=fwoN4JUL;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=oracle.onmicrosoft.com header.i=@oracle.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector2-oracle-onmicrosoft-com\n header.b=RumDbkVL;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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