[{"id":3668780,"web_url":"http://patchwork.ozlabs.org/comment/3668780/","msgid":"","list_archive_url":null,"date":"2026-03-25T02:26:55","subject":"Re: [PATCH v2] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Wed, Mar 25, 2026 at 11:49 AM Jay Chang wrote:\n>\n> Replace the temporary custom extension bit (TC[32]) with the\n> standard EN_PRI bit defined in RISC-V IOMMU specification.\n>\n> Signed-off-by: Jay Chang \n> Reviewed-by: Frank Chang \n> Reviewed-by: Nutty Liu \n>\n> Change in V2:\n> Align code\n\nIn future don't include the changelog in the commit message please\n\n>\n> Signed-off-by: Jay Chang \n\nReviewed-by: Alistair Francis \n\nAlistair\n\n> ---\n> hw/riscv/riscv-iommu.c | 7 ++-----\n> 1 file changed, 2 insertions(+), 5 deletions(-)\n>\n> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c\n> index 225394ea83..30343e98d0 100644\n> --- a/hw/riscv/riscv-iommu.c\n> +++ b/hw/riscv/riscv-iommu.c\n> @@ -1572,11 +1572,8 @@ static int riscv_iommu_translate(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,\n> riscv_iommu_hpm_incr_ctr(s, ctx, RISCV_IOMMU_HPMEVENT_URQ);\n>\n> iot_cache = g_hash_table_ref(s->iot_cache);\n> - /*\n> - * TC[32] is reserved for custom extensions, used here to temporarily\n> - * enable automatic page-request generation for ATS queries.\n> - */\n> - enable_pri = (iotlb->perm == IOMMU_NONE) && (ctx->tc & BIT_ULL(32));\n> + enable_pri = (iotlb->perm == IOMMU_NONE) &&\n> + (ctx->tc & RISCV_IOMMU_DC_TC_EN_PRI);\n> enable_pid = (ctx->tc & RISCV_IOMMU_DC_TC_PDTV);\n>\n> /* Check for ATS request. */\n> --\n> 2.48.1\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=fmFhnqqP;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Tue, 24 Mar 2026\n 19:27:21 -0700 (PDT)","MIME-Version":"1.0","References":"<20260325014856.58948-1-jay.chang@sifive.com>","In-Reply-To":"<20260325014856.58948-1-jay.chang@sifive.com>","From":"Alistair Francis ","Date":"Wed, 25 Mar 2026 12:26:55 +1000","X-Gm-Features":"AQROBzBJVjzHr-Xu02PLozIIOWaQGcbIn4lyD2s0qwIJWzHQ5XfOruYnl6vHyS0","Message-ID":"\n ","Subject":"Re: [PATCH v2] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI","To":"Jay Chang ","Cc":"qemu-devel@nongnu.org, qemu-riscv@nongnu.org,\n Palmer Dabbelt ,\n Alistair Francis ,\n Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu , Frank Chang ,\n Nutty Liu ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Received-SPF":"pass client-ip=2a00:1450:4864:20::632;\n envelope-from=alistair23@gmail.com; helo=mail-ej1-x632.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3668783,"web_url":"http://patchwork.ozlabs.org/comment/3668783/","msgid":"","list_archive_url":null,"date":"2026-03-25T02:29:09","subject":"Re: [PATCH v2] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Wed, Mar 25, 2026 at 11:49 AM Jay Chang wrote:\n>\n> Replace the temporary custom extension bit (TC[32]) with the\n> standard EN_PRI bit defined in RISC-V IOMMU specification.\n>\n> Signed-off-by: Jay Chang \n> Reviewed-by: Frank Chang \n> Reviewed-by: Nutty Liu \n>\n> Change in V2:\n> Align code\n>\n> Signed-off-by: Jay Chang \n\nThanks!\n\nApplied to riscv-to-apply.next\n\nAlistair\n\n> ---\n> hw/riscv/riscv-iommu.c | 7 ++-----\n> 1 file changed, 2 insertions(+), 5 deletions(-)\n>\n> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c\n> index 225394ea83..30343e98d0 100644\n> --- a/hw/riscv/riscv-iommu.c\n> +++ b/hw/riscv/riscv-iommu.c\n> @@ -1572,11 +1572,8 @@ static int riscv_iommu_translate(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,\n> riscv_iommu_hpm_incr_ctr(s, ctx, RISCV_IOMMU_HPMEVENT_URQ);\n>\n> iot_cache = g_hash_table_ref(s->iot_cache);\n> - /*\n> - * TC[32] is reserved for custom extensions, used here to temporarily\n> - * enable automatic page-request generation for ATS queries.\n> - */\n> - enable_pri = (iotlb->perm == IOMMU_NONE) && (ctx->tc & BIT_ULL(32));\n> + enable_pri = (iotlb->perm == IOMMU_NONE) &&\n> + (ctx->tc & RISCV_IOMMU_DC_TC_EN_PRI);\n> enable_pid = (ctx->tc & RISCV_IOMMU_DC_TC_PDTV);\n>\n> /* Check for ATS request. */\n> --\n> 2.48.1\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=Vb1EB8mw;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Tue, 24 Mar 2026\n 19:29:36 -0700 (PDT)","MIME-Version":"1.0","References":"<20260325014856.58948-1-jay.chang@sifive.com>","In-Reply-To":"<20260325014856.58948-1-jay.chang@sifive.com>","From":"Alistair Francis ","Date":"Wed, 25 Mar 2026 12:29:09 +1000","X-Gm-Features":"AQROBzA4eoAsiMTUTsZ4wRlCZiQzzoj2WEyBIjRriOqpWuwWp45uuU35I8O0WRo","Message-ID":"\n ","Subject":"Re: [PATCH v2] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI","To":"Jay Chang ","Cc":"qemu-devel@nongnu.org, qemu-riscv@nongnu.org,\n Palmer Dabbelt ,\n Alistair Francis ,\n Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu , Frank Chang ,\n Nutty Liu ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Received-SPF":"pass client-ip=2a00:1450:4864:20::62d;\n envelope-from=alistair23@gmail.com; helo=mail-ej1-x62d.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}}]