[{"id":3669368,"web_url":"http://patchwork.ozlabs.org/comment/3669368/","msgid":"","list_archive_url":null,"date":"2026-03-25T22:24:33","subject":"Re: [PATCH v2 1/1] x86_64: Prefer EVEX512 code-path on AMD Zen5 CPUs","submitter":{"id":4387,"url":"http://patchwork.ozlabs.org/api/people/4387/","name":"H.J. Lu","email":"hjl.tools@gmail.com"},"content":"On Tue, Mar 24, 2026 at 12:21 PM Sajan Karumanchi\n wrote:\n>\n> Introduced a synthetic architecture preference flag (Prefer_EVEX512)\n> and enabled it for AMD Zen5 (CPUID Family 0x1A) when AVX-512 is supported.\n>\n> This flag modifies IFUNC dispatch to prefer 512-bit EVEX variants over\n> 256-bit EVEX variants for string and memory functions on Zen5 processors,\n> leveraging their native 512-bit execution units for improved throughput.\n> When Prefer_EVEX512 is set, the dispatcher selects evex512 implementations;\n> otherwise, it falls back to evex (256-bit) variants.\n>\n> The implementation updates the IFUNC selection logic in ifunc-avx2.h and\n> ifunc-evex.h to check for the Prefer_EVEX512 flag before dispatching to\n> EVEX512 implementations. This change affects six string/memory functions:\n>\n> - strchr\n> - strlen\n> - strnlen\n> - strrchr\n> - strchrnul\n> - memchr\n>\n> Benchmarks conducted on AMD Zen5 hardware demonstrate significant\n> performance improvements across all affected functions:\n>\n> Function Baseline Patched Avg Avg Avg Max\n> Variant Variant Baseline Patched Change Improve\n> (ns) (ns) % %\n> ------------+----------+----------+-----------+----------+--------+--------\n> STRCHR evex evex512 16.408 12.293 25.08% 37.69%\n> STRLEN evex evex512 16.862 11.436 32.18% 56.74%\n> STRNLEN evex evex512 18.493 11.762 36.40% 64.40%\n> STRRCHR evex evex512 15.154 10.874 28.24% 44.38%\n> STRCHRNUL evex evex512 16.464 12.605 23.44% 45.56%\n> MEMCHR evex evex512 9.984 8.268 17.19% 39.99%\n>\n> Additionally, a tunable option (glibc.cpu.x86_cpu_features.preferred)\n> is provided to allow runtime control of the Prefer_EVEX512 flag for testing\n> and compatibility.\n>\n> Reviewed-by: Ganesh Gopalasubramanian \n> ---\n> sysdeps/x86/cpu-features.c | 8 ++++++++\n> sysdeps/x86/cpu-tunables.c | 6 ++++++\n> .../cpu-features-preferred_feature_index_1.def | 1 +\n> sysdeps/x86_64/multiarch/ifunc-avx2.h | 15 ++++++++++++---\n> sysdeps/x86_64/multiarch/ifunc-evex.h | 11 ++++++++++-\n> sysdeps/x86_64/multiarch/memchr.c | 1 +\n> sysdeps/x86_64/multiarch/strchr.c | 8 +++++++-\n> sysdeps/x86_64/multiarch/strchrnul.c | 1 +\n> sysdeps/x86_64/multiarch/strlen.c | 1 +\n> sysdeps/x86_64/multiarch/strnlen.c | 1 +\n> sysdeps/x86_64/multiarch/strrchr.c | 1 +\n> 11 files changed, 49 insertions(+), 5 deletions(-)\n>\n> diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c\n> index ccfef55652..0112a0dcc5 100644\n> --- a/sysdeps/x86/cpu-features.c\n> +++ b/sysdeps/x86/cpu-features.c\n> @@ -1009,6 +1009,14 @@ disable_tsx:\n> cpu_features->preferred[index_arch_Avoid_Non_Temporal_Memset]\n> &= ~bit_arch_Avoid_Non_Temporal_Memset;\n>\n> + /* Prefer EVEX512 string/memory variants on AMD Zen5 (Family 0x1A)\n> + when AVX-512 is usable. */\n> + if (family == 0x1A && CPU_FEATURE_USABLE_P (cpu_features, AVX512F))\n> + {\n\nDrop {}.\n\n> + cpu_features->preferred[index_arch_Prefer_EVEX512]\n> + |= bit_arch_Prefer_EVEX512;\n> + }\n> +\n> if (CPU_FEATURE_USABLE_P (cpu_features, AVX))\n> {\n> /* Since the FMA4 bit is in CPUID_INDEX_80000001 and\n> diff --git a/sysdeps/x86/cpu-tunables.c b/sysdeps/x86/cpu-tunables.c\n> index 51769a5493..59dde5f1d7 100644\n> --- a/sysdeps/x86/cpu-tunables.c\n> +++ b/sysdeps/x86/cpu-tunables.c\n> @@ -203,6 +203,12 @@ TUNABLE_CALLBACK (set_hwcaps) (tunable_val_t *valp)\n> 11);\n> }\n> break;\n> + case 14:\n> + {\n> + CHECK_GLIBC_IFUNC_PREFERRED_NEED_BOTH\n> + (n, cpu_features, Prefer_EVEX512, AVX512F, 14);\n> + }\n> + break;\n> case 15:\n> {\n> CHECK_GLIBC_IFUNC_PREFERRED_BOTH (n, cpu_features,\n> diff --git a/sysdeps/x86/include/cpu-features-preferred_feature_index_1.def b/sysdeps/x86/include/cpu-features-preferred_feature_index_1.def\n> index 8cab2ae248..74acb3fde1 100644\n> --- a/sysdeps/x86/include/cpu-features-preferred_feature_index_1.def\n> +++ b/sysdeps/x86/include/cpu-features-preferred_feature_index_1.def\n> @@ -35,3 +35,4 @@ BIT (Prefer_FSRM)\n> BIT (Avoid_Short_Distance_REP_MOVSB)\n> BIT (Avoid_Non_Temporal_Memset)\n> BIT (Avoid_STOSB)\n> +BIT (Prefer_EVEX512)\n> diff --git a/sysdeps/x86_64/multiarch/ifunc-avx2.h b/sysdeps/x86_64/multiarch/ifunc-avx2.h\n> index bc7178d97e..474466ba93 100644\n> --- a/sysdeps/x86_64/multiarch/ifunc-avx2.h\n> +++ b/sysdeps/x86_64/multiarch/ifunc-avx2.h\n> @@ -1,4 +1,4 @@\n> -/* Common definition for ifunc selections optimized with SSE2 and AVX2.\n> +/* Common definition for ifunc selections optimized with SSE2, AVX2 and EVEX512.\n> All versions must be listed in ifunc-impl-list.c.\n> Copyright (C) 2017-2026 Free Software Foundation, Inc.\n> This file is part of the GNU C Library.\n> @@ -25,6 +25,10 @@\n>\n> extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;\n>\n> +#ifdef USE_EVEX512\n> +extern __typeof (REDIRECT_NAME) OPTIMIZE (evex512) attribute_hidden;\n> +#endif\n> +\n> extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;\n> extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;\n>\n> @@ -44,8 +48,13 @@ IFUNC_SELECTOR (void)\n> {\n> if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)\n> && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))\n> - return OPTIMIZE (evex);\n> -\n> + {\n> +#ifdef USE_EVEX512\n> + if (CPU_FEATURES_ARCH_P (cpu_features, Prefer_EVEX512))\n> + return OPTIMIZE (evex512);\n> +#endif\n> + return OPTIMIZE (evex);\n> + }\n> if (CPU_FEATURE_USABLE_P (cpu_features, RTM))\n> return OPTIMIZE (avx2_rtm);\n>\n> diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h\n> index 973a5b3d15..02ca749a72 100644\n> --- a/sysdeps/x86_64/multiarch/ifunc-evex.h\n> +++ b/sysdeps/x86_64/multiarch/ifunc-evex.h\n> @@ -1,4 +1,4 @@\n> -/* Common definition for ifunc selection optimized with EVEX.\n> +/* Common definition for ifunc selection optimized with EVEX and EVEX512.\n> All versions must be listed in ifunc-impl-list.c.\n> Copyright (C) 2017-2026 Free Software Foundation, Inc.\n> This file is part of the GNU C Library.\n> @@ -22,6 +22,10 @@\n> extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;\n> extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden;\n>\n> +#ifdef USE_EVEX512\n> +extern __typeof (REDIRECT_NAME) OPTIMIZE (evex512) attribute_hidden;\n> +#endif\n> +\n> extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;\n> extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;\n>\n> @@ -42,6 +46,11 @@ IFUNC_SELECTOR (void)\n> if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)\n> && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))\n> {\n> +#ifdef USE_EVEX512\n> + if (CPU_FEATURES_ARCH_P (cpu_features, Prefer_EVEX512))\n> + return OPTIMIZE (evex512);\n> +#endif\n> +\n> if (CPU_FEATURE_USABLE_P (cpu_features, RTM))\n> return OPTIMIZE (evex_rtm);\n>\n> diff --git a/sysdeps/x86_64/multiarch/memchr.c b/sysdeps/x86_64/multiarch/memchr.c\n> index cea0518787..b2a6c666a9 100644\n> --- a/sysdeps/x86_64/multiarch/memchr.c\n> +++ b/sysdeps/x86_64/multiarch/memchr.c\n> @@ -24,6 +24,7 @@\n> # undef memchr\n>\n> # define SYMBOL_NAME memchr\n> +# define USE_EVEX512 1\n> # include \"ifunc-evex.h\"\n>\n> libc_ifunc_redirected (__redirect_memchr, memchr, IFUNC_SELECTOR ());\n> diff --git a/sysdeps/x86_64/multiarch/strchr.c b/sysdeps/x86_64/multiarch/strchr.c\n> index 1064bc8e5b..f6bd36ba73 100644\n> --- a/sysdeps/x86_64/multiarch/strchr.c\n> +++ b/sysdeps/x86_64/multiarch/strchr.c\n> @@ -27,6 +27,7 @@\n> # include \n>\n> extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;\n> +extern __typeof (REDIRECT_NAME) OPTIMIZE (evex512) attribute_hidden;\n>\n> extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;\n> extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;\n> @@ -46,7 +47,12 @@ IFUNC_SELECTOR (void)\n> {\n> if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)\n> && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))\n> - return OPTIMIZE (evex);\n> + {\n> + if (CPU_FEATURES_ARCH_P (cpu_features, Prefer_EVEX512))\n> + return OPTIMIZE (evex512);\n> +\n> + return OPTIMIZE (evex);\n> + }\n>\n> if (CPU_FEATURE_USABLE_P (cpu_features, RTM))\n> return OPTIMIZE (avx2_rtm);\n> diff --git a/sysdeps/x86_64/multiarch/strchrnul.c b/sysdeps/x86_64/multiarch/strchrnul.c\n> index f4bfc28c7b..3bb93bb812 100644\n> --- a/sysdeps/x86_64/multiarch/strchrnul.c\n> +++ b/sysdeps/x86_64/multiarch/strchrnul.c\n> @@ -26,6 +26,7 @@\n> # undef strchrnul\n>\n> # define SYMBOL_NAME strchrnul\n> +# define USE_EVEX512 1\n> # include \"ifunc-avx2.h\"\n>\n> libc_ifunc_redirected (__redirect_strchrnul, __strchrnul,\n> diff --git a/sysdeps/x86_64/multiarch/strlen.c b/sysdeps/x86_64/multiarch/strlen.c\n> index 95aa48e5d3..2f93abf1c8 100644\n> --- a/sysdeps/x86_64/multiarch/strlen.c\n> +++ b/sysdeps/x86_64/multiarch/strlen.c\n> @@ -24,6 +24,7 @@\n> # undef strlen\n>\n> # define SYMBOL_NAME strlen\n> +# define USE_EVEX512 1\n> # include \"ifunc-avx2.h\"\n>\n> libc_ifunc_redirected (__redirect_strlen, strlen, IFUNC_SELECTOR ());\n> diff --git a/sysdeps/x86_64/multiarch/strnlen.c b/sysdeps/x86_64/multiarch/strnlen.c\n> index bfe4d7abf0..62e50a27e4 100644\n> --- a/sysdeps/x86_64/multiarch/strnlen.c\n> +++ b/sysdeps/x86_64/multiarch/strnlen.c\n> @@ -26,6 +26,7 @@\n> # undef strnlen\n>\n> # define SYMBOL_NAME strnlen\n> +# define USE_EVEX512 1\n> # include \"ifunc-avx2.h\"\n>\n> libc_ifunc_redirected (__redirect_strnlen, __strnlen, IFUNC_SELECTOR ());\n> diff --git a/sysdeps/x86_64/multiarch/strrchr.c b/sysdeps/x86_64/multiarch/strrchr.c\n> index 66d3f5b1d1..0965938561 100644\n> --- a/sysdeps/x86_64/multiarch/strrchr.c\n> +++ b/sysdeps/x86_64/multiarch/strrchr.c\n> @@ -23,6 +23,7 @@\n> # undef strrchr\n>\n> # define SYMBOL_NAME strrchr\n> +# define USE_EVEX512 1\n> # include \"ifunc-avx2.h\"\n>\n> libc_ifunc_redirected (__redirect_strrchr, strrchr, IFUNC_SELECTOR ());\n> --\n> 2.34.1","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","libc-alpha@sourceware.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","libc-alpha@sourceware.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=eV31DzAy;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org\n (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org;\n envelope-from=libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org;\n receiver=patchwork.ozlabs.org)","sourceware.org;\n\tdkim=pass (2048-bit key,\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=eV31DzAy","sourceware.org;\n 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Lu\" ","Date":"Wed, 25 Mar 2026 15:24:33 -0700","X-Gm-Features":"AaiRm53Jr29ThqTboQWAuvBYYwF8WG4APNThSAo-tAsdcTAAP9_QRv_lFeIg82Y","Message-ID":"\n ","Subject":"Re: [PATCH v2 1/1] x86_64: Prefer EVEX512 code-path on AMD Zen5 CPUs","To":"Sajan Karumanchi ","Cc":"libc-alpha@sourceware.org, sajan.karumanchi@amd.com, fweimer@redhat.com,\n goldstein.w.n@gmail.com,\n Ganesh Gopalasubramanian ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","X-BeenThere":"libc-alpha@sourceware.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Libc-alpha mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org"}}]