[{"id":3675012,"web_url":"http://patchwork.ozlabs.org/comment/3675012/","msgid":"<20260408222409.GA329776@bhelgaas>","list_archive_url":null,"date":"2026-04-08T22:24:09","subject":"Re: [PATCH v8 12/14] PCI: dwc: Apply ECRC workaround to DesignWare\n 5.00a as well","submitter":{"id":67298,"url":"http://patchwork.ozlabs.org/api/people/67298/","name":"Bjorn Helgaas","email":"helgaas@kernel.org"},"content":"On Wed, Mar 25, 2026 at 12:37:53AM +0530, Manikanta Maddireddy wrote:\n> The ECRC (TLP digest) workaround was originally added for DesignWare\n> version 4.90a. Tegra234 SoC has 5.00a DWC HW version, which has\n> the same ATU TD override behaviour, so apply the workaround for 5.00a\n> too.\n> \n> Fixes: a54e19073718 (\"PCI: tegra194: Add Tegra234 PCIe support\")\n> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>\n> Tested-by: Jon Hunter <jonathanh@nvidia.com>\n> Reviewed-by: Vidya Sagar <vidyas@nvidia.com>\n> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n> ---\n> Changes V8: Split into two patches\n> Changes V1 -> V7: None\n> \n>  drivers/pci/controller/dwc/pcie-designware.c | 4 ++--\n>  1 file changed, 2 insertions(+), 2 deletions(-)\n> \n> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c\n> index 345365ea97c7..c4dc2d88649e 100644\n> --- a/drivers/pci/controller/dwc/pcie-designware.c\n> +++ b/drivers/pci/controller/dwc/pcie-designware.c\n> @@ -486,7 +486,7 @@ static inline void dw_pcie_writel_atu_ob(struct dw_pcie *pci, u32 index, u32 reg\n>  static inline u32 dw_pcie_enable_ecrc(u32 val)\n>  {\n>  \t/*\n> -\t * DesignWare core version 4.90A has a design issue where the 'TD'\n> +\t * DWC versions 0x3530302a and 0x3536322a has a design issue where the 'TD'\n\n0x3536322a looks like DW_PCIE_VER_562A, not DW_PCIE_VER_500A, so this\ncomment doesn't seem to match the commit log or the code.\n\n\"0x3530302a and 0x3536322a\" is not nearly as readable as 4.90A and\n5.00A.\n\n>  \t * bit in the Control register-1 of the ATU outbound region acts\n>  \t * like an override for the ECRC setting, i.e., the presence of TLP\n>  \t * Digest (ECRC) in the outgoing TLPs is solely determined by this\n> @@ -559,7 +559,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,\n>  \tif (upper_32_bits(limit_addr) > upper_32_bits(parent_bus_addr) &&\n>  \t    dw_pcie_ver_is_ge(pci, 460A))\n>  \t\tval |= PCIE_ATU_INCREASE_REGION_SIZE;\n> -\tif (dw_pcie_ver_is(pci, 490A))\n> +\tif (dw_pcie_ver_is(pci, 490A) || dw_pcie_ver_is(pci, 500A))\n>  \t\tval = dw_pcie_enable_ecrc(val);\n\nThis is in shared DWC code, which raises the question of whether this\nissue applies *only* to 490A and 500A?  What about other versions,\ne.g., 520A (unused AFAICS), 540A, 562A?\n\n>  \tdw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);\n>  \n> -- \n> 2.34.1\n>","headers":{"Return-Path":"\n <linux-pci+bounces-52177-incoming=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=KyNU+h2i;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-52177-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"KyNU+h2i\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frd021d6Bz1yD3\n\tfor <incoming@patchwork.ozlabs.org>; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20260324190755.1094879-13-mmaddireddy@nvidia.com>"}},{"id":3675189,"web_url":"http://patchwork.ozlabs.org/comment/3675189/","msgid":"<25417b97-ff10-4e5d-aa8f-2c832cb81250@nvidia.com>","list_archive_url":null,"date":"2026-04-09T08:51:57","subject":"Re: [PATCH v8 12/14] PCI: dwc: Apply ECRC workaround to DesignWare\n 5.00a as well","submitter":{"id":72399,"url":"http://patchwork.ozlabs.org/api/people/72399/","name":"Manikanta Maddireddy","email":"mmaddireddy@nvidia.com"},"content":"On 09/04/26 3:54 am, Bjorn Helgaas wrote:\n> On Wed, Mar 25, 2026 at 12:37:53AM +0530, Manikanta Maddireddy wrote:\n>> The ECRC (TLP digest) workaround was originally added for DesignWare\n>> version 4.90a. Tegra234 SoC has 5.00a DWC HW version, which has\n>> the same ATU TD override behaviour, so apply the workaround for 5.00a\n>> too.\n>>\n>> Fixes: a54e19073718 (\"PCI: tegra194: Add Tegra234 PCIe support\")\n>> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>\n>> Tested-by: Jon Hunter <jonathanh@nvidia.com>\n>> Reviewed-by: Vidya Sagar <vidyas@nvidia.com>\n>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n>> ---\n>> Changes V8: Split into two patches\n>> Changes V1 -> V7: None\n>>\n>>   drivers/pci/controller/dwc/pcie-designware.c | 4 ++--\n>>   1 file changed, 2 insertions(+), 2 deletions(-)\n>>\n>> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c\n>> index 345365ea97c7..c4dc2d88649e 100644\n>> --- a/drivers/pci/controller/dwc/pcie-designware.c\n>> +++ b/drivers/pci/controller/dwc/pcie-designware.c\n>> @@ -486,7 +486,7 @@ static inline void dw_pcie_writel_atu_ob(struct dw_pcie *pci, u32 index, u32 reg\n>>   static inline u32 dw_pcie_enable_ecrc(u32 val)\n>>   {\n>>   \t/*\n>> -\t * DesignWare core version 4.90A has a design issue where the 'TD'\n>> +\t * DWC versions 0x3530302a and 0x3536322a has a design issue where the 'TD'\n> \n> 0x3536322a looks like DW_PCIE_VER_562A, not DW_PCIE_VER_500A, so this\n> comment doesn't seem to match the commit log or the code.\n> \n> \"0x3530302a and 0x3536322a\" is not nearly as readable as 4.90A and\n> 5.00A.\n> \n>>   \t * bit in the Control register-1 of the ATU outbound region acts\n>>   \t * like an override for the ECRC setting, i.e., the presence of TLP\n>>   \t * Digest (ECRC) in the outgoing TLPs is solely determined by this\n>> @@ -559,7 +559,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,\n>>   \tif (upper_32_bits(limit_addr) > upper_32_bits(parent_bus_addr) &&\n>>   \t    dw_pcie_ver_is_ge(pci, 460A))\n>>   \t\tval |= PCIE_ATU_INCREASE_REGION_SIZE;\n>> -\tif (dw_pcie_ver_is(pci, 490A))\n>> +\tif (dw_pcie_ver_is(pci, 490A) || dw_pcie_ver_is(pci, 500A))\n>>   \t\tval = dw_pcie_enable_ecrc(val);\n> \n> This is in shared DWC code, which raises the question of whether this\n> issue applies *only* to 490A and 500A?  What about other versions,\n> e.g., 520A (unused AFAICS), 540A, 562A?\n> \n\nHi Bjorn,\n\nI reviewed our internal bug database, I found that this dependency of \niATU TD bit on ECRC is removed from version 5.10A. A comment from \nSynopsys case is quoted in our internal bug. Shall I prepare patch to \naddress this for all versions < 5.10A? Or do we need inputs from Synopsys?\n\nProposed patch\n\n--- a/drivers/pci/controller/dwc/pcie-designware.c\n+++ b/drivers/pci/controller/dwc/pcie-designware.c\n@@ -486,7 +486,7 @@ static inline void dw_pcie_writel_atu_ob(struct \ndw_pcie *pci, u32 index, u32 reg\n  static inline u32 dw_pcie_enable_ecrc(u32 val)\n  {\n         /*\n-        * DWC versions 0x3530302a and 0x3536322a has a design issue \nwhere the 'TD'\n+        * DWC versions less than 5.10A has a design issue where the 'TD'\n          * bit in the Control register-1 of the ATU outbound region acts\n          * like an override for the ECRC setting, i.e., the presence of TLP\n          * Digest (ECRC) in the outgoing TLPs is solely determined by this\n@@ -559,7 +559,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,\n         if (upper_32_bits(limit_addr) > upper_32_bits(parent_bus_addr) &&\n             dw_pcie_ver_is_ge(pci, 460A))\n                 val |= PCIE_ATU_INCREASE_REGION_SIZE;\n-       if (dw_pcie_ver_is(pci, 490A) || dw_pcie_ver_is(pci, 500A))\n+       if (!dw_pcie_ver_is_ge(pci, 510A))\n                 val = dw_pcie_enable_ecrc(val);\n         dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);\n\ndiff --git a/drivers/pci/controller/dwc/pcie-designware.h \nb/drivers/pci/controller/dwc/pcie-designware.h\nindex 5bceadbd2c9f..00891adfd07d 100644\n--- a/drivers/pci/controller/dwc/pcie-designware.h\n+++ b/drivers/pci/controller/dwc/pcie-designware.h\n@@ -35,6 +35,7 @@\n  #define DW_PCIE_VER_480A               0x3438302a\n  #define DW_PCIE_VER_490A               0x3439302a\n  #define DW_PCIE_VER_500A               0x3530302a\n+#define DW_PCIE_VER_510A               0x3531302a\n  #define DW_PCIE_VER_520A               0x3532302a\n  #define DW_PCIE_VER_540A               0x3534302a\n  #define DW_PCIE_VER_562A               0x3536322a\n\nThanks,\nManikanta\n\n>>   \tdw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);\n>>   \n>> -- \n>> 2.34.1\n>>","headers":{"Return-Path":"\n <linux-pci+bounces-52209-incoming=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=jMQRCrer;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-52209-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=\"jMQRCrer\"","smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=52.101.46.0","smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) 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Thunderbird","Subject":"Re: [PATCH v8 12/14] PCI: dwc: Apply ECRC workaround to DesignWare\n 5.00a as well","To":"Bjorn Helgaas <helgaas@kernel.org>","Cc":"bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org,\n mani@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,\n thierry.reding@gmail.com, jonathanh@nvidia.com, kishon@kernel.org,\n arnd@arndb.de, gregkh@linuxfoundation.org, Frank.Li@nxp.com,\n den@valinux.co.jp, hongxing.zhu@nxp.com, jingoohan1@gmail.com,\n vidyas@nvidia.com, cassel@kernel.org, 18255117159@163.com,\n linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org,\n linux-kernel@vger.kernel.org","References":"<20260408222409.GA329776@bhelgaas>","Content-Language":"en-US","X-Nvconfidentiality":"public","From":"Manikanta Maddireddy <mmaddireddy@nvidia.com>","In-Reply-To":"<20260408222409.GA329776@bhelgaas>","Content-Type":"text/plain; charset=UTF-8; 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Helgaas","email":"helgaas@kernel.org"},"content":"On Thu, Apr 09, 2026 at 02:21:57PM +0530, Manikanta Maddireddy wrote:\n> On 09/04/26 3:54 am, Bjorn Helgaas wrote:\n> > On Wed, Mar 25, 2026 at 12:37:53AM +0530, Manikanta Maddireddy wrote:\n> > > The ECRC (TLP digest) workaround was originally added for DesignWare\n> > > version 4.90a. Tegra234 SoC has 5.00a DWC HW version, which has\n> > > the same ATU TD override behaviour, so apply the workaround for 5.00a\n> > > too.\n> > > \n> > > Fixes: a54e19073718 (\"PCI: tegra194: Add Tegra234 PCIe support\")\n> > > Reviewed-by: Jon Hunter <jonathanh@nvidia.com>\n> > > Tested-by: Jon Hunter <jonathanh@nvidia.com>\n> > > Reviewed-by: Vidya Sagar <vidyas@nvidia.com>\n> > > Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n> > > ---\n> > > Changes V8: Split into two patches\n> > > Changes V1 -> V7: None\n> > > \n> > >   drivers/pci/controller/dwc/pcie-designware.c | 4 ++--\n> > >   1 file changed, 2 insertions(+), 2 deletions(-)\n> > > \n> > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c\n> > > index 345365ea97c7..c4dc2d88649e 100644\n> > > --- a/drivers/pci/controller/dwc/pcie-designware.c\n> > > +++ b/drivers/pci/controller/dwc/pcie-designware.c\n> > > @@ -486,7 +486,7 @@ static inline void dw_pcie_writel_atu_ob(struct dw_pcie *pci, u32 index, u32 reg\n> > >   static inline u32 dw_pcie_enable_ecrc(u32 val)\n> > >   {\n> > >   \t/*\n> > > -\t * DesignWare core version 4.90A has a design issue where the 'TD'\n> > > +\t * DWC versions 0x3530302a and 0x3536322a has a design issue where the 'TD'\n> > \n> > 0x3536322a looks like DW_PCIE_VER_562A, not DW_PCIE_VER_500A, so this\n> > comment doesn't seem to match the commit log or the code.\n> > \n> > \"0x3530302a and 0x3536322a\" is not nearly as readable as 4.90A and\n> > 5.00A.\n> > \n> > >   \t * bit in the Control register-1 of the ATU outbound region acts\n> > >   \t * like an override for the ECRC setting, i.e., the presence of TLP\n> > >   \t * Digest (ECRC) in the outgoing TLPs is solely determined by this\n> > > @@ -559,7 +559,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,\n> > >   \tif (upper_32_bits(limit_addr) > upper_32_bits(parent_bus_addr) &&\n> > >   \t    dw_pcie_ver_is_ge(pci, 460A))\n> > >   \t\tval |= PCIE_ATU_INCREASE_REGION_SIZE;\n> > > -\tif (dw_pcie_ver_is(pci, 490A))\n> > > +\tif (dw_pcie_ver_is(pci, 490A) || dw_pcie_ver_is(pci, 500A))\n> > >   \t\tval = dw_pcie_enable_ecrc(val);\n> > \n> > This is in shared DWC code, which raises the question of whether this\n> > issue applies *only* to 490A and 500A?  What about other versions,\n> > e.g., 520A (unused AFAICS), 540A, 562A?\n> > \n> \n> Hi Bjorn,\n> \n> I reviewed our internal bug database, I found that this dependency of iATU\n> TD bit on ECRC is removed from version 5.10A. A comment from Synopsys case\n> is quoted in our internal bug. Shall I prepare patch to address this for all\n> versions < 5.10A? Or do we need inputs from Synopsys?\n\nThe patch below looks good to me, assuming the commit log is updated\nto match this comment and the code.\n\nI don't have any visibility into the Synopsys IP versions.\n\n> Proposed patch\n> \n> --- a/drivers/pci/controller/dwc/pcie-designware.c\n> +++ b/drivers/pci/controller/dwc/pcie-designware.c\n> @@ -486,7 +486,7 @@ static inline void dw_pcie_writel_atu_ob(struct dw_pcie\n> *pci, u32 index, u32 reg\n>  static inline u32 dw_pcie_enable_ecrc(u32 val)\n>  {\n>         /*\n> -        * DWC versions 0x3530302a and 0x3536322a has a design issue where\n> the 'TD'\n> +        * DWC versions less than 5.10A has a design issue where the 'TD'\n>          * bit in the Control register-1 of the ATU outbound region acts\n>          * like an override for the ECRC setting, i.e., the presence of TLP\n>          * Digest (ECRC) in the outgoing TLPs is solely determined by this\n> @@ -559,7 +559,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,\n>         if (upper_32_bits(limit_addr) > upper_32_bits(parent_bus_addr) &&\n>             dw_pcie_ver_is_ge(pci, 460A))\n>                 val |= PCIE_ATU_INCREASE_REGION_SIZE;\n> -       if (dw_pcie_ver_is(pci, 490A) || dw_pcie_ver_is(pci, 500A))\n> +       if (!dw_pcie_ver_is_ge(pci, 510A))\n>                 val = dw_pcie_enable_ecrc(val);\n>         dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);\n> \n> diff --git a/drivers/pci/controller/dwc/pcie-designware.h\n> b/drivers/pci/controller/dwc/pcie-designware.h\n> index 5bceadbd2c9f..00891adfd07d 100644\n> --- a/drivers/pci/controller/dwc/pcie-designware.h\n> +++ b/drivers/pci/controller/dwc/pcie-designware.h\n> @@ -35,6 +35,7 @@\n>  #define DW_PCIE_VER_480A               0x3438302a\n>  #define DW_PCIE_VER_490A               0x3439302a\n>  #define DW_PCIE_VER_500A               0x3530302a\n> +#define DW_PCIE_VER_510A               0x3531302a\n>  #define DW_PCIE_VER_520A               0x3532302a\n>  #define DW_PCIE_VER_540A               0x3534302a\n>  #define DW_PCIE_VER_562A               0x3536322a\n> \n> Thanks,\n> Manikanta\n> \n> > >   \tdw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);\n> > > -- \n> > > 2.34.1\n> > > \n> \n> -- \n> nvpublic\n>","headers":{"Return-Path":"\n <linux-pci+bounces-52226-incoming=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=Yl6uJouq;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<25417b97-ff10-4e5d-aa8f-2c832cb81250@nvidia.com>"}},{"id":3675679,"web_url":"http://patchwork.ozlabs.org/comment/3675679/","msgid":"<3110bba0-ddfa-4adc-a73a-bb85b78febc0@nvidia.com>","list_archive_url":null,"date":"2026-04-10T06:32:51","subject":"Re: [PATCH v8 12/14] PCI: dwc: Apply ECRC workaround to DesignWare\n 5.00a as well","submitter":{"id":72399,"url":"http://patchwork.ozlabs.org/api/people/72399/","name":"Manikanta Maddireddy","email":"mmaddireddy@nvidia.com"},"content":"On 10/04/26 12:15 am, Bjorn Helgaas wrote:\n> On Thu, Apr 09, 2026 at 02:21:57PM +0530, Manikanta Maddireddy wrote:\n>> On 09/04/26 3:54 am, Bjorn Helgaas wrote:\n>>> On Wed, Mar 25, 2026 at 12:37:53AM +0530, Manikanta Maddireddy wrote:\n>>>> The ECRC (TLP digest) workaround was originally added for DesignWare\n>>>> version 4.90a. Tegra234 SoC has 5.00a DWC HW version, which has\n>>>> the same ATU TD override behaviour, so apply the workaround for 5.00a\n>>>> too.\n>>>>\n>>>> Fixes: a54e19073718 (\"PCI: tegra194: Add Tegra234 PCIe support\")\n>>>> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>\n>>>> Tested-by: Jon Hunter <jonathanh@nvidia.com>\n>>>> Reviewed-by: Vidya Sagar <vidyas@nvidia.com>\n>>>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n>>>> ---\n>>>> Changes V8: Split into two patches\n>>>> Changes V1 -> V7: None\n>>>>\n>>>>    drivers/pci/controller/dwc/pcie-designware.c | 4 ++--\n>>>>    1 file changed, 2 insertions(+), 2 deletions(-)\n>>>>\n>>>> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c\n>>>> index 345365ea97c7..c4dc2d88649e 100644\n>>>> --- a/drivers/pci/controller/dwc/pcie-designware.c\n>>>> +++ b/drivers/pci/controller/dwc/pcie-designware.c\n>>>> @@ -486,7 +486,7 @@ static inline void dw_pcie_writel_atu_ob(struct dw_pcie *pci, u32 index, u32 reg\n>>>>    static inline u32 dw_pcie_enable_ecrc(u32 val)\n>>>>    {\n>>>>    \t/*\n>>>> -\t * DesignWare core version 4.90A has a design issue where the 'TD'\n>>>> +\t * DWC versions 0x3530302a and 0x3536322a has a design issue where the 'TD'\n>>>\n>>> 0x3536322a looks like DW_PCIE_VER_562A, not DW_PCIE_VER_500A, so this\n>>> comment doesn't seem to match the commit log or the code.\n>>>\n>>> \"0x3530302a and 0x3536322a\" is not nearly as readable as 4.90A and\n>>> 5.00A.\n>>>\n>>>>    \t * bit in the Control register-1 of the ATU outbound region acts\n>>>>    \t * like an override for the ECRC setting, i.e., the presence of TLP\n>>>>    \t * Digest (ECRC) in the outgoing TLPs is solely determined by this\n>>>> @@ -559,7 +559,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,\n>>>>    \tif (upper_32_bits(limit_addr) > upper_32_bits(parent_bus_addr) &&\n>>>>    \t    dw_pcie_ver_is_ge(pci, 460A))\n>>>>    \t\tval |= PCIE_ATU_INCREASE_REGION_SIZE;\n>>>> -\tif (dw_pcie_ver_is(pci, 490A))\n>>>> +\tif (dw_pcie_ver_is(pci, 490A) || dw_pcie_ver_is(pci, 500A))\n>>>>    \t\tval = dw_pcie_enable_ecrc(val);\n>>>\n>>> This is in shared DWC code, which raises the question of whether this\n>>> issue applies *only* to 490A and 500A?  What about other versions,\n>>> e.g., 520A (unused AFAICS), 540A, 562A?\n>>>\n>>\n>> Hi Bjorn,\n>>\n>> I reviewed our internal bug database, I found that this dependency of iATU\n>> TD bit on ECRC is removed from version 5.10A. A comment from Synopsys case\n>> is quoted in our internal bug. Shall I prepare patch to address this for all\n>> versions < 5.10A? Or do we need inputs from Synopsys?\n> \n> The patch below looks good to me, assuming the commit log is updated\n> to match this comment and the code.\n> \n> I don't have any visibility into the Synopsys IP versions.\n\nHi Bjorn,\n\nI published new patch with proposed fix.\nhttps://patchwork.kernel.org/project/linux-pci/patch/20260410062507.657453-1-mmaddireddy@nvidia.com/\n\nThanks,\nManikanta\n\n> \n>> Proposed patch\n>>\n>> --- a/drivers/pci/controller/dwc/pcie-designware.c\n>> +++ b/drivers/pci/controller/dwc/pcie-designware.c\n>> @@ -486,7 +486,7 @@ static inline void dw_pcie_writel_atu_ob(struct dw_pcie\n>> *pci, u32 index, u32 reg\n>>   static inline u32 dw_pcie_enable_ecrc(u32 val)\n>>   {\n>>          /*\n>> -        * DWC versions 0x3530302a and 0x3536322a has a design issue where\n>> the 'TD'\n>> +        * DWC versions less than 5.10A has a design issue where the 'TD'\n>>           * bit in the Control register-1 of the ATU outbound region acts\n>>           * like an override for the ECRC setting, i.e., the presence of TLP\n>>           * Digest (ECRC) in the outgoing TLPs is solely determined by this\n>> @@ -559,7 +559,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,\n>>          if (upper_32_bits(limit_addr) > upper_32_bits(parent_bus_addr) &&\n>>              dw_pcie_ver_is_ge(pci, 460A))\n>>                  val |= PCIE_ATU_INCREASE_REGION_SIZE;\n>> -       if (dw_pcie_ver_is(pci, 490A) || dw_pcie_ver_is(pci, 500A))\n>> +       if (!dw_pcie_ver_is_ge(pci, 510A))\n>>                  val = dw_pcie_enable_ecrc(val);\n>>          dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);\n>>\n>> diff --git a/drivers/pci/controller/dwc/pcie-designware.h\n>> b/drivers/pci/controller/dwc/pcie-designware.h\n>> index 5bceadbd2c9f..00891adfd07d 100644\n>> --- a/drivers/pci/controller/dwc/pcie-designware.h\n>> +++ b/drivers/pci/controller/dwc/pcie-designware.h\n>> @@ -35,6 +35,7 @@\n>>   #define DW_PCIE_VER_480A               0x3438302a\n>>   #define DW_PCIE_VER_490A               0x3439302a\n>>   #define DW_PCIE_VER_500A               0x3530302a\n>> +#define DW_PCIE_VER_510A               0x3531302a\n>>   #define DW_PCIE_VER_520A               0x3532302a\n>>   #define DW_PCIE_VER_540A               0x3534302a\n>>   #define DW_PCIE_VER_562A               0x3536322a\n>>\n>> Thanks,\n>> Manikanta\n>>\n>>>>    \tdw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);\n>>>> -- \n>>>> 2.34.1\n>>>>\n>>\n>> -- \n>> nvpublic\n>>","headers":{"Return-Path":"\n <linux-pci+bounces-52284-incoming=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=UAVwfBS5;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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