[{"id":3670057,"web_url":"http://patchwork.ozlabs.org/comment/3670057/","msgid":"","list_archive_url":null,"date":"2026-03-27T04:14:49","subject":"Re: [PATCH v5 3/7] target/riscv: Implement runtime data endianness\n via MSTATUS bits","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"I replied to v4 before I saw a v5 was already posted:\nhttps://lore.kernel.org/qemu-devel/d974df44-b46e-4e51-9eec-b46e391c3462@linaro.org/\n\nOn 3/25/26 02:40, Djordje Todorovic wrote:\n> Implement runtime big-endian data support by reading the MSTATUS\n> UBE/SBE/MBE bits to determine data endianness per privilege level.\n> \n> The key changes are:\n> \n> - Add riscv_cpu_data_is_big_endian() helper in cpu.h that checks\n> the appropriate MSTATUS endianness bit based on current privilege\n> level (MBE for M-mode, SBE for S-mode, UBE for U-mode).\n> \n> - Update mo_endian() in translate.c to return MO_BE or MO_LE based\n> on a new 'big_endian' field in DisasContext, rather than the\n> previous hardcoded MO_TE.\n> \n> - Update mo_endian_env() in op_helper.c to call the new helper,\n> giving hypervisor load/store helpers correct runtime endianness.\n> \n> - Pack the endianness flag into cs_base bit 32 (alongside misa_ext\n> in bits 0-25) in riscv_get_tb_cpu_state(), ensuring translation\n> blocks are correctly separated by data endianness.\n> \n> Note: instruction fetches continue to use MO_LE unconditionally\n> (from the previous patch), as RISC-V instructions are always\n> little-endian per the ISA specification.\n> \n> Signed-off-by: Djordje Todorovic \n> ---\n> target/riscv/cpu.h | 28 ++++++++++++++++++++++++++++\n> target/riscv/internals.h | 9 +--------\n> target/riscv/tcg/tcg-cpu.c | 9 ++++++++-\n> target/riscv/translate.c | 12 ++++--------\n> 4 files changed, 41 insertions(+), 17 deletions(-)\n> \n> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\n> index 35d1f6362c..ef870d05b3 100644\n> --- a/target/riscv/cpu.h\n> +++ b/target/riscv/cpu.h\n> @@ -703,6 +703,12 @@ FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1)\n> FIELD(TB_FLAGS, PM_PMM, 29, 2)\n> FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1)\n> \n> +/*\n> + * cs_base carries misa_ext (bits 0-25) plus additional flags.\n> + * Bit 32 is used for data endianness since TB_FLAGS has no free bits.\n> + */\n> +#define TB_CSBASE_BIG_ENDIAN (1ULL << 32)\n> +\n> #ifdef TARGET_RISCV32\n> #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)\n> #else\n> @@ -718,6 +724,28 @@ static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env)\n> return &env_archcpu(env)->cfg;\n> }\n> \n> +/*\n> + * Return true if data accesses are big-endian for the current privilege\n> + * level, based on the MSTATUS MBE/SBE/UBE bits.\n> + */\n> +static inline bool riscv_cpu_data_is_big_endian(CPURISCVState *env)\n> +{\n> +#if defined(CONFIG_USER_ONLY)\n> + return false;\n> +#else\n> + switch (env->priv) {\n> + case PRV_M:\n> + return env->mstatus & MSTATUS_MBE;\n> + case PRV_S:\n> + return env->mstatus & MSTATUS_SBE;\n> + case PRV_U:\n> + return env->mstatus & MSTATUS_UBE;\n> + default:\n> + g_assert_not_reached();\n> + }\n> +#endif\n> +}\n> +\n> #if !defined(CONFIG_USER_ONLY)\n> static inline int cpu_address_mode(CPURISCVState *env)\n> {\n> diff --git a/target/riscv/internals.h b/target/riscv/internals.h\n> index 460346dd6d..e2f0334da8 100644\n> --- a/target/riscv/internals.h\n> +++ b/target/riscv/internals.h\n> @@ -64,14 +64,7 @@ static inline bool mmuidx_2stage(int mmu_idx)\n> \n> static inline MemOp mo_endian_env(CPURISCVState *env)\n> {\n> - /*\n> - * A couple of bits in MSTATUS set the endianness:\n> - * - MSTATUS_UBE (User-mode),\n> - * - MSTATUS_SBE (Supervisor-mode),\n> - * - MSTATUS_MBE (Machine-mode)\n> - * but we don't implement that yet.\n> - */\n> - return MO_LE;\n> + return riscv_cpu_data_is_big_endian(env) ? MO_BE : MO_LE;\n> }\n> \n> /* share data between vector helpers and decode code */\n> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\n> index 3407191c22..fa42197e98 100644\n> --- a/target/riscv/tcg/tcg-cpu.c\n> +++ b/target/riscv/tcg/tcg-cpu.c\n> @@ -189,10 +189,17 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)\n> flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env));\n> flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext);\n> \n> + uint64_t cs_base = env->misa_ext;\n> +#ifndef CONFIG_USER_ONLY\n> + if (riscv_cpu_data_is_big_endian(env)) {\n> + cs_base |= TB_CSBASE_BIG_ENDIAN;\n> + }\n> +#endif\n> +\n> return (TCGTBCPUState){\n> .pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc,\n> .flags = flags,\n> - .cs_base = env->misa_ext,\n> + .cs_base = cs_base,\n> };\n> }\n> \n> diff --git a/target/riscv/translate.c b/target/riscv/translate.c\n> index 5df5b73849..d7f1f8e466 100644\n> --- a/target/riscv/translate.c\n> +++ b/target/riscv/translate.c\n> @@ -119,6 +119,8 @@ typedef struct DisasContext {\n> bool fcfi_lp_expected;\n> /* zicfiss extension, if shadow stack was enabled during TB gen */\n> bool bcfi_enabled;\n> + /* Data endianness from MSTATUS UBE/SBE/MBE */\n> + bool big_endian;\n> } DisasContext;\n> \n> static inline bool has_ext(DisasContext *ctx, uint32_t ext)\n> @@ -128,14 +130,7 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)\n> \n> static inline MemOp mo_endian(DisasContext *ctx)\n> {\n> - /*\n> - * A couple of bits in MSTATUS set the endianness:\n> - * - MSTATUS_UBE (User-mode),\n> - * - MSTATUS_SBE (Supervisor-mode),\n> - * - MSTATUS_MBE (Machine-mode)\n> - * but we don't implement that yet.\n> - */\n> - return MO_LE;\n> + return ctx->big_endian ? MO_BE : MO_LE;\n> }\n> \n> #ifdef TARGET_RISCV32\n> @@ -1346,6 +1341,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)\n> ctx->zero = tcg_constant_tl(0);\n> ctx->virt_inst_excp = false;\n> ctx->decoders = cpu->decoders;\n> + ctx->big_endian = ctx->base.tb->cs_base & TB_CSBASE_BIG_ENDIAN;\n> }\n> \n> static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=CPPnyMOQ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhnPQ5QF8z1y1j\n\tfor ; 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