[{"id":3670058,"web_url":"http://patchwork.ozlabs.org/comment/3670058/","msgid":"","list_archive_url":null,"date":"2026-03-27T04:15:52","subject":"Re: [PATCH v5 6/7] target/riscv: Support runtime endianness in virtio\n via sysemu callback","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 3/25/26 02:40, Djordje Todorovic wrote:\n> Implement the .virtio_is_big_endian SysemuCPUOps callback for RISC-V.\n> This makes cpu_virtio_is_big_endian() return the correct endianness\n> based on the hart's MSTATUS MBE/SBE/UBE bits, which is used by\n> virtio_current_cpu_endian() during guest-initiated device resets.\n> \n> For bi-endian RISC-V targets, this ensures legacy virtio devices\n> correctly detect the guest's runtime data endianness, matching\n> how ARM handles its bi-endian support.\n> \n> Signed-off-by: Djordje Todorovic \n> ---\n> target/riscv/cpu.c | 11 +++++++++++\n> 1 file changed, 11 insertions(+)\n\nNack.\n\nI replied to v4 before I saw v5:\nhttps://lore.kernel.org/qemu-devel/23a0d240-6f77-4edb-8128-fd2c2b8354df@linaro.org/\n\n\nr~\n\n> \n> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\n> index eed5afd27e..f813acf579 100644\n> --- a/target/riscv/cpu.c\n> +++ b/target/riscv/cpu.c\n> @@ -32,6 +32,7 @@\n> #include \"migration/vmstate.h\"\n> #include \"fpu/softfloat-helpers.h\"\n> #include \"system/device_tree.h\"\n> +#include \"system/hw_accel.h\"\n> #include \"system/kvm.h\"\n> #include \"system/tcg.h\"\n> #include \"kvm/kvm_riscv.h\"\n> @@ -2713,11 +2714,21 @@ static int64_t riscv_get_arch_id(CPUState *cs)\n> \n> #include \"hw/core/sysemu-cpu-ops.h\"\n> \n> +static bool riscv_cpu_virtio_is_big_endian(CPUState *cs)\n> +{\n> + RISCVCPU *cpu = RISCV_CPU(cs);\n> + CPURISCVState *env = &cpu->env;\n> +\n> + cpu_synchronize_state(cs);\n> + return riscv_cpu_data_is_big_endian(env);\n> +}\n> +\n> static const struct SysemuCPUOps riscv_sysemu_ops = {\n> .has_work = riscv_cpu_has_work,\n> .get_phys_page_debug = riscv_cpu_get_phys_page_debug,\n> .write_elf64_note = riscv_cpu_write_elf64_note,\n> .write_elf32_note = riscv_cpu_write_elf32_note,\n> + .internal_is_big_endian = riscv_cpu_virtio_is_big_endian,\n> .legacy_vmsd = &vmstate_riscv_cpu,\n> };\n> #endif","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=hjkzalia;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::634;\n envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3673780,"web_url":"http://patchwork.ozlabs.org/comment/3673780/","msgid":"<7a81cb84-e6e2-45c9-b73a-b4f93c14f584@htecgroup.com>","list_archive_url":null,"date":"2026-04-06T15:50:37","subject":"Re: [PATCH v5 6/7] target/riscv: Support runtime endianness in virtio\n via sysemu callback","submitter":{"id":90738,"url":"http://patchwork.ozlabs.org/api/people/90738/","name":"Djordje Todorovic","email":"Djordje.Todorovic@htecgroup.com"},"content":"On 3/27/26 05:15, Richard Henderson wrote:\n> [You don't often get email from richard.henderson@linaro.org. Learn \n> why this is important at https://aka.ms/LearnAboutSenderIdentification ]\n>\n> CAUTION: This email originated from outside of the organization. Do \n> not click links or open attachments unless you recognize the sender \n> and know the content is safe.\n>\n>\n> On 3/25/26 02:40, Djordje Todorovic wrote:\n>> Implement the .virtio_is_big_endian SysemuCPUOps callback for RISC-V.\n>> This makes cpu_virtio_is_big_endian() return the correct endianness\n>> based on the hart's MSTATUS MBE/SBE/UBE bits, which is used by\n>> virtio_current_cpu_endian() during guest-initiated device resets.\n>>\n>> For bi-endian RISC-V targets, this ensures legacy virtio devices\n>> correctly detect the guest's runtime data endianness, matching\n>> how ARM handles its bi-endian support.\n>>\n>> Signed-off-by: Djordje Todorovic \n>> ---\n>>   target/riscv/cpu.c | 11 +++++++++++\n>>   1 file changed, 11 insertions(+)\n>\n> Nack.\n>\n> I replied to v4 before I saw v5:\n> https://lore.kernel.org/qemu-devel/23a0d240-6f77-4edb-8128-fd2c2b8354df@linaro.org/ \n>\n>\nThanks a lot for the comment. We do not need this patch, I will drop it \nfrom v6.\nDjordje\n\n\n>\n> r~\n>\n>>\n>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\n>> index eed5afd27e..f813acf579 100644\n>> --- a/target/riscv/cpu.c\n>> +++ b/target/riscv/cpu.c\n>> @@ -32,6 +32,7 @@\n>>   #include \"migration/vmstate.h\"\n>>   #include \"fpu/softfloat-helpers.h\"\n>>   #include \"system/device_tree.h\"\n>> +#include \"system/hw_accel.h\"\n>>   #include \"system/kvm.h\"\n>>   #include \"system/tcg.h\"\n>>   #include \"kvm/kvm_riscv.h\"\n>> @@ -2713,11 +2714,21 @@ static int64_t riscv_get_arch_id(CPUState *cs)\n>>\n>>   #include \"hw/core/sysemu-cpu-ops.h\"\n>>\n>> +static bool riscv_cpu_virtio_is_big_endian(CPUState *cs)\n>> +{\n>> +    RISCVCPU *cpu = RISCV_CPU(cs);\n>> +    CPURISCVState *env = &cpu->env;\n>> +\n>> +    cpu_synchronize_state(cs);\n>> +    return riscv_cpu_data_is_big_endian(env);\n>> +}\n>> +\n>>   static const struct SysemuCPUOps riscv_sysemu_ops = {\n>>       .has_work = riscv_cpu_has_work,\n>>       .get_phys_page_debug = riscv_cpu_get_phys_page_debug,\n>>       .write_elf64_note = riscv_cpu_write_elf64_note,\n>>       .write_elf32_note = riscv_cpu_write_elf32_note,\n>> +    .internal_is_big_endian = riscv_cpu_virtio_is_big_endian,\n>>       .legacy_vmsd = &vmstate_riscv_cpu,\n>>   };\n>>   #endif\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=htecgroup.com header.i=@htecgroup.com\n header.a=rsa-sha256 header.s=selector1 header.b=UI7Opa7c;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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