[{"id":3668855,"web_url":"http://patchwork.ozlabs.org/comment/3668855/","msgid":"","list_archive_url":null,"date":"2026-03-25T07:26:12","subject":"Re: [PATCH v5 1/7] target/riscv: Add big-endian CPU property","submitter":{"id":92265,"url":"http://patchwork.ozlabs.org/api/people/92265/","name":"Chao Liu","email":"chao.liu.zevorn@gmail.com"},"content":"On Tue, Mar 24, 2026 at 04:40:15PM +0000, Djordje Todorovic wrote:\n> Add a \"big-endian\" boolean property to the RISC-V CPU configuration,\n> defaulting to false (little-endian). This property allows machine\n> models to configure individual HARTs for big-endian data operation.\n> \n> The RISC-V ISA supports big-endian data accesses via the mstatus\n> SBE/MBE/UBE bits, while instructions remain always little-endian.\n> This property provides the configuration interface; subsequent\n> patches will connect it to the CPU state and translation logic.\n> \nLGTM.\n\nReviewed-by: Chao Liu \n\nThanks,\nChao\n> Signed-off-by: Djordje Todorovic \n> ---\n> target/riscv/cpu.c | 1 +\n> target/riscv/cpu_cfg_fields.h.inc | 1 +\n> 2 files changed, 2 insertions(+)\n> \n> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\n> index e56470a374..4537305dfe 100644\n> --- a/target/riscv/cpu.c\n> +++ b/target/riscv/cpu.c\n> @@ -2641,6 +2641,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {\n> \n> static const Property riscv_cpu_properties[] = {\n> DEFINE_PROP_BOOL(\"debug\", RISCVCPU, cfg.debug, true),\n> + DEFINE_PROP_BOOL(\"big-endian\", RISCVCPU, cfg.big_endian, false),\n> \n> {.name = \"pmu-mask\", .info = &prop_pmu_mask},\n> {.name = \"pmu-num\", .info = &prop_pmu_num}, /* Deprecated */\n> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc\n> index 70ec650abf..51436daabf 100644\n> --- a/target/riscv/cpu_cfg_fields.h.inc\n> +++ b/target/riscv/cpu_cfg_fields.h.inc\n> @@ -154,6 +154,7 @@ BOOL_FIELD(ext_xmipscbop)\n> BOOL_FIELD(ext_xmipscmov)\n> BOOL_FIELD(ext_xmipslsp)\n> \n> +BOOL_FIELD(big_endian)\n> BOOL_FIELD(mmu)\n> BOOL_FIELD(pmp)\n> BOOL_FIELD(debug)\n> -- \n> 2.34.1\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=YPdPW/hd;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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This property allows machine\n> models to configure individual HARTs for big-endian data operation.\n> \n> The RISC-V ISA supports big-endian data accesses via the mstatus\n> SBE/MBE/UBE bits, while instructions remain always little-endian.\n> This property provides the configuration interface; subsequent\n> patches will connect it to the CPU state and translation logic.\n> \n> Signed-off-by: Djordje Todorovic \n> ---\n> target/riscv/cpu.c | 1 +\n> target/riscv/cpu_cfg_fields.h.inc | 1 +\n> 2 files changed, 2 insertions(+)\n> \n> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\n> index e56470a374..4537305dfe 100644\n> --- a/target/riscv/cpu.c\n> +++ b/target/riscv/cpu.c\n> @@ -2641,6 +2641,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {\n> \n> static const Property riscv_cpu_properties[] = {\n> DEFINE_PROP_BOOL(\"debug\", RISCVCPU, cfg.debug, true),\n> + DEFINE_PROP_BOOL(\"big-endian\", RISCVCPU, cfg.big_endian, false),\n\nNote that there is also a DEFINE_PROP_ENDIAN available ... not sure whether \nit's a better fit here, though. Maybe mention in the patch description why \nBOOL is better than ENDIAN here?\n\n Thomas","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=mimecast20190719 header.b=hmPYul8s;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=google header.b=WmAIBlN5;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fgkCb03rGz1y1K\n\tfor ; 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