[{"id":3668545,"web_url":"http://patchwork.ozlabs.org/comment/3668545/","msgid":"","list_archive_url":null,"date":"2026-03-24T15:51:12","subject":"Re: [Intel-wired-lan] [PATCH iwl-next v3] ice: add 200G_AUI8 PHY\n type definitions and wire them up","submitter":{"id":70275,"url":"http://patchwork.ozlabs.org/api/people/70275/","name":"Paul Menzel","email":"pmenzel@molgen.mpg.de"},"content":"Dear Aleksandr,\n\n\nThank you for your patch.\n\nAm 24.03.26 um 16:35 schrieb Aleksandr Loktionov:\n> ice_link_mode_str_high[] lacks entries for phy_type_high bits 5-14\n> (all 200G PHY types on E825C); ice_dump_phy_type() prints nothing for\n> them when ICE_DBG_LINK is set (e.g. 'ethtool -s ethX msglvl 0x10').\n> The loop also iterates all 64 bits against a 5-entry array - undefined\n> behaviour for any matched bit beyond the end. Add strings for bits\n> 5-14 and guard the loop with ARRAY_SIZE(), falling back to \"unknown\"\n> for unrecognised bits.\n> \n> ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC (bit 13) and 200G_AUI8 (bit 14)\n> were absent from ice_adminq_cmd.h; ICE_PHY_TYPE_HIGH_MAX_INDEX capped\n> at 12 caused ice_update_phy_type() to skip them entirely, leaving both\n> invisible to 200G speed requests. Add the definitions and bump\n> MAX_INDEX to 14.\n> \n> Wire the two new types throughout the driver:\n> - ice_get_media_type(): handle all ten 200G phy_type_high values so\n> E825C ports no longer return ICE_MEDIA_UNKNOWN. AOC_ACC interfaces\n> map to FIBER; bare AUI4/AUI8 to DA with cage, else BACKPLANE\n> (matching existing AUI2/CAUI2 logic); CR4_PAM4 to DA; SR4/FR4/LR4/\n> DR4 to FIBER; KR4_PAM4 to BACKPLANE.\n> - ice_get_link_speed_based_on_phy_type(): return ICE_AQ_LINK_SPEED_200GB\n> for both new types so ice_update_phy_type() enables them correctly.\n> - phy_type_high_lkup[13,14]: AUI8 is 8-lane 25G-per-lane; no\n> 200000baseSR8/CR8 ethtool modes exist yet, so approximate with\n> SR4_Full/CR4_Full - matching AUI4 at indices 11-12. FIXME once\n> those link modes land upstream.\n> - ICE_PHY_TYPE_HIGH_MASK_200G: add bits 13-14 for the minimum-speed\n> floor in ice_mask_min_supported_speeds().\n> \n> Suggested-by: Paul Greenwalt \n> Signed-off-by: Aleksandr Loktionov \n> Cc: Simon Horman \n> Cc: Paul Menzel \n> ---\n> v3 -> v4: add ARRAY_SIZE() OOB guard in ice_dump_phy_type(); cover all\n> ten 200G phy_type_high values in ice_get_media_type(); add FIXME\n> to lkup[13..14] for missing SR8/CR8 modes; rename subject\n> fix subject; fix debug enable example (ethtool, not modprobe);\n> add AUI8 speed mapping, lkup[13-14], MASK_200G bits 13-14,\n> and AUI8->SR4/CR4 approximation comment\n> v1 -> v2: add ICE_PHY_TYPE_HIGH_MAX_INDEX update\n> ---\n> .../net/ethernet/intel/ice/ice_adminq_cmd.h | 4 ++-\n> drivers/net/ethernet/intel/ice/ice_common.c | 31 ++++++++++++++++++-\n> drivers/net/ethernet/intel/ice/ice_ethtool.c | 4 ++-\n> drivers/net/ethernet/intel/ice/ice_ethtool.h | 8 +++++\n> 4 files changed, 44 insertions(+), 3 deletions(-)\n> \n> diff --git a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\n> index 859e9c6..efe985c 100644\n> --- a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\n> +++ b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\n> @@ -1044,7 +1044,9 @@ struct ice_aqc_get_phy_caps {\n> #define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4\t\tBIT_ULL(10)\n> #define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC\tBIT_ULL(11)\n> #define ICE_PHY_TYPE_HIGH_200G_AUI4\t\tBIT_ULL(12)\n> -#define ICE_PHY_TYPE_HIGH_MAX_INDEX\t\t12\n> +#define ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC\tBIT_ULL(13)\n> +#define ICE_PHY_TYPE_HIGH_200G_AUI8\t\tBIT_ULL(14)\n> +#define ICE_PHY_TYPE_HIGH_MAX_INDEX\t\t14\n> \n> struct ice_aqc_get_phy_caps_data {\n> \t__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */\n> diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c\n> index ce11fea..2f3a268 100644\n> --- a/drivers/net/ethernet/intel/ice/ice_common.c\n> +++ b/drivers/net/ethernet/intel/ice/ice_common.c\n> @@ -84,6 +84,16 @@ static const char * const ice_link_mode_str_high[] = {\n> \t[2] = \"100G_CAUI2\",\n> \t[3] = \"100G_AUI2_AOC_ACC\",\n> \t[4] = \"100G_AUI2\",\n> +\t[5] = \"200G_CR4_PAM4\",\n> +\t[6] = \"200G_SR4\",\n> +\t[7] = \"200G_FR4\",\n> +\t[8] = \"200G_LR4\",\n> +\t[9] = \"200G_DR4\",\n> +\t[10] = \"200G_KR4_PAM4\",\n> +\t[11] = \"200G_AUI4_AOC_ACC\",\n> +\t[12] = \"200G_AUI4\",\n> +\t[13] = \"200G_AUI8_AOC_ACC\",\n> +\t[14] = \"200G_AUI8\",\n> };\n> \n> /**\n> @@ -107,9 +117,14 @@ ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix)\n> \tice_debug(hw, ICE_DBG_PHY, \"%s: phy_type_high: 0x%016llx\\n\", prefix, high);\n> \n> \tfor (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) {\n> -\t\tif (high & BIT_ULL(i))\n> +\t\tif (!(high & BIT_ULL(i)))\n> +\t\t\tcontinue;\n> +\t\tif (i < ARRAY_SIZE(ice_link_mode_str_high))\n> \t\t\tice_debug(hw, ICE_DBG_PHY, \"%s: bit(%d): %s\\n\",\n> \t\t\t\t prefix, i, ice_link_mode_str_high[i]);\n> +\t\telse\n> +\t\t\tice_debug(hw, ICE_DBG_PHY, \"%s: bit(%d): unknown\\n\",\n> +\t\t\t\t prefix, i);\n> \t}\n> }\n> \n> @@ -605,13 +620,25 @@ static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)\n> \t\tswitch (hw_link_info->phy_type_high) {\n> \t\tcase ICE_PHY_TYPE_HIGH_100G_AUI2:\n> \t\tcase ICE_PHY_TYPE_HIGH_100G_CAUI2:\n> +\t\tcase ICE_PHY_TYPE_HIGH_200G_AUI4:\n> +\t\tcase ICE_PHY_TYPE_HIGH_200G_AUI8:\n> \t\t\tif (ice_is_media_cage_present(pi))\n> \t\t\t\treturn ICE_MEDIA_DA;\n> \t\t\tfallthrough;\n> \t\tcase ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:\n> +\t\tcase ICE_PHY_TYPE_HIGH_200G_KR4_PAM4:\n> \t\t\treturn ICE_MEDIA_BACKPLANE;\n> \t\tcase ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:\n> \t\tcase ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:\n> +\t\tcase ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC:\n> +\t\tcase ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC:\n> +\t\t\treturn ICE_MEDIA_FIBER;\n> +\t\tcase ICE_PHY_TYPE_HIGH_200G_CR4_PAM4:\n> +\t\t\treturn ICE_MEDIA_DA;\n> +\t\tcase ICE_PHY_TYPE_HIGH_200G_SR4:\n> +\t\tcase ICE_PHY_TYPE_HIGH_200G_FR4:\n> +\t\tcase ICE_PHY_TYPE_HIGH_200G_LR4:\n> +\t\tcase ICE_PHY_TYPE_HIGH_200G_DR4:\n> \t\t\treturn ICE_MEDIA_FIBER;\n> \t\t}\n> \t}\n> @@ -3493,6 +3520,8 @@ u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)\n> \tcase ICE_PHY_TYPE_HIGH_200G_KR4_PAM4:\n> \tcase ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC:\n> \tcase ICE_PHY_TYPE_HIGH_200G_AUI4:\n> +\tcase ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC:\n> +\tcase ICE_PHY_TYPE_HIGH_200G_AUI8:\n> \t\tspeed_phy_type_high = ICE_AQ_LINK_SPEED_200GB;\n> \t\tbreak;\n> \tdefault:\n> diff --git a/drivers/net/ethernet/intel/ice/ice_ethtool.c b/drivers/net/ethernet/intel/ice/ice_ethtool.c\n> index 301947d..beb638c 100644\n> --- a/drivers/net/ethernet/intel/ice/ice_ethtool.c\n> +++ b/drivers/net/ethernet/intel/ice/ice_ethtool.c\n> @@ -2057,7 +2057,9 @@ ice_get_ethtool_stats(struct net_device *netdev,\n> \t\t\t\t\t ICE_PHY_TYPE_HIGH_200G_DR4 | \\\n> \t\t\t\t\t ICE_PHY_TYPE_HIGH_200G_KR4_PAM4 | \\\n> \t\t\t\t\t ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC | \\\n> -\t\t\t\t\t ICE_PHY_TYPE_HIGH_200G_AUI4)\n> +\t\t\t\t\t ICE_PHY_TYPE_HIGH_200G_AUI4 | \\\n> +\t\t\t\t\t ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC | \\\n> +\t\t\t\t\t ICE_PHY_TYPE_HIGH_200G_AUI8)\n> \n> /**\n> * ice_mask_min_supported_speeds\n> diff --git a/drivers/net/ethernet/intel/ice/ice_ethtool.h b/drivers/net/ethernet/intel/ice/ice_ethtool.h\n> index 23b2cfb..c4732a3 100644\n> --- a/drivers/net/ethernet/intel/ice/ice_ethtool.h\n> +++ b/drivers/net/ethernet/intel/ice/ice_ethtool.h\n> @@ -153,6 +153,14 @@ phy_type_high_lkup[] = {\n> \t[10] = ICE_PHY_TYPE(200GB, 200000baseKR4_Full),\n> \t[11] = ICE_PHY_TYPE(200GB, 200000baseSR4_Full),\n> \t[12] = ICE_PHY_TYPE(200GB, 200000baseCR4_Full),\n> +\t/* 200G_AUI8_AOC_ACC and 200G_AUI8 are 8-lane 25G-per-lane interfaces.\n> +\t * The kernel has no 200000baseSR8/CR8 modes yet; map to the closest\n> +\t * available 4-lane equivalents so ethtool reports 200G as supported.\n> +\t * FIXME: replace with 200000baseSR8_Full / 200000baseCR8_Full once\n> +\t * those ethtool link modes are defined upstream.\n> +\t */\n> +\t[13] = ICE_PHY_TYPE(200GB, 200000baseSR4_Full),\n> +\t[14] = ICE_PHY_TYPE(200GB, 200000baseCR4_Full),\n> };\n> \n> #endif /* !_ICE_ETHTOOL_H_ */\n\nReviewed-by: Paul Menzel \n\n\nKind regards,\n\nPaul","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=hhH6tVt2;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::137; helo=smtp4.osuosl.org;\n envelope-from=intel-wired-lan-bounces@osuosl.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from smtp4.osuosl.org (smtp4.osuosl.org [IPv6:2605:bc80:3010::137])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fgF062SSYz1y1g\n\tfor ; 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client-ip=141.14.17.11;\n helo=mx3.molgen.mpg.de; envelope-from=pmenzel@molgen.mpg.de;\n receiver=","DMARC-Filter":"OpenDMARC Filter v1.4.2 smtp3.osuosl.org 4F1A160D72","Message-ID":"","Date":"Tue, 24 Mar 2026 16:51:12 +0100","MIME-Version":"1.0","User-Agent":"Mozilla Thunderbird","To":"Aleksandr Loktionov ","Cc":"intel-wired-lan@lists.osuosl.org, anthony.l.nguyen@intel.com,\n netdev@vger.kernel.org, Paul Greenwalt ,\n Simon Horman ","References":"<20260324153542.674859-1-aleksandr.loktionov@intel.com>","Content-Language":"en-US","From":"Paul Menzel ","In-Reply-To":"<20260324153542.674859-1-aleksandr.loktionov@intel.com>","Content-Type":"text/plain; charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","X-Mailman-Original-Authentication-Results":"smtp3.osuosl.org;\n dmarc=none (p=none dis=none)\n header.from=molgen.mpg.de","Subject":"Re: [Intel-wired-lan] [PATCH iwl-next v3] ice: add 200G_AUI8 PHY\n type definitions and wire them up","X-BeenThere":"intel-wired-lan@osuosl.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Intel Wired Ethernet Linux Kernel Driver Development\n ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"intel-wired-lan-bounces@osuosl.org","Sender":"\"Intel-wired-lan\" "}},{"id":3670217,"web_url":"http://patchwork.ozlabs.org/comment/3670217/","msgid":"<20260327104732.GB567789@horms.kernel.org>","list_archive_url":null,"date":"2026-03-27T10:47:32","subject":"Re: [Intel-wired-lan] [PATCH iwl-next v3] ice: add 200G_AUI8 PHY\n type definitions and wire them up","submitter":{"id":82748,"url":"http://patchwork.ozlabs.org/api/people/82748/","name":"Simon Horman","email":"horms@kernel.org"},"content":"On Tue, Mar 24, 2026 at 04:35:42PM +0100, Aleksandr Loktionov wrote:\n> ice_link_mode_str_high[] lacks entries for phy_type_high bits 5-14\n> (all 200G PHY types on E825C); ice_dump_phy_type() prints nothing for\n> them when ICE_DBG_LINK is set (e.g. 'ethtool -s ethX msglvl 0x10').\n> The loop also iterates all 64 bits against a 5-entry array - undefined\n> behaviour for any matched bit beyond the end. Add strings for bits\n> 5-14 and guard the loop with ARRAY_SIZE(), falling back to \"unknown\"\n> for unrecognised bits.\n> \n> ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC (bit 13) and 200G_AUI8 (bit 14)\n> were absent from ice_adminq_cmd.h; ICE_PHY_TYPE_HIGH_MAX_INDEX capped\n> at 12 caused ice_update_phy_type() to skip them entirely, leaving both\n> invisible to 200G speed requests. Add the definitions and bump\n> MAX_INDEX to 14.\n> \n> Wire the two new types throughout the driver:\n> - ice_get_media_type(): handle all ten 200G phy_type_high values so\n> E825C ports no longer return ICE_MEDIA_UNKNOWN. AOC_ACC interfaces\n> map to FIBER; bare AUI4/AUI8 to DA with cage, else BACKPLANE\n> (matching existing AUI2/CAUI2 logic); CR4_PAM4 to DA; SR4/FR4/LR4/\n> DR4 to FIBER; KR4_PAM4 to BACKPLANE.\n> - ice_get_link_speed_based_on_phy_type(): return ICE_AQ_LINK_SPEED_200GB\n> for both new types so ice_update_phy_type() enables them correctly.\n> - phy_type_high_lkup[13,14]: AUI8 is 8-lane 25G-per-lane; no\n> 200000baseSR8/CR8 ethtool modes exist yet, so approximate with\n> SR4_Full/CR4_Full - matching AUI4 at indices 11-12. FIXME once\n> those link modes land upstream.\n> - ICE_PHY_TYPE_HIGH_MASK_200G: add bits 13-14 for the minimum-speed\n> floor in ice_mask_min_supported_speeds().\n> \n> Suggested-by: Paul Greenwalt \n> Signed-off-by: Aleksandr Loktionov \n> Cc: Simon Horman \n> Cc: Paul Menzel \n> ---\n> v3 -> v4: add ARRAY_SIZE() OOB guard in ice_dump_phy_type(); cover all\n> ten 200G phy_type_high values in ice_get_media_type(); add FIXME\n> to lkup[13..14] for missing SR8/CR8 modes; rename subject\n> fix subject; fix debug enable example (ethtool, not modprobe);\n> add AUI8 speed mapping, lkup[13-14], MASK_200G bits 13-14,\n> and AUI8->SR4/CR4 approximation comment\n> v1 -> v2: add ICE_PHY_TYPE_HIGH_MAX_INDEX update\n\nThanks for the updates.\n\nReviewed-by: Simon Horman ","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=ZekP/kqk;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::138; 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receiver=","DMARC-Filter":"OpenDMARC Filter v1.4.2 smtp3.osuosl.org ADD7D6128F","Date":"Fri, 27 Mar 2026 10:47:32 +0000","From":"Simon Horman ","To":"Aleksandr Loktionov ","Cc":"intel-wired-lan@lists.osuosl.org, anthony.l.nguyen@intel.com,\n netdev@vger.kernel.org, Paul Greenwalt ,\n Paul Menzel ","Message-ID":"<20260327104732.GB567789@horms.kernel.org>","References":"<20260324153542.674859-1-aleksandr.loktionov@intel.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20260324153542.674859-1-aleksandr.loktionov@intel.com>","X-Mailman-Original-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=kernel.org; s=k20201202; t=1774608456;\n bh=r8OjbGRJ6dRl5LnFR7ool+5ejKgvKJDtEWK8kYX9IKY=;\n h=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n b=i1e2SwED2RVc9xwPFJddwd7l0aG9w8ww3zAFuC3hxAl4vGwrPcmOsoV3toopAjA/7\n E+5SR/x1Bi6ptb/m1EaVXNwOyXx/mtnR3SyJnwAfxbmpV7GOB/RUqXZOZJskYAwM8o\n bebwwg7A737E4jpYTVzge/4LqV+/e4A9dphKhsQYrGb6U2U7cWMQCVoDIimlkS89Om\n 2LTv4rKhkiNHQ9ZHpWVI/KkVAMjojTBwkwEKIqr51YbNYw6CoHqwyOWnPyBBKJfhQ4\n M8ILvVKuT++cygF5tgUmzP9rcHIwFCIRKwnKThBayO+LJG8qLo00FUi2PchnBrGlw7\n pYBAR1dQQZ+CA==","X-Mailman-Original-Authentication-Results":["smtp3.osuosl.org;\n dmarc=pass (p=quarantine dis=none)\n header.from=kernel.org","smtp3.osuosl.org;\n dkim=pass (2048-bit key,\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=i1e2SwED"],"Subject":"Re: [Intel-wired-lan] [PATCH iwl-next v3] ice: add 200G_AUI8 PHY\n type definitions and wire them up","X-BeenThere":"intel-wired-lan@osuosl.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Intel Wired Ethernet Linux Kernel Driver Development\n ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"intel-wired-lan-bounces@osuosl.org","Sender":"\"Intel-wired-lan\" "}},{"id":3671933,"web_url":"http://patchwork.ozlabs.org/comment/3671933/","msgid":"","list_archive_url":null,"date":"2026-03-31T20:59:37","subject":"Re: [Intel-wired-lan] [PATCH iwl-next v3] ice: add 200G_AUI8 PHY\n type definitions and wire them up","submitter":{"id":68875,"url":"http://patchwork.ozlabs.org/api/people/68875/","name":"Tony Nguyen","email":"anthony.l.nguyen@intel.com"},"content":"On 3/24/2026 8:35 AM, Aleksandr Loktionov wrote:\n> ice_link_mode_str_high[] lacks entries for phy_type_high bits 5-14\n> (all 200G PHY types on E825C); ice_dump_phy_type() prints nothing for\n> them when ICE_DBG_LINK is set (e.g. 'ethtool -s ethX msglvl 0x10').\n> The loop also iterates all 64 bits against a 5-entry array - undefined\n> behaviour for any matched bit beyond the end. Add strings for bits\n> 5-14 and guard the loop with ARRAY_SIZE(), falling back to \"unknown\"\n> for unrecognised bits.\n> \n> ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC (bit 13) and 200G_AUI8 (bit 14)\n> were absent from ice_adminq_cmd.h; ICE_PHY_TYPE_HIGH_MAX_INDEX capped\n> at 12 caused ice_update_phy_type() to skip them entirely, leaving both\n> invisible to 200G speed requests. Add the definitions and bump\n> MAX_INDEX to 14.\n\nI don't believe support for these two types got implemented so I don't \nthink there is need to add them.\n\n> \n> Wire the two new types throughout the driver:\n> - ice_get_media_type(): handle all ten 200G phy_type_high values so\n> E825C ports no longer return ICE_MEDIA_UNKNOWN. AOC_ACC interfaces\n> map to FIBER; bare AUI4/AUI8 to DA with cage, else BACKPLANE\n> (matching existing AUI2/CAUI2 logic); CR4_PAM4 to DA; SR4/FR4/LR4/\n> DR4 to FIBER; KR4_PAM4 to BACKPLANE.\n> - ice_get_link_speed_based_on_phy_type(): return ICE_AQ_LINK_SPEED_200GB\n> for both new types so ice_update_phy_type() enables them correctly.\n> - phy_type_high_lkup[13,14]: AUI8 is 8-lane 25G-per-lane; no\n> 200000baseSR8/CR8 ethtool modes exist yet, so approximate with\n> SR4_Full/CR4_Full - matching AUI4 at indices 11-12. FIXME once\n> those link modes land upstream.\n> - ICE_PHY_TYPE_HIGH_MASK_200G: add bits 13-14 for the minimum-speed\n> floor in ice_mask_min_supported_speeds().\n> \n> Suggested-by: Paul Greenwalt \n> Signed-off-by: Aleksandr Loktionov \n> Cc: Simon Horman \n> Cc: Paul Menzel \n> ---\n> v3 -> v4: add ARRAY_SIZE() OOB guard in ice_dump_phy_type(); cover all\n> ten 200G phy_type_high values in ice_get_media_type(); add FIXME\n> to lkup[13..14] for missing SR8/CR8 modes; rename subject\n> fix subject; fix debug enable example (ethtool, not modprobe);\n> add AUI8 speed mapping, lkup[13-14], MASK_200G bits 13-14,\n> and AUI8->SR4/CR4 approximation comment\n> v1 -> v2: add ICE_PHY_TYPE_HIGH_MAX_INDEX update\n> ---\n> .../net/ethernet/intel/ice/ice_adminq_cmd.h | 4 ++-\n> drivers/net/ethernet/intel/ice/ice_common.c | 31 ++++++++++++++++++-\n> drivers/net/ethernet/intel/ice/ice_ethtool.c | 4 ++-\n> drivers/net/ethernet/intel/ice/ice_ethtool.h | 8 +++++\n> 4 files changed, 44 insertions(+), 3 deletions(-)\n> \n> diff --git a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\n> index 859e9c6..efe985c 100644\n> --- a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\n> +++ b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\n> @@ -1044,7 +1044,9 @@ struct ice_aqc_get_phy_caps {\n> #define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4\t\tBIT_ULL(10)\n> #define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC\tBIT_ULL(11)\n> #define ICE_PHY_TYPE_HIGH_200G_AUI4\t\tBIT_ULL(12)\n> -#define ICE_PHY_TYPE_HIGH_MAX_INDEX\t\t12\n> +#define ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC\tBIT_ULL(13)\n> +#define ICE_PHY_TYPE_HIGH_200G_AUI8\t\tBIT_ULL(14)\n> +#define ICE_PHY_TYPE_HIGH_MAX_INDEX\t\t14\n> \n> struct ice_aqc_get_phy_caps_data {\n> \t__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */\n> diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c\n> index ce11fea..2f3a268 100644\n> --- a/drivers/net/ethernet/intel/ice/ice_common.c\n> +++ b/drivers/net/ethernet/intel/ice/ice_common.c\n> @@ -84,6 +84,16 @@ static const char * const ice_link_mode_str_high[] = {\n> \t[2] = \"100G_CAUI2\",\n> \t[3] = \"100G_AUI2_AOC_ACC\",\n> \t[4] = \"100G_AUI2\",\n> +\t[5] = \"200G_CR4_PAM4\",\n> +\t[6] = \"200G_SR4\",\n> +\t[7] = \"200G_FR4\",\n> +\t[8] = \"200G_LR4\",\n> +\t[9] = \"200G_DR4\",\n> +\t[10] = \"200G_KR4_PAM4\",\n> +\t[11] = \"200G_AUI4_AOC_ACC\",\n> +\t[12] = \"200G_AUI4\",\n> +\t[13] = \"200G_AUI8_AOC_ACC\",\n> +\t[14] = \"200G_AUI8\",\n> };\n> \n> /**\n> @@ -107,9 +117,14 @@ ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix)\n> \tice_debug(hw, ICE_DBG_PHY, \"%s: phy_type_high: 0x%016llx\\n\", prefix, high);\n> \n> \tfor (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) {\n> -\t\tif (high & BIT_ULL(i))\n> +\t\tif (!(high & BIT_ULL(i)))\n> +\t\t\tcontinue;\n> +\t\tif (i < ARRAY_SIZE(ice_link_mode_str_high))\n> \t\t\tice_debug(hw, ICE_DBG_PHY, \"%s: bit(%d): %s\\n\",\n> \t\t\t\t prefix, i, ice_link_mode_str_high[i]);\n> +\t\telse\n> +\t\t\tice_debug(hw, ICE_DBG_PHY, \"%s: bit(%d): unknown\\n\",\n> +\t\t\t\t prefix, i);\n> \t}\n> }\n> \n> @@ -605,13 +620,25 @@ static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)\n> \t\tswitch (hw_link_info->phy_type_high) {\n> \t\tcase ICE_PHY_TYPE_HIGH_100G_AUI2:\n> \t\tcase ICE_PHY_TYPE_HIGH_100G_CAUI2:\n> +\t\tcase ICE_PHY_TYPE_HIGH_200G_AUI4:\n> +\t\tcase ICE_PHY_TYPE_HIGH_200G_AUI8:\n> \t\t\tif (ice_is_media_cage_present(pi))\n> \t\t\t\treturn ICE_MEDIA_DA;\n> \t\t\tfallthrough;\n> \t\tcase ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:\n> +\t\tcase ICE_PHY_TYPE_HIGH_200G_KR4_PAM4:\n> \t\t\treturn ICE_MEDIA_BACKPLANE;\n> \t\tcase ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:\n> \t\tcase ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:\n> +\t\tcase ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC:\n> +\t\tcase ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC:\n> +\t\t\treturn ICE_MEDIA_FIBER;\n> +\t\tcase ICE_PHY_TYPE_HIGH_200G_CR4_PAM4:\n> +\t\t\treturn ICE_MEDIA_DA;\n\nAny reason we don't put this with the other DAs above...\n\n> +\t\tcase ICE_PHY_TYPE_HIGH_200G_SR4:\n> +\t\tcase ICE_PHY_TYPE_HIGH_200G_FR4:\n> +\t\tcase ICE_PHY_TYPE_HIGH_200G_LR4:\n> +\t\tcase ICE_PHY_TYPE_HIGH_200G_DR4:\n> \t\t\treturn ICE_MEDIA_FIBER;\n\nand these with the other FIBERs?\n\nThanks,\nTony","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=qbe2Uf3t;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::138; 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