[{"id":3641204,"web_url":"http://patchwork.ozlabs.org/comment/3641204/","msgid":"","list_archive_url":null,"date":"2026-01-23T23:59:20","subject":"Re: [PATCH v2 1/1] x86: Fix for cache computation on Hygon under\n hypervisors","submitter":{"id":4387,"url":"http://patchwork.ozlabs.org/api/people/4387/","name":"H.J. Lu","email":"hjl.tools@gmail.com"},"content":"On Fri, Jan 16, 2026 at 3:46 PM Jiamei Xie wrote:\n>\n> On Hygon CPUs, glibc currently relies on CPUID leaf 0x8000001D to\n> compute cache parameters. This works correctly on bare-metal\n> systems. However, under some hypervisors (e.g. QEMU with -cpu\n> qemu64), the maximum supported extended CPUID leaf is only\n> 0x8000000A, and CPUID 0x8000001D is not exposed. In this case,\n> cache information computed via 0x8000001D is zeroed out.\n>\n> This patch introduces legacy fallback of cache computation based on\n> CPUID 0x80000005 and 0x80000006, consistent with the AMD\n> implementation, to restore correct cache information under such\n> environments.\n>\n> Signed-off-by: Jiamei Xie \n> ---\n> sysdeps/x86/dl-cacheinfo.h | 201 +++++++++++++++++++++++++++++++++----\n> 1 file changed, 179 insertions(+), 22 deletions(-)\n>\n> diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h\n> index b6520bddaa..d2d4301bc7 100644\n> --- a/sysdeps/x86/dl-cacheinfo.h\n> +++ b/sysdeps/x86/dl-cacheinfo.h\n> @@ -585,35 +585,192 @@ handle_hygon (int name)\n> unsigned int ebx;\n> unsigned int ecx;\n> unsigned int edx;\n> - unsigned int count = 0x1;\n> + unsigned int max_cpuid = 0;\n> +\n> + /* No level 4 cache (yet). */\n> + if (name > _SC_LEVEL3_CACHE_LINESIZE)\n> + return 0;\n> +\n> + __cpuid (0x80000000, max_cpuid, ebx, ecx, edx);\n> +\n> + if (max_cpuid >= 0x8000001D)\n> + /* Use __cpuid__ '0x8000_001D' to compute cache details. */\n> + {\n> + unsigned int count = 0x1;\n>\n> - if (name >= _SC_LEVEL3_CACHE_SIZE)\n> - count = 0x3;\n> - else if (name >= _SC_LEVEL2_CACHE_SIZE)\n> - count = 0x2;\n> - else if (name >= _SC_LEVEL1_DCACHE_SIZE)\n> - count = 0x0;\n> + if (name >= _SC_LEVEL3_CACHE_SIZE)\n> + count = 0x3;\n> + else if (name >= _SC_LEVEL2_CACHE_SIZE)\n> + count = 0x2;\n> + else if (name >= _SC_LEVEL1_DCACHE_SIZE)\n> + count = 0x0;\n> +\n> + __cpuid_count (0x8000001D, count, eax, ebx, ecx, edx);\n>\n> - /* Use __cpuid__ '0x8000_001D' to compute cache details. */\n> - __cpuid_count (0x8000001D, count, eax, ebx, ecx, edx);\n> + if (ecx != 0)\n> + {\n> + switch (name)\n> + {\n> + case _SC_LEVEL1_ICACHE_ASSOC:\n> + case _SC_LEVEL1_DCACHE_ASSOC:\n> + case _SC_LEVEL2_CACHE_ASSOC:\n> + case _SC_LEVEL3_CACHE_ASSOC:\n> + return ((ebx >> 22) & 0x3ff) + 1;\n> + case _SC_LEVEL1_ICACHE_LINESIZE:\n> + case _SC_LEVEL1_DCACHE_LINESIZE:\n> + case _SC_LEVEL2_CACHE_LINESIZE:\n> + case _SC_LEVEL3_CACHE_LINESIZE:\n> + return (ebx & 0xfff) + 1;\n> + case _SC_LEVEL1_ICACHE_SIZE:\n> + case _SC_LEVEL1_DCACHE_SIZE:\n> + case _SC_LEVEL2_CACHE_SIZE:\n> + case _SC_LEVEL3_CACHE_SIZE:\n> + return (((ebx >> 22) & 0x3ff) + 1) * ((ebx & 0xfff) + 1) * (ecx + 1);\n> + default:\n> + __builtin_unreachable ();\n> + }\n> + return -1;\n> + }\n> + }\n> +\n> + /* Legacy cache computation for some hypervisors that\n> + accidentally configure __cpuid__ '0x8000_001D' to Zero. */\n> +\n> + unsigned int fn = 0x80000005 + (name >= _SC_LEVEL2_CACHE_SIZE);\n> +\n> + if (max_cpuid < fn)\n> + return 0;\n> +\n> + __cpuid (fn, eax, ebx, ecx, edx);\n> +\n> + if (name < _SC_LEVEL1_DCACHE_SIZE)\n> + {\n> + name += _SC_LEVEL1_DCACHE_SIZE - _SC_LEVEL1_ICACHE_SIZE;\n> + ecx = edx;\n> + }\n>\n> switch (name)\n> {\n> - case _SC_LEVEL1_ICACHE_ASSOC:\n> - case _SC_LEVEL1_DCACHE_ASSOC:\n> - case _SC_LEVEL2_CACHE_ASSOC:\n> + case _SC_LEVEL1_DCACHE_SIZE:\n> + return (ecx >> 14) & 0x3fc00;\n> +\n> + case _SC_LEVEL1_DCACHE_ASSOC:\n> + ecx >>= 16;\n> + if ((ecx & 0xff) == 0xff)\n> + {\n> + /* Fully associative. */\n> + return (ecx << 2) & 0x3fc00;\n> + }\n> + return ecx & 0xff;\n> +\n> + case _SC_LEVEL1_DCACHE_LINESIZE:\n> + return ecx & 0xff;\n> +\n> + case _SC_LEVEL2_CACHE_SIZE:\n> + return (ecx & 0xf000) == 0 ? 0 : (ecx >> 6) & 0x3fffc00;\n> +\n> + case _SC_LEVEL2_CACHE_ASSOC:\n> + switch ((ecx >> 12) & 0xf)\n> + {\n> + case 0:\n> + case 1:\n> + case 2:\n> + case 4:\n> + return (ecx >> 12) & 0xf;\n> + case 6:\n> + return 8;\n> + case 8:\n> + return 16;\n> + case 10:\n> + return 32;\n> + case 11:\n> + return 48;\n> + case 12:\n> + return 64;\n> + case 13:\n> + return 96;\n> + case 14:\n> + return 128;\n> + case 15:\n> + return ((ecx >> 6) & 0x3fffc00) / (ecx & 0xff);\n> + default:\n> + return 0;\n> + }\n> +\n> + case _SC_LEVEL2_CACHE_LINESIZE:\n> + return (ecx & 0xf000) == 0 ? 0 : ecx & 0xff;\n> +\n> + case _SC_LEVEL3_CACHE_SIZE:\n> + {\n> + long int total_l3_cache = 0, l3_cache_per_thread = 0;\n> + unsigned int threads = 0;\n> +\n> + if ((edx & 0xf000) == 0)\n> + return 0;\n> +\n> + total_l3_cache = (edx & 0x3ffc0000) << 1;\n> +\n> + /* Figure out the number of logical threads that share L3. */\n> + if (max_cpuid >= 0x80000008)\n> + {\n> + /* Get width of APIC ID. */\n> + __cpuid (0x80000008, eax, ebx, ecx, edx);\n> + threads = (ecx & 0xff) + 1;\n> + }\n> +\n> + if (threads == 0)\n> + {\n> + /* If APIC ID width is not available, use logical\n> + processor count. */\n> + __cpuid (0x00000001, eax, ebx, ecx, edx);\n> + if ((edx & (1 << 28)) != 0)\n> + threads = (ebx >> 16) & 0xff;\n> + }\n> +\n> + /* Cap usage of highest cache level to the number of\n> + supported threads. */\n> + if (threads > 0)\n> + l3_cache_per_thread = total_l3_cache/threads;\n> +\n> + /* Get shared cache per ccx. */\n> + /* Get number of threads share the L3 cache in CCX. */\n> + __cpuid_count (0x8000001D, 0x3, eax, ebx, ecx, edx);\n> + unsigned int threads_per_ccx = ((eax >> 14) & 0xfff) + 1;\n> + long int l3_cache_per_ccx = l3_cache_per_thread * threads_per_ccx;\n> + return l3_cache_per_ccx;\n> + }\n> +\n> case _SC_LEVEL3_CACHE_ASSOC:\n> - return ((ebx >> 22) & 0x3ff) + 1;\n> - case _SC_LEVEL1_ICACHE_LINESIZE:\n> - case _SC_LEVEL1_DCACHE_LINESIZE:\n> - case _SC_LEVEL2_CACHE_LINESIZE:\n> + switch ((edx >> 12) & 0xf)\n> + {\n> + case 0:\n> + case 1:\n> + case 2:\n> + case 4:\n> + return (edx >> 12) & 0xf;\n> + case 6:\n> + return 8;\n> + case 8:\n> + return 16;\n> + case 10:\n> + return 32;\n> + case 11:\n> + return 48;\n> + case 12:\n> + return 64;\n> + case 13:\n> + return 96;\n> + case 14:\n> + return 128;\n> + case 15:\n> + return ((edx & 0x3ffc0000) << 1) / (edx & 0xff);\n> + default:\n> + return 0;\n> + }\n> +\n> case _SC_LEVEL3_CACHE_LINESIZE:\n> - return (ebx & 0xfff) + 1;\n> - case _SC_LEVEL1_ICACHE_SIZE:\n> - case _SC_LEVEL1_DCACHE_SIZE:\n> - case _SC_LEVEL2_CACHE_SIZE:\n> - case _SC_LEVEL3_CACHE_SIZE:\n> - return (((ebx >> 22) & 0x3ff) + 1) * ((ebx & 0xfff) + 1) * (ecx + 1);\n> + return (edx & 0xf000) == 0 ? 0 : edx & 0xff;\n> +\n> default:\n> __builtin_unreachable ();\n> }\n> --\n> 2.43.0\n>\n>\n\nLGTM.\n\nReviewed-by: H.J. Lu \n\nThanks.","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","libc-alpha@sourceware.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","libc-alpha@sourceware.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=TDHeOG9v;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org\n (client-ip=38.145.34.32; helo=vm01.sourceware.org;\n envelope-from=libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org;\n receiver=patchwork.ozlabs.org)","sourceware.org;\n\tdkim=pass (2048-bit key,\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=TDHeOG9v","sourceware.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com","sourceware.org; spf=pass smtp.mailfrom=gmail.com","server2.sourceware.org;\n arc=pass smtp.remote-ip=2607:f8b0:4864:20::530"],"Received":["from vm01.sourceware.org (vm01.sourceware.org [38.145.34.32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dyZgW65kVz1xt1\n\tfor ; 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Fri, 23 Jan 2026\n 15:59:56 -0800 (PST)","MIME-Version":"1.0","References":"<20260116074425.1208705-1-xiejiamei@hygon.cn>\n <20260116074425.1208705-2-xiejiamei@hygon.cn>","In-Reply-To":"<20260116074425.1208705-2-xiejiamei@hygon.cn>","From":"\"H.J. Lu\" ","Date":"Sat, 24 Jan 2026 07:59:20 +0800","X-Gm-Features":"AZwV_QiMenFobCHCImRjc1XrUtADKYgLyPQ5_xasa2ing6ykyRscYnbkONTNG-A","Message-ID":"\n ","Subject":"Re: [PATCH v2 1/1] x86: Fix for cache computation on Hygon under\n hypervisors","To":"Jiamei Xie ","Cc":"libc-alpha@sourceware.org, lijing@hygon.cn","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","X-BeenThere":"libc-alpha@sourceware.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Libc-alpha mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org"}},{"id":3645606,"web_url":"http://patchwork.ozlabs.org/comment/3645606/","msgid":"<5a298f09d430468bbd0736c06bf5e537@hygon.cn>","list_archive_url":null,"date":"2026-02-04T02:03:44","subject":"RE: [PATCH v2 1/1] x86: Fix for cache computation on Hygon under\n hypervisors","submitter":{"id":91872,"url":"http://patchwork.ozlabs.org/api/people/91872/","name":"Jiamei Xie","email":"xiejiamei@hygon.cn"},"content":"Hi\n\nJust a gentle ping on this patch. It has already received a Reviewed-by,\nbut hasn’t been merged into master yet.\n\nI’ve checked and it applies cleanly on current master.\nPlease let me know if anything else is needed from my side.\n\nBest regards,\nJiamei\n\n> -----Original Message-----\n> From: H.J. Lu \n> Sent: 2026年1月24日 7:59\n> To: Jiamei Xie \n> Cc: libc-alpha@sourceware.org; Jing Li \n> Subject: Re: [PATCH v2 1/1] x86: Fix for cache computation on Hygon under\n> hypervisors\n> \n> On Fri, Jan 16, 2026 at 3:46 PM Jiamei Xie wrote:\n> >\n> > On Hygon CPUs, glibc currently relies on CPUID leaf 0x8000001D to\n> > compute cache parameters. This works correctly on bare-metal systems.\n> > However, under some hypervisors (e.g. QEMU with -cpu qemu64), the\n> > maximum supported extended CPUID leaf is only 0x8000000A, and CPUID\n> > 0x8000001D is not exposed. In this case, cache information computed\n> > via 0x8000001D is zeroed out.\n> >\n> > This patch introduces legacy fallback of cache computation based on\n> > CPUID 0x80000005 and 0x80000006, consistent with the AMD\n> > implementation, to restore correct cache information under such\n> > environments.\n> >\n> > Signed-off-by: Jiamei Xie \n> > ---\n> > sysdeps/x86/dl-cacheinfo.h | 201\n> > +++++++++++++++++++++++++++++++++----\n> > 1 file changed, 179 insertions(+), 22 deletions(-)\n> >\n> > diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h\n> > index b6520bddaa..d2d4301bc7 100644\n> > --- a/sysdeps/x86/dl-cacheinfo.h\n> > +++ b/sysdeps/x86/dl-cacheinfo.h\n> > @@ -585,35 +585,192 @@ handle_hygon (int name)\n> > unsigned int ebx;\n> > unsigned int ecx;\n> > unsigned int edx;\n> > - unsigned int count = 0x1;\n> > + unsigned int max_cpuid = 0;\n> > +\n> > + /* No level 4 cache (yet). */\n> > + if (name > _SC_LEVEL3_CACHE_LINESIZE)\n> > + return 0;\n> > +\n> > + __cpuid (0x80000000, max_cpuid, ebx, ecx, edx);\n> > +\n> > + if (max_cpuid >= 0x8000001D)\n> > + /* Use __cpuid__ '0x8000_001D' to compute cache details. */\n> > + {\n> > + unsigned int count = 0x1;\n> >\n> > - if (name >= _SC_LEVEL3_CACHE_SIZE)\n> > - count = 0x3;\n> > - else if (name >= _SC_LEVEL2_CACHE_SIZE)\n> > - count = 0x2;\n> > - else if (name >= _SC_LEVEL1_DCACHE_SIZE)\n> > - count = 0x0;\n> > + if (name >= _SC_LEVEL3_CACHE_SIZE)\n> > + count = 0x3;\n> > + else if (name >= _SC_LEVEL2_CACHE_SIZE)\n> > + count = 0x2;\n> > + else if (name >= _SC_LEVEL1_DCACHE_SIZE)\n> > + count = 0x0;\n> > +\n> > + __cpuid_count (0x8000001D, count, eax, ebx, ecx, edx);\n> >\n> > - /* Use __cpuid__ '0x8000_001D' to compute cache details. */\n> > - __cpuid_count (0x8000001D, count, eax, ebx, ecx, edx);\n> > + if (ecx != 0)\n> > + {\n> > + switch (name)\n> > + {\n> > + case _SC_LEVEL1_ICACHE_ASSOC:\n> > + case _SC_LEVEL1_DCACHE_ASSOC:\n> > + case _SC_LEVEL2_CACHE_ASSOC:\n> > + case _SC_LEVEL3_CACHE_ASSOC:\n> > + return ((ebx >> 22) & 0x3ff) + 1;\n> > + case _SC_LEVEL1_ICACHE_LINESIZE:\n> > + case _SC_LEVEL1_DCACHE_LINESIZE:\n> > + case _SC_LEVEL2_CACHE_LINESIZE:\n> > + case _SC_LEVEL3_CACHE_LINESIZE:\n> > + return (ebx & 0xfff) + 1;\n> > + case _SC_LEVEL1_ICACHE_SIZE:\n> > + case _SC_LEVEL1_DCACHE_SIZE:\n> > + case _SC_LEVEL2_CACHE_SIZE:\n> > + case _SC_LEVEL3_CACHE_SIZE:\n> > + return (((ebx >> 22) & 0x3ff) + 1) * ((ebx & 0xfff) + 1) * (ecx\n> + 1);\n> > + default:\n> > + __builtin_unreachable ();\n> > + }\n> > + return -1;\n> > + }\n> > + }\n> > +\n> > + /* Legacy cache computation for some hypervisors that\n> > + accidentally configure __cpuid__ '0x8000_001D' to Zero. */\n> > +\n> > + unsigned int fn = 0x80000005 + (name >= _SC_LEVEL2_CACHE_SIZE);\n> > +\n> > + if (max_cpuid < fn)\n> > + return 0;\n> > +\n> > + __cpuid (fn, eax, ebx, ecx, edx);\n> > +\n> > + if (name < _SC_LEVEL1_DCACHE_SIZE)\n> > + {\n> > + name += _SC_LEVEL1_DCACHE_SIZE - _SC_LEVEL1_ICACHE_SIZE;\n> > + ecx = edx;\n> > + }\n> >\n> > switch (name)\n> > {\n> > - case _SC_LEVEL1_ICACHE_ASSOC:\n> > - case _SC_LEVEL1_DCACHE_ASSOC:\n> > - case _SC_LEVEL2_CACHE_ASSOC:\n> > + case _SC_LEVEL1_DCACHE_SIZE:\n> > + return (ecx >> 14) & 0x3fc00;\n> > +\n> > + case _SC_LEVEL1_DCACHE_ASSOC:\n> > + ecx >>= 16;\n> > + if ((ecx & 0xff) == 0xff)\n> > + {\n> > + /* Fully associative. */\n> > + return (ecx << 2) & 0x3fc00;\n> > + }\n> > + return ecx & 0xff;\n> > +\n> > + case _SC_LEVEL1_DCACHE_LINESIZE:\n> > + return ecx & 0xff;\n> > +\n> > + case _SC_LEVEL2_CACHE_SIZE:\n> > + return (ecx & 0xf000) == 0 ? 0 : (ecx >> 6) & 0x3fffc00;\n> > +\n> > + case _SC_LEVEL2_CACHE_ASSOC:\n> > + switch ((ecx >> 12) & 0xf)\n> > + {\n> > + case 0:\n> > + case 1:\n> > + case 2:\n> > + case 4:\n> > + return (ecx >> 12) & 0xf;\n> > + case 6:\n> > + return 8;\n> > + case 8:\n> > + return 16;\n> > + case 10:\n> > + return 32;\n> > + case 11:\n> > + return 48;\n> > + case 12:\n> > + return 64;\n> > + case 13:\n> > + return 96;\n> > + case 14:\n> > + return 128;\n> > + case 15:\n> > + return ((ecx >> 6) & 0x3fffc00) / (ecx & 0xff);\n> > + default:\n> > + return 0;\n> > + }\n> > +\n> > + case _SC_LEVEL2_CACHE_LINESIZE:\n> > + return (ecx & 0xf000) == 0 ? 0 : ecx & 0xff;\n> > +\n> > + case _SC_LEVEL3_CACHE_SIZE:\n> > + {\n> > + long int total_l3_cache = 0, l3_cache_per_thread = 0;\n> > + unsigned int threads = 0;\n> > +\n> > + if ((edx & 0xf000) == 0)\n> > + return 0;\n> > +\n> > + total_l3_cache = (edx & 0x3ffc0000) << 1;\n> > +\n> > + /* Figure out the number of logical threads that share L3. */\n> > + if (max_cpuid >= 0x80000008)\n> > + {\n> > + /* Get width of APIC ID. */\n> > + __cpuid (0x80000008, eax, ebx, ecx, edx);\n> > + threads = (ecx & 0xff) + 1;\n> > + }\n> > +\n> > + if (threads == 0)\n> > + {\n> > + /* If APIC ID width is not available, use logical\n> > + processor count. */\n> > + __cpuid (0x00000001, eax, ebx, ecx, edx);\n> > + if ((edx & (1 << 28)) != 0)\n> > + threads = (ebx >> 16) & 0xff;\n> > + }\n> > +\n> > + /* Cap usage of highest cache level to the number of\n> > + supported threads. */\n> > + if (threads > 0)\n> > + l3_cache_per_thread = total_l3_cache/threads;\n> > +\n> > + /* Get shared cache per ccx. */\n> > + /* Get number of threads share the L3 cache in CCX. */\n> > + __cpuid_count (0x8000001D, 0x3, eax, ebx, ecx, edx);\n> > + unsigned int threads_per_ccx = ((eax >> 14) & 0xfff) + 1;\n> > + long int l3_cache_per_ccx = l3_cache_per_thread *\n> threads_per_ccx;\n> > + return l3_cache_per_ccx;\n> > + }\n> > +\n> > case _SC_LEVEL3_CACHE_ASSOC:\n> > - return ((ebx >> 22) & 0x3ff) + 1;\n> > - case _SC_LEVEL1_ICACHE_LINESIZE:\n> > - case _SC_LEVEL1_DCACHE_LINESIZE:\n> > - case _SC_LEVEL2_CACHE_LINESIZE:\n> > + switch ((edx >> 12) & 0xf)\n> > + {\n> > + case 0:\n> > + case 1:\n> > + case 2:\n> > + case 4:\n> > + return (edx >> 12) & 0xf;\n> > + case 6:\n> > + return 8;\n> > + case 8:\n> > + return 16;\n> > + case 10:\n> > + return 32;\n> > + case 11:\n> > + return 48;\n> > + case 12:\n> > + return 64;\n> > + case 13:\n> > + return 96;\n> > + case 14:\n> > + return 128;\n> > + case 15:\n> > + return ((edx & 0x3ffc0000) << 1) / (edx & 0xff);\n> > + default:\n> > + return 0;\n> > + }\n> > +\n> > case _SC_LEVEL3_CACHE_LINESIZE:\n> > - return (ebx & 0xfff) + 1;\n> > - case _SC_LEVEL1_ICACHE_SIZE:\n> > - case _SC_LEVEL1_DCACHE_SIZE:\n> > - case _SC_LEVEL2_CACHE_SIZE:\n> > - case _SC_LEVEL3_CACHE_SIZE:\n> > - return (((ebx >> 22) & 0x3ff) + 1) * ((ebx & 0xfff) + 1) * (ecx + 1);\n> > + return (edx & 0xf000) == 0 ? 0 : edx & 0xff;\n> > +\n> > default:\n> > __builtin_unreachable ();\n> > }\n> > --\n> > 2.43.0\n> >\n> >\n> \n> LGTM.\n> \n> Reviewed-by: H.J. Lu \n> \n> Thanks.\n> \n> --\n> H.J.","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","libc-alpha@sourceware.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","libc-alpha@sourceware.org"],"Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org\n (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org;\n envelope-from=libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org;\n receiver=patchwork.ozlabs.org)","sourceware.org;\n dmarc=pass (p=none dis=none) header.from=hygon.cn","sourceware.org; spf=pass smtp.mailfrom=hygon.cn","server2.sourceware.org;\n arc=none smtp.remote-ip=101.204.27.37"],"Received":["from vm01.sourceware.org (vm01.sourceware.org\n [IPv6:2620:52:6:3111::32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f5Nx363blz1xtH\n\tfor ; Wed, 04 Feb 2026 13:05:42 +1100 (AEDT)","from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id ED7B14BA2E0A\n\tfor ; Wed, 4 Feb 2026 02:05:34 +0000 (GMT)","from mailgw2.hygon.cn (unknown [101.204.27.37])\n by sourceware.org (Postfix) with ESMTP id 0FBF94BA2E17\n for ; Wed, 4 Feb 2026 02:03:48 +0000 (GMT)","from maildlp2.hygon.cn (unknown [127.0.0.1])\n by mailgw2.hygon.cn (Postfix) with ESMTP id 4f5Ntm2cPCz1Ygxjd;\n Wed, 4 Feb 2026 10:03:44 +0800 (CST)","from maildlp2.hygon.cn (unknown [172.23.18.61])\n by mailgw2.hygon.cn (Postfix) with ESMTP id 4f5Ntm07nVz1Ygxjd;\n Wed, 4 Feb 2026 10:03:44 +0800 (CST)","from cncheex04.Hygon.cn (unknown [172.23.18.114])\n by maildlp2.hygon.cn (Postfix) with ESMTPS id EF29E30195C6;\n Wed, 4 Feb 2026 10:03:12 +0800 (CST)","from cncheex04.Hygon.cn (172.23.18.114) by cncheex04.Hygon.cn\n (172.23.18.114) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.36; Wed, 4 Feb\n 2026 10:03:44 +0800","from cncheex04.Hygon.cn ([fe80::1b6f:6c58:58a4:430d]) by\n cncheex04.Hygon.cn ([fe80::1b6f:6c58:58a4:430d%10]) with mapi id\n 15.02.1544.036; Wed, 4 Feb 2026 10:03:44 +0800"],"DKIM-Filter":["OpenDKIM Filter v2.11.0 sourceware.org ED7B14BA2E0A","OpenDKIM Filter v2.11.0 sourceware.org 0FBF94BA2E17"],"DMARC-Filter":"OpenDMARC Filter v1.4.2 sourceware.org 0FBF94BA2E17","ARC-Filter":"OpenARC Filter v1.0.0 sourceware.org 0FBF94BA2E17","ARC-Seal":"i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1770170628; cv=none;\n b=pLOaKa3qlwIW6MHdK4CvIpVo9pgP+LzuNz3MBRa3wV3heA8Js7/7fYlaJLqJ70DTBU2K0gsa/WrTzt0WGJI9cMk1i4s1QUnzFoSos+boqQnCSmH1S7IqNeFB7p4/7XPbWReOvKhOlFh5X6SIcg+vdjTaUkXc9fo+oTCqNhWv+H4=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1770170628; c=relaxed/simple;\n bh=6KTesd/2j6/Z3e008butNj8vhGHISHw/XZLzUEWsHts=;\n h=From:To:Subject:Date:Message-ID:MIME-Version;\n b=mRZiaAyZ5QUgXz+D/w4XmpoWUVopbZkSnMJBFvw827GSKv+fKQNwpnrt9PhsHFdqK79oKpQVzm7GQCAeswqz63n5HwtFy/xNnugl3YnqjfaDtaS3uiykMAe/ourMzNogfJ3bTv+nT9l9ObPwKn5iOxufKs6u/7E58RrsC37n1Gc=","ARC-Authentication-Results":"i=1; server2.sourceware.org","From":"Jiamei Xie ","To":"\"H.J. Lu\" ","CC":"\"libc-alpha@sourceware.org\" , Jing Li\n ","Subject":"RE: [PATCH v2 1/1] x86: Fix for cache computation on Hygon under\n hypervisors","Thread-Topic":"[PATCH v2 1/1] x86: Fix for cache computation on Hygon under\n hypervisors","Thread-Index":"AQHchrwSUXspFDdx6EyD7ZL+Ben1ALVf9P8AgBHxdQA=","Date":"Wed, 4 Feb 2026 02:03:44 +0000","Message-ID":"<5a298f09d430468bbd0736c06bf5e537@hygon.cn>","References":"<20260116074425.1208705-1-xiejiamei@hygon.cn>\n <20260116074425.1208705-2-xiejiamei@hygon.cn>\n ","In-Reply-To":"\n ","Accept-Language":"zh-CN, en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[172.19.21.15]","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","MIME-Version":"1.0","X-BeenThere":"libc-alpha@sourceware.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Libc-alpha mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org"}},{"id":3645708,"web_url":"http://patchwork.ozlabs.org/comment/3645708/","msgid":"","list_archive_url":null,"date":"2026-02-04T08:47:20","subject":"Re: [PATCH v2 1/1] x86: Fix for cache computation on Hygon under\n hypervisors","submitter":{"id":14312,"url":"http://patchwork.ozlabs.org/api/people/14312/","name":"Florian Weimer","email":"fweimer@redhat.com"},"content":"* Jiamei Xie:\n\n> Just a gentle ping on this patch. It has already received a Reviewed-by,\n> but hasn’t been merged into master yet.\n>\n> I’ve checked and it applies cleanly on current master.\n> Please let me know if anything else is needed from my side.\n\nI've pushed it for you.\n\nThanks,\nFlorian","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","libc-alpha@sourceware.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","libc-alpha@sourceware.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=mimecast20190719 header.b=VxNc1iOE;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org\n (client-ip=38.145.34.32; helo=vm01.sourceware.org;\n envelope-from=libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org;\n receiver=patchwork.ozlabs.org)","sourceware.org;\n\tdkim=pass (1024-bit key,\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=mimecast20190719 header.b=VxNc1iOE","sourceware.org; dmarc=pass (p=quarantine dis=none)\n header.from=redhat.com","sourceware.org; spf=pass smtp.mailfrom=redhat.com","server2.sourceware.org;\n arc=none smtp.remote-ip=170.10.133.124"],"Received":["from vm01.sourceware.org (unknown [38.145.34.32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f5YsH0Yxmz1xpg\n\tfor ; Wed, 04 Feb 2026 19:48:03 +1100 (AEDT)","from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id 2296F4BA2E0A\n\tfor ; Wed, 4 Feb 2026 08:48:01 +0000 (GMT)","from us-smtp-delivery-124.mimecast.com\n (us-smtp-delivery-124.mimecast.com [170.10.133.124])\n by sourceware.org (Postfix) with ESMTP id CA15A4BA2E1B\n for ; Wed, 4 Feb 2026 08:47:30 +0000 (GMT)","from mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com\n (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by\n relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3,\n cipher=TLS_AES_256_GCM_SHA384) id us-mta-88-l-WVnA-RO92yZbgBHjnc6A-1; Wed,\n 04 Feb 2026 03:47:27 -0500","from mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com\n (mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.93])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest\n SHA256)\n (No client certificate requested)\n by mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS\n id BA41018003FC; Wed, 4 Feb 2026 08:47:25 +0000 (UTC)","from fweimer-oldenburg.csb.redhat.com (unknown [10.44.32.172])\n by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with\n ESMTPS\n id 40F471800464; Wed, 4 Feb 2026 08:47:23 +0000 (UTC)"],"DKIM-Filter":["OpenDKIM Filter v2.11.0 sourceware.org 2296F4BA2E0A","OpenDKIM Filter v2.11.0 sourceware.org CA15A4BA2E1B"],"DMARC-Filter":"OpenDMARC Filter v1.4.2 sourceware.org CA15A4BA2E1B","ARC-Filter":"OpenARC Filter v1.0.0 sourceware.org CA15A4BA2E1B","ARC-Seal":"i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1770194850; cv=none;\n b=ximPB2gt11XvRidBSkTQn43sw0InmO1ZZl4FMBnLtRXgWa3z1TQzfQcstoYtnMev9lLAk7btkiAVdf9tE0bbAMOirsp1Vx5OieSrjvRzbBwliUiYw8rewGAhaRX73AxiQWgXI0irCInQCy7fSmK+84lC1203FrWgLnNbs6+X0dU=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1770194850; c=relaxed/simple;\n bh=jndXmcZzesBPikkK6qaeETmHsOz1KMotVkvwabi2NX8=;\n h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version;\n b=LyzM3AeqR3n+iSWH5bMSytra9/u4htBiPYNwt8WCpVtNISEfUbQrZcExSHLSu/aDDdo/S7PYdluzyWMJg+kUYusgeofAtux0xH+iYvO9y2xa+wGBpKgIEp3n/CuZAZOT7gvj0k6l6kMupMGshYnXHUHhNwca6zHkXTMau+Foe9M=","ARC-Authentication-Results":"i=1; server2.sourceware.org","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com;\n s=mimecast20190719; t=1770194850;\n h=from:from:reply-to:subject:subject:date:date:message-id:message-id:\n to:to:cc:cc:mime-version:mime-version:content-type:content-type:\n content-transfer-encoding:content-transfer-encoding:\n in-reply-to:in-reply-to:references:references;\n bh=jndXmcZzesBPikkK6qaeETmHsOz1KMotVkvwabi2NX8=;\n b=VxNc1iOEyKGnrdyZK46K1mQo8VcUUt5MkKVRahdsSG4wG+wtm+tZ0t/yyJhxyurAxM2XwX\n wmb3fGlOt7Tx/0Rb+PvcmKQFurVnf4gmg341a4c5te5Isiw98punmZn75wk1In56YNkuCf\n KDJnXPRcQuM4bp+zIWPKSYOfv7fBE8Q=","X-MC-Unique":"l-WVnA-RO92yZbgBHjnc6A-1","X-Mimecast-MFC-AGG-ID":"l-WVnA-RO92yZbgBHjnc6A_1770194846","From":"Florian Weimer ","To":"Jiamei Xie ","Cc":"\"H.J. Lu\" , \"libc-alpha@sourceware.org\"\n , Jing Li ","Subject":"Re: [PATCH v2 1/1] x86: Fix for cache computation on Hygon under\n hypervisors","In-Reply-To":"<5a298f09d430468bbd0736c06bf5e537@hygon.cn> (Jiamei Xie's message\n of \"Wed, 4 Feb 2026 02:03:44 +0000\")","References":"<20260116074425.1208705-1-xiejiamei@hygon.cn>\n <20260116074425.1208705-2-xiejiamei@hygon.cn>\n \n <5a298f09d430468bbd0736c06bf5e537@hygon.cn>","Date":"Wed, 04 Feb 2026 09:47:20 +0100","Message-ID":"","User-Agent":"Gnus/5.13 (Gnus v5.13)","MIME-Version":"1.0","X-Scanned-By":"MIMEDefang 3.4.1 on 10.30.177.93","X-Mimecast-Spam-Score":"0","X-Mimecast-MFC-PROC-ID":"ymwmsaXkkIeR62YsPP8ns5lAmO4S2nHLlzp3s2UC8pk_1770194846","X-Mimecast-Originator":"redhat.com","Content-Type":"text/plain; charset=utf-8","Content-Transfer-Encoding":"quoted-printable","X-BeenThere":"libc-alpha@sourceware.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Libc-alpha mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org"}}]