{"id":2137031,"url":"http://patchwork.ozlabs.org/api/patches/2137031/","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250915080157.28195-8-clamor95@gmail.com/","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/projects/37/","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20250915080157.28195-8-clamor95@gmail.com>","list_archive_url":null,"date":"2025-09-15T08:01:53","name":"[v3,07/11] dt-bindings: memory: Document Tegra114 External Memory Controller","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":false,"hash":"ee48530f4eccda301d673bca3a0abe5a36e617c2","submitter":{"id":84146,"url":"http://patchwork.ozlabs.org/api/people/84146/","name":"Svyatoslav Ryhel","email":"clamor95@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250915080157.28195-8-clamor95@gmail.com/mbox/","series":[{"id":473641,"url":"http://patchwork.ozlabs.org/api/series/473641/","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=473641","date":"2025-09-15T08:01:46","name":"Tegra114: implement EMC support","version":3,"mbox":"http://patchwork.ozlabs.org/series/473641/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2137031/comments/","check":"success","checks":"http://patchwork.ozlabs.org/api/patches/2137031/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming-dt@patchwork.ozlabs.org","devicetree@vger.kernel.org"],"Delivered-To":"patchwork-incoming-dt@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=bnyvOUm6;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2604:1380:45e3:2400::1; helo=sv.mirrors.kernel.org;\n envelope-from=devicetree+bounces-217260-incoming-dt=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com\n header.b=\"bnyvOUm6\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=209.85.167.50","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=gmail.com"],"Received":["from sv.mirrors.kernel.org (sv.mirrors.kernel.org\n [IPv6:2604:1380:45e3:2400::1])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4cQHcD57t9z1y1Y\n\tfor ;\n Mon, 15 Sep 2025 18:04:12 +1000 (AEST)","from smtp.subspace.kernel.org (relay.kernel.org [52.25.139.140])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby sv.mirrors.kernel.org (Postfix) with ESMTPS id 766BE3BDA8E\n\tfor ; Mon, 15 Sep 2025 08:04:11 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 12E0D2EA728;\n\tMon, 15 Sep 2025 08:02:37 +0000 (UTC)","from mail-lf1-f50.google.com (mail-lf1-f50.google.com\n [209.85.167.50])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 56F5B2EC541\n\tfor ; Mon, 15 Sep 2025 08:02:33 +0000 (UTC)","by mail-lf1-f50.google.com with SMTP id\n 2adb3069b0e04-5607a240c75so3949858e87.2\n for ;\n Mon, 15 Sep 2025 01:02:33 -0700 (PDT)","from xeon.. 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These are the registers (see\n- section \"15.6.2 EMC Registers\" in the TRM) whose values need to\n+ section \"20.11.2 EMC Registers\" in the Tegra114 TRM or section\n+ \"15.6.2 EMC Registers\" in the Tegra124 TRM) whose values need to\n be specified, according to the board documentation.\n $ref: /schemas/types.yaml#/definitions/uint32-array\n- items:\n- - description: EMC_RC\n- - description: EMC_RFC\n- - description: EMC_RFC_SLR\n- - description: EMC_RAS\n- - description: EMC_RP\n- - description: EMC_R2W\n- - description: EMC_W2R\n- - description: EMC_R2P\n- - description: EMC_W2P\n- - description: EMC_RD_RCD\n- - description: EMC_WR_RCD\n- - description: EMC_RRD\n- - description: EMC_REXT\n- - description: EMC_WEXT\n- - description: EMC_WDV\n- - description: EMC_WDV_MASK\n- - description: EMC_QUSE\n- - description: EMC_QUSE_WIDTH\n- - description: EMC_IBDLY\n- - description: EMC_EINPUT\n- - description: EMC_EINPUT_DURATION\n- - description: EMC_PUTERM_EXTRA\n- - description: EMC_PUTERM_WIDTH\n- - description: EMC_PUTERM_ADJ\n- - description: EMC_CDB_CNTL_1\n- - description: EMC_CDB_CNTL_2\n- - description: EMC_CDB_CNTL_3\n- - description: EMC_QRST\n- - description: EMC_QSAFE\n- - description: EMC_RDV\n- - description: EMC_RDV_MASK\n- - description: EMC_REFRESH\n- - description: EMC_BURST_REFRESH_NUM\n- - description: EMC_PRE_REFRESH_REQ_CNT\n- - description: EMC_PDEX2WR\n- - description: EMC_PDEX2RD\n- - description: EMC_PCHG2PDEN\n- - description: EMC_ACT2PDEN\n- - description: EMC_AR2PDEN\n- - description: EMC_RW2PDEN\n- - description: EMC_TXSR\n- - description: EMC_TXSRDLL\n- - description: EMC_TCKE\n- - description: EMC_TCKESR\n- - description: EMC_TPD\n- - description: EMC_TFAW\n- - description: EMC_TRPAB\n- - description: EMC_TCLKSTABLE\n- - description: EMC_TCLKSTOP\n- - description: EMC_TREFBW\n- - description: EMC_FBIO_CFG6\n- - description: EMC_ODT_WRITE\n- - description: EMC_ODT_READ\n- - description: EMC_FBIO_CFG5\n- - description: EMC_CFG_DIG_DLL\n- - description: EMC_CFG_DIG_DLL_PERIOD\n- - description: EMC_DLL_XFORM_DQS0\n- - description: EMC_DLL_XFORM_DQS1\n- - description: EMC_DLL_XFORM_DQS2\n- - description: EMC_DLL_XFORM_DQS3\n- - description: EMC_DLL_XFORM_DQS4\n- - description: EMC_DLL_XFORM_DQS5\n- - description: EMC_DLL_XFORM_DQS6\n- - description: EMC_DLL_XFORM_DQS7\n- - description: EMC_DLL_XFORM_DQS8\n- - description: EMC_DLL_XFORM_DQS9\n- - description: EMC_DLL_XFORM_DQS10\n- - description: EMC_DLL_XFORM_DQS11\n- - description: EMC_DLL_XFORM_DQS12\n- - description: EMC_DLL_XFORM_DQS13\n- - description: EMC_DLL_XFORM_DQS14\n- - description: EMC_DLL_XFORM_DQS15\n- - description: EMC_DLL_XFORM_QUSE0\n- - description: EMC_DLL_XFORM_QUSE1\n- - description: EMC_DLL_XFORM_QUSE2\n- - description: EMC_DLL_XFORM_QUSE3\n- - description: EMC_DLL_XFORM_QUSE4\n- - description: EMC_DLL_XFORM_QUSE5\n- - description: EMC_DLL_XFORM_QUSE6\n- - description: EMC_DLL_XFORM_QUSE7\n- - description: EMC_DLL_XFORM_ADDR0\n- - description: EMC_DLL_XFORM_ADDR1\n- - description: EMC_DLL_XFORM_ADDR2\n- - description: EMC_DLL_XFORM_ADDR3\n- - description: EMC_DLL_XFORM_ADDR4\n- - description: EMC_DLL_XFORM_ADDR5\n- - description: EMC_DLL_XFORM_QUSE8\n- - description: EMC_DLL_XFORM_QUSE9\n- - description: EMC_DLL_XFORM_QUSE10\n- - description: EMC_DLL_XFORM_QUSE11\n- - description: EMC_DLL_XFORM_QUSE12\n- - description: EMC_DLL_XFORM_QUSE13\n- - description: EMC_DLL_XFORM_QUSE14\n- - description: EMC_DLL_XFORM_QUSE15\n- - description: EMC_DLI_TRIM_TXDQS0\n- - description: EMC_DLI_TRIM_TXDQS1\n- - description: EMC_DLI_TRIM_TXDQS2\n- - description: EMC_DLI_TRIM_TXDQS3\n- - description: EMC_DLI_TRIM_TXDQS4\n- - description: EMC_DLI_TRIM_TXDQS5\n- - description: EMC_DLI_TRIM_TXDQS6\n- - description: EMC_DLI_TRIM_TXDQS7\n- - description: EMC_DLI_TRIM_TXDQS8\n- - description: EMC_DLI_TRIM_TXDQS9\n- - description: EMC_DLI_TRIM_TXDQS10\n- - description: EMC_DLI_TRIM_TXDQS11\n- - description: EMC_DLI_TRIM_TXDQS12\n- - description: EMC_DLI_TRIM_TXDQS13\n- - description: EMC_DLI_TRIM_TXDQS14\n- - description: EMC_DLI_TRIM_TXDQS15\n- - description: EMC_DLL_XFORM_DQ0\n- - description: EMC_DLL_XFORM_DQ1\n- - description: EMC_DLL_XFORM_DQ2\n- - description: EMC_DLL_XFORM_DQ3\n- - description: EMC_DLL_XFORM_DQ4\n- - description: EMC_DLL_XFORM_DQ5\n- - description: EMC_DLL_XFORM_DQ6\n- - description: EMC_DLL_XFORM_DQ7\n- - description: EMC_XM2CMDPADCTRL\n- - description: EMC_XM2CMDPADCTRL4\n- - description: EMC_XM2CMDPADCTRL5\n- - description: EMC_XM2DQPADCTRL2\n- - description: EMC_XM2DQPADCTRL3\n- - description: EMC_XM2CLKPADCTRL\n- - description: EMC_XM2CLKPADCTRL2\n- - description: EMC_XM2COMPPADCTRL\n- - description: EMC_XM2VTTGENPADCTRL\n- - description: EMC_XM2VTTGENPADCTRL2\n- - description: EMC_XM2VTTGENPADCTRL3\n- - description: EMC_XM2DQSPADCTRL3\n- - description: EMC_XM2DQSPADCTRL4\n- - description: EMC_XM2DQSPADCTRL5\n- - description: EMC_XM2DQSPADCTRL6\n- - description: EMC_DSR_VTTGEN_DRV\n- - description: EMC_TXDSRVTTGEN\n- - description: EMC_FBIO_SPARE\n- - description: EMC_ZCAL_WAIT_CNT\n- - description: EMC_MRS_WAIT_CNT2\n- - description: EMC_CTT\n- - description: EMC_CTT_DURATION\n- - description: EMC_CFG_PIPE\n- - description: EMC_DYN_SELF_REF_CONTROL\n- - description: EMC_QPOP\n \n required:\n - clock-frequency\n@@ -318,9 +180,7 @@ patternProperties:\n - nvidia,emc-auto-cal-config2\n - nvidia,emc-auto-cal-config3\n - nvidia,emc-auto-cal-interval\n- - nvidia,emc-bgbias-ctl0\n - nvidia,emc-cfg\n- - nvidia,emc-cfg-2\n - nvidia,emc-ctt-term-ctrl\n - nvidia,emc-mode-1\n - nvidia,emc-mode-2\n@@ -344,6 +204,281 @@ required:\n - \"#interconnect-cells\"\n - operating-points-v2\n \n+allOf:\n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ enum:\n+ - nvidia,tegra114-emc\n+ then:\n+ patternProperties:\n+ \"^emc-timings-[0-9]+$\":\n+ patternProperties:\n+ \"^timing-[0-9]+$\":\n+ properties:\n+ nvidia,emc-configuration:\n+ items:\n+ - description: EMC_RC\n+ - description: EMC_RFC\n+ - description: EMC_RAS\n+ - description: EMC_RP\n+ - description: EMC_R2W\n+ - description: EMC_W2R\n+ - description: EMC_R2P\n+ - description: EMC_W2P\n+ - description: EMC_RD_RCD\n+ - description: EMC_WR_RCD\n+ - description: EMC_RRD\n+ - description: EMC_REXT\n+ - description: EMC_WEXT\n+ - description: EMC_WDV\n+ - description: EMC_WDV_MASK\n+ - description: EMC_QUSE\n+ - description: EMC_IBDLY\n+ - description: EMC_EINPUT\n+ - description: EMC_EINPUT_DURATION\n+ - description: EMC_PUTERM_EXTRA\n+ - description: EMC_CDB_CNTL_1\n+ - description: EMC_CDB_CNTL_2\n+ - description: EMC_QRST\n+ - description: EMC_QSAFE\n+ - description: EMC_RDV\n+ - description: EMC_RDV_MASK\n+ - description: EMC_REFRESH\n+ - description: EMC_BURST_REFRESH_NUM\n+ - description: EMC_PRE_REFRESH_REQ_CNT\n+ - description: EMC_PDEX2WR\n+ - description: EMC_PDEX2RD\n+ - description: EMC_PCHG2PDEN\n+ - description: EMC_ACT2PDEN\n+ - description: EMC_AR2PDEN\n+ - description: EMC_RW2PDEN\n+ - description: EMC_TXSR\n+ - description: EMC_TXSRDLL\n+ - description: EMC_TCKE\n+ - description: EMC_TCKESR\n+ - description: EMC_TPD\n+ - description: EMC_TFAW\n+ - description: EMC_TRPAB\n+ - description: EMC_TCLKSTABLE\n+ - description: EMC_TCLKSTOP\n+ - description: EMC_TREFBW\n+ - description: EMC_QUSE_EXTRA\n+ - description: EMC_FBIO_CFG6\n+ - description: EMC_ODT_WRITE\n+ - description: EMC_ODT_READ\n+ - description: EMC_FBIO_CFG5\n+ - description: EMC_CFG_DIG_DLL\n+ - description: EMC_CFG_DIG_DLL_PERIOD\n+ - description: EMC_DLL_XFORM_DQS0\n+ - description: EMC_DLL_XFORM_DQS1\n+ - description: EMC_DLL_XFORM_DQS2\n+ - description: EMC_DLL_XFORM_DQS3\n+ - description: EMC_DLL_XFORM_DQS4\n+ - description: EMC_DLL_XFORM_DQS5\n+ - description: EMC_DLL_XFORM_DQS6\n+ - description: EMC_DLL_XFORM_DQS7\n+ - description: EMC_DLL_XFORM_QUSE0\n+ - description: EMC_DLL_XFORM_QUSE1\n+ - description: EMC_DLL_XFORM_QUSE2\n+ - description: EMC_DLL_XFORM_QUSE3\n+ - description: EMC_DLL_XFORM_QUSE4\n+ - description: EMC_DLL_XFORM_QUSE5\n+ - description: EMC_DLL_XFORM_QUSE6\n+ - description: EMC_DLL_XFORM_QUSE7\n+ - description: EMC_DLI_TRIM_TXDQS0\n+ - description: EMC_DLI_TRIM_TXDQS1\n+ - description: EMC_DLI_TRIM_TXDQS2\n+ - description: EMC_DLI_TRIM_TXDQS3\n+ - description: EMC_DLI_TRIM_TXDQS4\n+ - description: EMC_DLI_TRIM_TXDQS5\n+ - description: EMC_DLI_TRIM_TXDQS6\n+ - description: EMC_DLI_TRIM_TXDQS7\n+ - description: EMC_DLL_XFORM_DQ0\n+ - description: EMC_DLL_XFORM_DQ1\n+ - description: EMC_DLL_XFORM_DQ2\n+ - description: EMC_DLL_XFORM_DQ3\n+ - description: EMC_XM2CMDPADCTRL\n+ - description: EMC_XM2CMDPADCTRL4\n+ - description: EMC_XM2DQPADCTRL2\n+ - description: EMC_XM2CLKPADCTRL\n+ - description: EMC_XM2COMPPADCTRL\n+ - description: EMC_XM2VTTGENPADCTRL\n+ - description: EMC_XM2VTTGENPADCTRL2\n+ - description: EMC_XM2DQSPADCTRL3\n+ - description: EMC_XM2DQSPADCTRL4\n+ - description: EMC_DSR_VTTGEN_DRV\n+ - description: EMC_TXDSRVTTGEN\n+ - description: EMC_FBIO_SPARE\n+ - description: EMC_ZCAL_WAIT_CNT\n+ - description: EMC_MRS_WAIT_CNT2\n+ - description: EMC_CTT\n+ - description: EMC_CTT_DURATION\n+ - description: EMC_DYN_SELF_REF_CONTROL\n+\n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ enum:\n+ - nvidia,tegra124-emc\n+ then:\n+ patternProperties:\n+ \"^emc-timings-[0-9]+$\":\n+ patternProperties:\n+ \"^timing-[0-9]+$\":\n+ properties:\n+ nvidia,emc-configuration:\n+ items:\n+ - description: EMC_RC\n+ - description: EMC_RFC\n+ - description: EMC_RFC_SLR\n+ - description: EMC_RAS\n+ - description: EMC_RP\n+ - description: EMC_R2W\n+ - description: EMC_W2R\n+ - description: EMC_R2P\n+ - description: EMC_W2P\n+ - description: EMC_RD_RCD\n+ - description: EMC_WR_RCD\n+ - description: EMC_RRD\n+ - description: EMC_REXT\n+ - description: EMC_WEXT\n+ - description: EMC_WDV\n+ - description: EMC_WDV_MASK\n+ - description: EMC_QUSE\n+ - description: EMC_QUSE_WIDTH\n+ - description: EMC_IBDLY\n+ - description: EMC_EINPUT\n+ - description: EMC_EINPUT_DURATION\n+ - description: EMC_PUTERM_EXTRA\n+ - description: EMC_PUTERM_WIDTH\n+ - description: EMC_PUTERM_ADJ\n+ - description: EMC_CDB_CNTL_1\n+ - description: EMC_CDB_CNTL_2\n+ - description: EMC_CDB_CNTL_3\n+ - description: EMC_QRST\n+ - description: EMC_QSAFE\n+ - description: EMC_RDV\n+ - description: EMC_RDV_MASK\n+ - description: EMC_REFRESH\n+ - description: EMC_BURST_REFRESH_NUM\n+ - description: EMC_PRE_REFRESH_REQ_CNT\n+ - description: EMC_PDEX2WR\n+ - description: EMC_PDEX2RD\n+ - description: EMC_PCHG2PDEN\n+ - description: EMC_ACT2PDEN\n+ - description: EMC_AR2PDEN\n+ - description: EMC_RW2PDEN\n+ - description: EMC_TXSR\n+ - description: EMC_TXSRDLL\n+ - description: EMC_TCKE\n+ - description: EMC_TCKESR\n+ - description: EMC_TPD\n+ - description: EMC_TFAW\n+ - description: EMC_TRPAB\n+ - description: EMC_TCLKSTABLE\n+ - description: EMC_TCLKSTOP\n+ - description: EMC_TREFBW\n+ - description: EMC_FBIO_CFG6\n+ - description: EMC_ODT_WRITE\n+ - description: EMC_ODT_READ\n+ - description: EMC_FBIO_CFG5\n+ - description: EMC_CFG_DIG_DLL\n+ - description: EMC_CFG_DIG_DLL_PERIOD\n+ - description: EMC_DLL_XFORM_DQS0\n+ - description: EMC_DLL_XFORM_DQS1\n+ - description: EMC_DLL_XFORM_DQS2\n+ - description: EMC_DLL_XFORM_DQS3\n+ - description: EMC_DLL_XFORM_DQS4\n+ - description: EMC_DLL_XFORM_DQS5\n+ - description: EMC_DLL_XFORM_DQS6\n+ - description: EMC_DLL_XFORM_DQS7\n+ - description: EMC_DLL_XFORM_DQS8\n+ - description: EMC_DLL_XFORM_DQS9\n+ - description: EMC_DLL_XFORM_DQS10\n+ - description: EMC_DLL_XFORM_DQS11\n+ - description: EMC_DLL_XFORM_DQS12\n+ - description: EMC_DLL_XFORM_DQS13\n+ - description: EMC_DLL_XFORM_DQS14\n+ - description: EMC_DLL_XFORM_DQS15\n+ - description: EMC_DLL_XFORM_QUSE0\n+ - description: EMC_DLL_XFORM_QUSE1\n+ - description: EMC_DLL_XFORM_QUSE2\n+ - description: EMC_DLL_XFORM_QUSE3\n+ - description: EMC_DLL_XFORM_QUSE4\n+ - description: EMC_DLL_XFORM_QUSE5\n+ - description: EMC_DLL_XFORM_QUSE6\n+ - description: EMC_DLL_XFORM_QUSE7\n+ - description: EMC_DLL_XFORM_ADDR0\n+ - description: EMC_DLL_XFORM_ADDR1\n+ - description: EMC_DLL_XFORM_ADDR2\n+ - description: EMC_DLL_XFORM_ADDR3\n+ - description: EMC_DLL_XFORM_ADDR4\n+ - description: EMC_DLL_XFORM_ADDR5\n+ - description: EMC_DLL_XFORM_QUSE8\n+ - description: EMC_DLL_XFORM_QUSE9\n+ - description: EMC_DLL_XFORM_QUSE10\n+ - description: EMC_DLL_XFORM_QUSE11\n+ - description: EMC_DLL_XFORM_QUSE12\n+ - description: EMC_DLL_XFORM_QUSE13\n+ - description: EMC_DLL_XFORM_QUSE14\n+ - description: EMC_DLL_XFORM_QUSE15\n+ - description: EMC_DLI_TRIM_TXDQS0\n+ - description: EMC_DLI_TRIM_TXDQS1\n+ - description: EMC_DLI_TRIM_TXDQS2\n+ - description: EMC_DLI_TRIM_TXDQS3\n+ - description: EMC_DLI_TRIM_TXDQS4\n+ - description: EMC_DLI_TRIM_TXDQS5\n+ - description: EMC_DLI_TRIM_TXDQS6\n+ - description: EMC_DLI_TRIM_TXDQS7\n+ - description: EMC_DLI_TRIM_TXDQS8\n+ - description: EMC_DLI_TRIM_TXDQS9\n+ - description: EMC_DLI_TRIM_TXDQS10\n+ - description: EMC_DLI_TRIM_TXDQS11\n+ - description: EMC_DLI_TRIM_TXDQS12\n+ - description: EMC_DLI_TRIM_TXDQS13\n+ - description: EMC_DLI_TRIM_TXDQS14\n+ - description: EMC_DLI_TRIM_TXDQS15\n+ - description: EMC_DLL_XFORM_DQ0\n+ - description: EMC_DLL_XFORM_DQ1\n+ - description: EMC_DLL_XFORM_DQ2\n+ - description: EMC_DLL_XFORM_DQ3\n+ - description: EMC_DLL_XFORM_DQ4\n+ - description: EMC_DLL_XFORM_DQ5\n+ - description: EMC_DLL_XFORM_DQ6\n+ - description: EMC_DLL_XFORM_DQ7\n+ - description: EMC_XM2CMDPADCTRL\n+ - description: EMC_XM2CMDPADCTRL4\n+ - description: EMC_XM2CMDPADCTRL5\n+ - description: EMC_XM2DQPADCTRL2\n+ - description: EMC_XM2DQPADCTRL3\n+ - description: EMC_XM2CLKPADCTRL\n+ - description: EMC_XM2CLKPADCTRL2\n+ - description: EMC_XM2COMPPADCTRL\n+ - description: EMC_XM2VTTGENPADCTRL\n+ - description: EMC_XM2VTTGENPADCTRL2\n+ - description: EMC_XM2VTTGENPADCTRL3\n+ - description: EMC_XM2DQSPADCTRL3\n+ - description: EMC_XM2DQSPADCTRL4\n+ - description: EMC_XM2DQSPADCTRL5\n+ - description: EMC_XM2DQSPADCTRL6\n+ - description: EMC_DSR_VTTGEN_DRV\n+ - description: EMC_TXDSRVTTGEN\n+ - description: EMC_FBIO_SPARE\n+ - description: EMC_ZCAL_WAIT_CNT\n+ - description: EMC_MRS_WAIT_CNT2\n+ - description: EMC_CTT\n+ - description: EMC_CTT_DURATION\n+ - description: EMC_CFG_PIPE\n+ - description: EMC_DYN_SELF_REF_CONTROL\n+ - description: EMC_QPOP\n+\n+ required:\n+ - nvidia,emc-bgbias-ctl0\n+ - nvidia,emc-cfg-2\n+\n additionalProperties: false\n \n examples:\n","prefixes":["v3","07/11"]}